JPH05136183A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH05136183A JPH05136183A JP3325175A JP32517591A JPH05136183A JP H05136183 A JPH05136183 A JP H05136183A JP 3325175 A JP3325175 A JP 3325175A JP 32517591 A JP32517591 A JP 32517591A JP H05136183 A JPH05136183 A JP H05136183A
- Authority
- JP
- Japan
- Prior art keywords
- power element
- lead frame
- circuit device
- copper lead
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims abstract description 19
- 239000010949 copper Substances 0.000 claims abstract description 19
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 12
- 239000011733 molybdenum Substances 0.000 claims abstract description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 230000008646 thermal stress Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、例えば自動車用電装
品に使用する集積回路装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device used for, for example, electric components for automobiles.
【０００２】[0002]
【従来の技術】図３は従来技術による半導体装置の断面
図である。図において、１は放熱板を兼ねた銅リードフ
レーム、２はＳｉ単結晶でなるパワー素子であり、銅リ
ードフレーム１はパワー素子２の放熱効果を上げるた
め、引出しリード側とは厚みを異にする異厚材となって
いる。３はパワー素子２を取付けるための半田材、４は
パワー素子２に電流を流すリードで、通常アルミ線が使
用される。５はモールドされた樹脂である。2. Description of the Related Art FIG. 3 is a sectional view of a conventional semiconductor device. In the figure, 1 is a copper lead frame that also serves as a heat sink, 2 is a power element made of Si single crystal, and the copper lead frame 1 has a different thickness from the lead-out lead side in order to enhance the heat radiation effect of the power element 2. It is a different thickness material. Reference numeral 3 is a solder material for attaching the power element 2, and 4 is a lead for supplying a current to the power element 2, and usually an aluminum wire is used. 5 is a molded resin.
【０００３】図３のリードフレームは図２に示す例の如
く、引出しリード側は、数本に分かれているが、その先
端は予めタイバー部として整列固定されている。図２，
図３はそのタイバー部を切り落とした形状である。パワ
ー素子２は熱伝導率の高い銅材であるリードフレーム１
に半田３により融着され、次にアルミ線４を通常超音波
によりパワー素子２に接合し、樹脂５によりモールドパ
ッケージされる。The lead frame shown in FIG. 3 is divided into several pieces on the lead-out lead side as in the example shown in FIG. 2, but the tip ends thereof are aligned and fixed in advance as tie bars. Figure 2,
FIG. 3 shows a shape in which the tie bar portion is cut off. The power element 2 is a lead frame 1 which is a copper material having high thermal conductivity.
Then, the aluminum wire 4 is bonded to the power element 2 usually by ultrasonic waves, and the resin wire 5 is molded and packaged.
【０００４】[0004]
【発明が解決しようとする課題】この従来装置の構造の
ものでは、Ｓｉ単結晶で出来ているパワー素子２と銅リ
ードフレーム１の熱膨張係数の差による熱ストレスがパ
ワー素子２に不具合を生じさせることや、接合に使用し
ている半田３にクラック等の不具合を与える等の問題点
があった。In the structure of this conventional device, the thermal stress due to the difference in thermal expansion coefficient between the power element 2 made of Si single crystal and the copper lead frame 1 causes a problem in the power element 2. There is a problem in that the solder 3 used for joining is given a defect such as a crack.
【０００５】この発明は上記のような問題点を解消する
ためになされたもので、熱ストレスの発生を緩和させ、
パワー素子への熱ストレスを低減し、また半田クラック
等の発生を防止した集積回路装置を得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and alleviates the occurrence of heat stress.
An object of the present invention is to obtain an integrated circuit device in which thermal stress on a power element is reduced and solder cracks and the like are prevented from occurring.
【０００６】[0006]
【課題を解決するための手段】この発明に係る集積回路
装置は、パワー素子と銅リードフレーム間に、熱膨張係
数が銅より小さいモリブデンを挟んで半田付けし、パワ
ー素子の材料であるシリコンと銅の熱膨張係数の差によ
る熱ストレスを緩和するものである。In the integrated circuit device according to the present invention, molybdenum having a coefficient of thermal expansion smaller than that of copper is sandwiched between a power element and a copper lead frame for soldering, and silicon is used as a material for the power element. It reduces the thermal stress due to the difference in the thermal expansion coefficient of copper.
【０００７】[0007]
【作用】この発明において、熱変化による熱ストレスの
発生は、銅リードフレームが支配的であり、その熱スト
レスのパワー素子への直接的影響を熱膨張係数が銅より
小さいモリブデンが緩和する。In the present invention, the occurrence of thermal stress due to thermal change is dominated by the copper lead frame, and molybdenum having a thermal expansion coefficient smaller than that of copper reduces the direct influence of the thermal stress on the power element.
【０００８】[0008]
【実施例】実施例１．以下、この発明の一実施例を図に
ついて説明する。図１，図２において、６は制御ＩＣチ
ップ、７は通常Ａｕ細線、８はモリブデン板である。こ
のモリブデン板８は例えば両面銀メッキが施され、半田
の濡れを良くしている。また銅リードフレーム１も銀メ
ッキ等が施され、制御用ＩＣチップ６等と共に半田濡れ
対策が施されている。チップ類のダイボンド、ワイヤボ
ンドの後、パワー素子２、制御ＩＣチップ６は一体型モ
ールド５でパッケージされる。その他の構成は従来のも
のと同様である。EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 and 2, 6 is a control IC chip, 7 is a normal Au thin wire, and 8 is a molybdenum plate. The molybdenum plate 8 is plated with silver on both sides, for example, to improve solder wetting. Further, the copper lead frame 1 is also plated with silver or the like, and measures against solder wetting are taken together with the control IC chip 6 and the like. After die bonding and wire bonding of chips, the power element 2 and the control IC chip 6 are packaged by the integral mold 5. Other configurations are the same as the conventional ones.
【０００９】各材料の熱膨張係数（×１０-6/℃）は、
銅１７、半田（９５％Ｐｂ）２８.７、モリブデン５.
１，シリコン３.５であるため、シリコンからなるパワ
ー素子２と銅リードフレーム１の熱膨張の差をモリブデ
ン板８が緩和する。なお、制御ＩＣチップ６については
発熱量が少ないから、モリブデン板を必要としない。The coefficient of thermal expansion (× 10 −6 / ° C.) of each material is
Copper 17, solder (95% Pb) 28.7, molybdenum 5.
1 and 3.5, the molybdenum plate 8 alleviates the difference in thermal expansion between the power element 2 made of silicon and the copper lead frame 1. The control IC chip 6 does not require a molybdenum plate because it generates a small amount of heat.
【００１０】[0010]
【発明の効果】以上のようにこの発明によれば、パワー
素子と銅リードフレームの熱膨張係数の差による熱スト
レスを、モリブデン板が緩和するので、パワー素子の不
具合を防止出来、信頼性の高いものが得られる効果があ
る。As described above, according to the present invention, since the molybdenum plate alleviates the thermal stress due to the difference in the thermal expansion coefficient between the power element and the copper lead frame, the power element can be prevented from being defective and the reliability can be improved. There is an effect that a high price can be obtained.
【図１】この発明の一実施例によるパワー素子、制御Ｉ
Ｃ一体型混成集積回路装置の側面断面図を示す。FIG. 1 is a power device according to an embodiment of the present invention, control I
The side sectional view of a C integrated hybrid integrated circuit device is shown.
【図２】この発明の斜視図を示す。FIG. 2 shows a perspective view of the present invention.
【図３】従来技術の側面断面図を示す。FIG. 3 shows a side sectional view of the prior art.
１ 銅リードフレーム ２ パワー素子 ３ 半田 ４ アルミ線 ５ モールド樹脂 ６ 制御ＩＣチップ ７ Ａｕ細線 ８ モリブデン板 1 Copper Lead Frame 2 Power Element 3 Solder 4 Aluminum Wire 5 Mold Resin 6 Control IC Chip 7 Au Fine Wire 8 Molybdenum Plate
Claims (1)
付けされた集積回路装置において、パワー素子と銅リー
ドフレーム上にモリブデン板を半田付けし、さらにこの
モリブデン板上にパワー素子を半田付けしたことを特徴
とする集積回路装置。1. An integrated circuit device in which a power element is soldered on a copper lead frame, a molybdenum plate is soldered on the power element and the copper lead frame, and the power element is further soldered on the molybdenum plate. An integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3325175A JPH05136183A (en) | 1991-11-12 | 1991-11-12 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3325175A JPH05136183A (en) | 1991-11-12 | 1991-11-12 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05136183A true JPH05136183A (en) | 1993-06-01 |
Family
ID=18173850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3325175A Pending JPH05136183A (en) | 1991-11-12 | 1991-11-12 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05136183A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997035347A1 (en) * | 1996-03-20 | 1997-09-25 | Siemens Aktiengesellschaft | Semiconductor device |
| JP2007088264A (en) * | 2005-09-22 | 2007-04-05 | Toshiba Components Co Ltd | Resin sealed semiconductor device |
| JP2018018952A (en) * | 2016-07-28 | 2018-02-01 | 三菱電機株式会社 | Semiconductor device |
-
1991
- 1991-11-12 JP JP3325175A patent/JPH05136183A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997035347A1 (en) * | 1996-03-20 | 1997-09-25 | Siemens Aktiengesellschaft | Semiconductor device |
| JP2007088264A (en) * | 2005-09-22 | 2007-04-05 | Toshiba Components Co Ltd | Resin sealed semiconductor device |
| JP2018018952A (en) * | 2016-07-28 | 2018-02-01 | 三菱電機株式会社 | Semiconductor device |
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