JPH0473912B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a static induction phototransistor (Static
Induction Phototransistor (hereinafter referred to as SIPT)
This relates to a signal readout method for a solid-state imaging device using
In the signal readout method in the Y address method,
The SIPT provides a low power consumption, high speed, large capacity solid-state imaging device that detects images stably and uniformly using a method in which all of the main electrodes of the SIPT function as address lines or signal readout lines. It can be applied to television cameras, etc., which take advantage of its high sensitivity, to video cameras for astronomical observation, and can also be applied to still cameras, etc., for taking still images.

[Conventional technology]

2 by gate accumulation method using conventional SIPT
Regarding the configuration and signal readout method of a two-dimensional solid-state imaging device in which the source and drain of the SIPT are signal readout lines and address lines, respectively, please refer to Japanese Patent Application Laid-Open No. 1987-199277 “Two-dimensional Solid-State Imaging Device”. Disclosed. The disclosed signal readout method will first be described below as a conventional example.

FIG. 3a shows an example of the construction method of this example, and FIG. 3b shows an example of the operating pulse. One pixel C _ij of a two-dimensional solid-state imaging device consists of one PIPT and a gate capacitor. The drain of SIPT of pixel C _ij is connected to the signal readout line S _i , the source is connected to the embedded line BL _j ,
The vertical address gate line GL _j is connected to the gate of SIPT through a gate capacitor C _G .
A precharge transistor Q _Pi is connected to the signal readout line SL _i , and is connected to a precharge power supply V _P through this Q _Pi . This Q _Pi has a common gate, and a precharge pulse φ _P is applied. Furthermore, SL _i is a transfer transistor
Connected to transfer line TL _i through Q _Ti ,
TL _i is connected to a switch transistor Q _Si . Q _Ti has a common gate and transfer pulse φ _T is applied. The gate of Q _Si is led to a horizontal shift register 32. Q _Si is the load resistance R _L
The output is connected to the video power supply V _V through Q _Ti and
It is obtained from the V _put terminal by the voltage drop of R _L due to the capacitor G _Li commonly connected to Q _Si being made conductive and being charged by V _V. Further, the buried line BL _j is grounded through the buried line selection transistor Q _Bj , and the gate of Q _Bj connected to BL _j is connected to GL _j , _which is led to the vertical shift register 31.

The reading method will be explained with reference to FIG. 3b. First, when the transfer transistor Q _Ti is conductive due to the transfer pulse φ _T , the signal readout line SL _i and the capacitors C _SLi and C _TLi are connected through the precharge transistor Q _Pi by the precharge pulse φ _P. is charged by V _P.
Next, each of the pixels C _1j to C _oj connected to the vertical address line GL _j by the vertical address pulse φ _Gj
SIPT generates a discharge according to the amount of incident light. By simultaneously cutting off φ _Gj and φ _T , the optical information of the pixels C _1j to _{C oj} is stored as the discharge amount of the capacitor C _TL . Read pulse φ _s1 from horizontal shift register 32
~φ _so allows outputs to be obtained sequentially from the V _put terminal.

[Problem that the invention seeks to solve]

The two-dimensional solid-state imaging device using the above-mentioned SIPT is
This makes it possible to take advantage of the inherent high sensitivity of SIPT.
In other words, the image C _1j ~ C _oj on the vertical address line GL _j
The source of each SIPT constituting the SIPT is connected to a common buried line BL _j , and a buried line selection transistor Q _Bj is connected between BL _j and ground, and the gate of Q _Bj is connected to a vertical address line GL _j. By connecting them, only BL _j becomes the ground potential at the same time as the vertical address line GL _j is selected, suppressing crosstalk between pixels on the same signal readout line.

However, a SIPT with higher sensitivity is a SIPT that is close to normal-on, and a SIPT of a pixel that receives light close to the saturated light amount, even when not selected,
Leakage current is large. Configuring a two-dimensional solid-state imaging device using such highly sensitive SIPT using the method described above means that although the source of the SIPT that constitutes the non-selected pixels is separated from the ground by Q _Bj , Since the buried line has a certain capacitance with respect to ground, a discharge to the extent that this capacitance is heavily charged can occur. For example, when the incident light is close to the saturation light intensity, the potential of the signal readout line is this BL _j
It fluctuates depending on the leakage current that charges the capacitance of the battery. For this reason, in the above-mentioned two-dimensional solid-state imaging device, in order to minimize the voltage fluctuation of the signal readout line due to unselected pixels, the capacitance of the buried line to the ground is kept low, and the timing of the vertical address pulse and transfer pulse after precharging is adjusted. In addition to optimization, there are also limitations in the design conditions of SIPT, which prevents SIPT from being used under extremely sensitive conditions.

[Means for solving problems]

In the two-dimensional solid-state imaging device described above, although the source of SIPT of an unselected pixel is separated from the ground potential by a transistor,
Embedded line to which the SIPT source is connected
Since BL _j has a capacitance with respect to the ground, for example, when a saturated amount of incident light hits, discharge to the extent that the capacitance of this BL _j with respect to the ground is charged is unavoidable. Therefore, in the signal readout method for a solid-state imaging device of the present invention, the embedded line BL _j is charged at the same time as the signal readout line. Thereafter, only the buried line of the column to be read is set to the ground potential at the same time as the vertical address. In other words, the capacitance of the embedded line BL _j relative to the ground is charged in advance. For this purpose, two switch transistors are connected to the embedded line BL _j , one connected to the precharge power supply and the other grounded.

Next, the principle of the reading method according to the present invention will be explained using FIG.

FIG. 2a shows a readout circuit for one pixel of the solid-state imaging device according to the present invention, and FIG. 2b shows a pulse timing chart of the readout operation, the potential change of the transfer line _{TL i} , and the potential change of the output terminal 25. shows. In Figure 2a, one pixel C _ij is
It consists of a SIPT20 and a gate capacitor _CG24 , the drain 21 of SIPT20 is connected to the signal readout line SL _i , the source 22 of SIPT20 is connected to the buried line _BLj , and the gate 23 of SIPT20 is connected to the vertical address gate line GL through the gate capacitor _CG24 . connected to _j . A precharge transistor Q _Pi and a transfer transistor Q _Ti are connected to the signal readout line SL _i , and
Q _Ti includes a switch transistor Q _Si and a load resistor R _L
The output terminal V _put 25 is connected to the video power supply V _V via the load resistor R _L and connected to the Q _Si of the load resistor R L . A precharge pulse φ _P is applied to the gate of Q _Pi .
A transfer pulse φ _T is applied to the gate of Q _Ti , and a read pulse φ _si is applied to the gate of Q _Si . The buried line BL _j is grounded through a buried line selection transistor Q _Bj and connected to a precharge power supply through a switch transistor Q _Hj . The gate of Q _Bj is connected to GL _j , and BL _j is grounded by φ _Gj . Q _Hj
A precharge pulse φ _P is applied to the gate of
BL _j is precharged to the same potential at the same time as SL _j . C _SLi represents the capacitance that the signal readout line SL _j has with respect to the ground, and C _TLi represents the capacitance that the transfer line TL _i has with respect to the ground.

In FIG. 2b, at time t ₁ , the transfer transistor is first activated by the transfer pulse φ _Ti .
Q _Ti becomes conductive, and transfer line TL _i is coupled to signal readout line SL _i . Next, at time t ₂ , the precharge pulse φ _Pi connects the precharge transistor Q _Pi and the buried line.
Switch transistor Q _Hj of BL _j becomes conductive, and SL _i , capacitor C _TLi and BL _j are precharged by precharge voltage _VP . at time t ₃
After Q _Pi enters the cut-off state, a vertical address pulse φ _Gj is applied at time t ₄ . At this time, the buried line is at ground potential and the SIPT 20 is biased. At the same time, SIPT20 is gate capacitor C _G 2
Vertical address palace φ _Gj is added through 4,
A discharge current flows through the SIPT 20 in accordance with the amount of light incident on the SIPT 20 within a certain period. At time _t5 , φ _Ti and φ _Gj are cut off, and Q _Ti is cut off, causing SIPT20
The optical information of the pixel C _ij obtained from is stored in C _TLi . Next, at time _t6 , the read pulse φ _Si turns on the switch transistor Q _Si , and the video voltage V _V charges C _TLi through the load resistor R _L , and an output is obtained. At this time, V _put changes according to the value of V _TLi : dotted line c when the light incident on the pixel C _ij is in a dark state, dashed line b when it is normal light irradiation, and solid line a when the amount of light is saturated. It will look like this.

[Effect]

In the signal readout method for a solid-state imaging device of the present invention, the embedded line is charged at the same time as the signal readout line. That is, the capacitance of the embedded line relative to the ground is charged in advance. Thereafter, by setting only the buried line of the column to be read out to the ground potential at the same time as the vertical address, it is possible to bias only the column to be read out, and it is possible to suppress the influence on V _SL by pixels on the same signal readout line. Therefore, a large-capacity two-dimensional solid-state imaging device can be read out stably.

〔Example〕

An embodiment of the signal readout method for a solid-state imaging device according to the present invention is shown in FIG. 1, and an example of a device structure for one pixel is shown in FIG.

First, the configuration of a two-dimensional solid-state imaging device will be described with reference to FIG. 1a.

One of the n×m pixels arranged in a two-dimensional matrix, C _ij , has one SIPT and a gate capacitor.
Consists of C _G. The drain of the SIPT of this pixel C _ij is connected to the signal readout line SL _i , the source is connected to the embedded line BL _j , and the gate is connected to the vertical address line GL _j via the gate capacitor _CG . BL _j and
GL _j is parallel and perpendicular to SL _i . The signal readout line SL _i is connected to a precharge power supply V _P through a precharge transistor Q _Pi , and all the gates of Q _Pi are made common and a precharge pulse φ _P is applied. Further, SL _i is connected to a transfer line TL _i through a transfer transistor Q _Ti , and TL _i is connected to a switch transistor Q _Si . All gates of Q _Ti are made common and transfer pulse φ _T is applied. Capacitor C _SLi
C TLi represents the capacitance that SL _i has with respect to ground, and C _TLi represents the capacitance that transfer line TL _i has with respect to ground. GL _j is vertical shift register 11
A vertical address pulse φ _Gj is applied.
A read pulse φ _Si is applied to the gate of the switch transistor Q _Si through the horizontal shift register 12 . The buried line BL _j is grounded through a buried line selection transistor Q _Bj and connected to a precharge power supply V _P through a switch transistor Q _Hj . The gate of Q _Bj is connected to GL _j and φ _Gj is applied. A precharge pulse φ _P is applied to the gate of Q _Hj .

FIG. 1b shows a timing chart of read pulses. The vertical shift register sequentially outputs vertical address pulses φ _G1 , . . . , φ _{Gn ,} and _FIG . At time t ₁ , a transfer pulse φ _T enters, and the transfer transistor Q _Ti becomes conductive. At time t ₂ , a pre-charge pulse φ _P turns on the pre-charge transistor Q _P and the buried line switch transistor Q _Hj. becomes conductive,
SL _i , C _SLi and C _TLi , BL _j are precharged by the precharge voltage _VP . At time _t3 , a vertical address pulse φ _Gj is input, and at this time, the buried line is brought to the ground potential and the SIPT 10 is biased. At the same time, the vertical address pulse of SIPT10 is changed through the gate capacitor C _G4 , and the vertical address line
Each pixel C _1j , ..., C _oj on GL _j depends on the amount of incident light,
Discharge C _SL1 ,..., C _SLi and C _TL1 ,..., C _TLi . time
At t ₄ , φ _Gj is cut off at the same time as φ _T , and the optical information of C _1j , ..., C _oj is stored in the corresponding C _TL1 , ..., C _TLi , respectively. After φ _T expires, the horizontal shift register generates read pulses φ _s1 ,..., φ _so , which sequentially conducts the switch transistors Q _s1 ,..., Q _{so so} that the video voltage V _V is changed to C through the load resistor R _L . Charge _{the TL} ,
The outputs of C _1j , . . . , C _oj are sequentially output as changes in the potential of V _put . In this way, C _1j , ..., C _oj by time t ₈
After outputting one horizontal row of light information, next C _1j+1 ,
..., the same procedure is repeated to read out the optical information of C _oj+1 .

In Fig. 1a, Q _P , Q _T , Q _S , Q _B , and Q _H are all shown as MOS transistors, but they do not all need to be MOS transistors, and are SIT, bipolar transistors, It may be a JFET or the like.

4a, b, c, and d show an example of the device structure of one pixel portion. FIGS. 4e and 4f are circuit diagrams for explaining that there are two ways of configuring a matrix by erecting and inverting the SIPT, taking a 2×2 matrix as an example.

Figures 4a and 4b show the surface structure when using an inverted SIPT for one pixel device, respectively.
The cross-sectional structure taken along the line A-A' in a is schematically shown. In the device structure example shown here, an inverted n-channel SIPT is formed on a p-type Si substrate 418, a transparent electrode 411 made of polysilicon, etc., and a transparent insulating film 412 made of SiO ₂ etc.
One pixel is constituted by a MOS capacitor constituted by p ⁺ gate 416.

In FIG. 4b, n ⁺ region 414 is the drain region of SIT, n ⁺ region 415 is the source region of SIPT,
n ^- area 417 is the SIPT channel area, area 4
A separation region 13 separates each pixel. Although not shown in the figure, vertically adjacent pixels in FIG. 4a are similarly separated. drain region 4
14 is a conductive transparent electrode 419 made of polysilicon or the like.
The electrodes are taken by. An electrode 44 is removed from the surface of the buried source region 415. The gate capacitor electrode 411 is connected to a vertical address line 45 made of the same material, with a highly conductive material 46 (e.g.
(Al-Si, etc.) to reduce resistance.

In FIG. 4a, a portion corresponding to the pixel C _ij is indicated by a dash-dotted line. 45 is the vertical address line
GL _j , 44 is a buried line BL _j , and 49 is a signal read line S _i . BL _j 44 and GL _j 45 are parallel and perpendicular to SL _i 49. The intersections are insulated by an insulating material such as SiO ₂ or PSG. 42, 48, and 410 are the same materials as 46, and are provided to reduce the resistance of SL _i-1 41, GL _j+1 47, and SL _i 49, respectively.

As mentioned above, in the pixel configuration, all wiring is on the surface, so it is impossible to fabricate the precharge transistor, transfer transistor, buried line selection transistor, and switch transistor for readout on the same chip. It's easy.

Figures 4c and d show the case where the SIPT constituting one pixel is of the upright type, c shows its surface structure, and d shows the A-
The cross-sectional structure along the line indicated by A' is schematically shown. The example device structure shown here is an upright n-channel fabricated on a p-type Si substrate 438.
SIPT and transparent electrode 431 such as polysilicon
Similar to FIGS. 4a and 4b, one pixel is constituted by a MOS capacitor constituted by a transparent insulating film 432 such as SiO ₂ and a p ⁺ gate 436 of SIPT. This structure shows that the surface n ⁺ region 434 is
The source area of SIPT, the embedded n ⁺ area 435 is
It differs from Figure 4 a and b in that it becomes the drain of SIPT. n ^- area 437 is the SIPT channel area,
433 is an isolation region, 423 and 424 are electrodes in the buried region, and a highly conductive material (for example, Al-Si, etc.) 426 is on the vertical address line GL _j 425.
The resistance is reduced by 423 is the embedded line BL _j , 422 is the signal readout line SL _i
It is. 430, 428, 422 are similar substances to 426, respectively SL _j-1 429, GL _j+1 427,
This is provided to reduce the resistance of SL _j 421.

In FIG. 4e, the surface n ⁺ region 414 is used as a drain region and the n ⁺
A matrix configuration in which a buried region 415 is formed as a source region is shown. Figure 4 f
1 shows a matrix configuration in which the surface n ⁺ region 414 is formed as a source region and the n ⁺ buried region 415 is formed as a drain region. In this case, the embedded lines BL _i , BL _i+1 , etc. become signal readout lines, and the lines that commonly connect the source areas
SL _j , SL _j+1 , etc. become source lines. Address gate lines GL _j , GL _j+1 , etc. are signal readout lines
It is orthogonal to BL _i , BL _i+1 , etc.

FIG. 5 shows an embodiment in which the configuration method of FIG. 4f is applied to a two-dimensional solid-state imaging device. The SIPTs that make up the pixels of this two-dimensional solid-state imaging device are SIPTs for upright operation.
can be used, so the sensitivity is even higher than that of the embodiment shown in FIG. This is due to device operation.
This is because the rate at which electrons injected from the source reach the drain can be increased compared to the case of reverse operation (inverted operation). The rate of change (Gm) in the source-drain current caused by a change in gate potential can also be increased. The readout operation of the two-dimensional solid-state imaging device shown in FIG. 5 is basically the same as the embodiment shown in FIG.

〔Effect of the invention〕

The signal readout method of the solid-state imaging device of the present invention is as follows:
Charging the capacitance of the buried line to ground at the same time as the signal readout line,
Afterwards, by setting only the embedded line of the column to be read out to the ground potential at the same time as the vertical address, biasing only the column to be read out, even if the incident light intensity is close to the saturation light intensity, the signal readout line by the unselected pixel can be fixed. can suppress the influence on the electric potential. Therefore, a large capacity two-dimensional solid-state imaging device can be read out more stably.

FIG. 6 is a diagram for showing the effect of the present invention, and the fourth
An example of photoelectric conversion characteristics of one pixel when the pixel having the structure shown in FIG. 1 is shown in FIG. 1 is shown. The dimensions of one pixel are 65 μm×65 μm. Power supply voltage V _V =
V _P = 0.5V, load resistance R _L = 10kΩ, optical integration time T _Li
= Light with a wavelength of 655 nm (red) is irradiated for 11 ms,
The horizontal axis shows the amount of incident light P _i (μW/cm ² ), and the vertical axis shows the difference in output voltage V _put from the dark state ΔV _put (mV). These are the photoelectric conversion characteristics when _φG is 1.6V, 1.8V, and 2V. The output voltage is 1 mV at an incident light amount P _i = 6.5 × 10 ^-2 μW/cm ^{2 ,} making it possible to read out with extremely high sensitivity.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, a is a diagram showing the configuration, b is a diagram showing the readout operation waveform (when an inverted SIPT is used for one pixel), and Fig. 2 is a diagram for explaining the operation of the present invention. indicates the operation of one pixel, a is the configuration,
b is a diagram showing the readout operation waveform, FIG. 3 is a diagram for explaining the conventional technology, a is the configuration, b is a diagram showing the readout operation waveform, and FIG. 4 is an example of the structure of one pixel. Shown a and b are examples of the configuration of one pixel when SIPT is operated in an inverted position, and a shows the structure of its surface;
b is the cross-sectional structure taken along the line A-A' in a, c, d
is an example of the configuration of one pixel when SIPT is operated in the upright position, c is the structure of its surface, d is the cross-sectional structure of c along the line A-A', and e and f are the inverted operation a and the normal position, respectively. FIG. 5 is a circuit representation of the configuration corresponding to the standing action c, which is another embodiment of the present invention (one pixel, upright type).
(When using SIPT), FIG. 6 is a diagram for explaining the effects of the present invention, and is a diagram showing the photoelectric conversion characteristics of one pixel. 10... Electrostatic induction phototransistor, 1... Drain of electrostatic induction phototransistor, 2... Source of electrostatic induction phototransistor, 3... Gate of electrostatic induction phototransistor, 4... Gate capacitor, 16... Video power supply, 15...Load resistance,
17...Output terminal, 18...Precharge power supply.

Claims (1)

[Claims] 1. Pixels C _ij composed of electrostatic induction phototransistors and gate capacitors are arranged in an n×m matrix, and vertical address gate lines
GL _j (j=1 to m) is commonly connected to the gate of the electrostatic induction phototransistor constituting the pixel C _ij (i=1 to n) via the gate capacitor, and is connected to the signal readout line SLi (i=1 to n). 1 to n) are commonly connected to the drains of the electrostatic induction phototransistors constituting the pixels C _ij (j=1 to m),
The embedded line BL _j (j=1 to m) is the pixel C _ij
(i=1 to n) are commonly connected to the sources of the electrostatic induction phototransistors constituting the vertical address gate lines GL _j (j=1
~m) are vertical address pulses φ _Gj (j=
1 to m) are connected to be input, and furthermore, the signal readout line SL _i (i=1 to n)
is a predetermined capacitor C _SLi (i
= 1 to n), and the pre-charge transistor
Q _Pi (i=1 to n) are commonly connected to a predetermined precharge power supply V _p , and the gates of the precharge transistors Q _Pi (i=1 to n) are commonly input with a driving pulse φ _p . The signal readout line SL _i (i=1 to n) is connected to the transfer line TL _i (i=1 to n) via the transfer transistor Q _Ti (i=1 to n). and the transfer transistor Q _Ti (i=
The gates of the transfer lines TL i (i=1 to n) are connected to the common input of the transfer pulse φ _T , and the transfer line TL _i (i=1 to n) is connected to the ground potential by a predetermined capacitor C. _TLi (i=1~
n), and has a switch transistor Q _Si (i=1~
n) is commonly connected to the video output line through the switch transistor Q _Si (i=1~n)
The gates of each horizontal address pulse φ _Si (i=
1 to n) are connected to be input, a video power supply V _V is connected to the video output line via a load resistor R _L , and the embedded line BL _j (j = 1 to m ) is connected to the ground potential via a switch transistor Q _Bj (j=1 to m), and the switch transistor Q _Bj (j=1 to
m) gate is the vertical address gate line.
GL _j (j=1 to m), and the buried line BL _j (j=1 to m) is connected to the precharge power supply via another switch transistor Q _Hj (j=1 to m). V _P and the gate of the switch transistor Q _Hj (j=1 to m) is connected to the transfer pulse φ _T in a two-dimensional solid-state imaging device connected so that the drive pulse φ _P is input in common. By inputting the drive pulse φ P, the transfer transistor Q _Ti (i=1 to n) is made conductive, and by inputting the drive pulse φ _P , the precharge transistor Q _Pi
(i=1 to n) and the switch transistor Q _Hj (j=1 to m) are turned on, and the capacitor C TLi (i=1 to n) and the capacitor C _TLi (i=1 to n) are turned on.
After precharging C _STi (i=1 to n) to approximately the same potential as the precharge power supply V _P , the vertical address pulse φ _Gj (j=1 to m) is applied to the vertical address gate line GL _j (j=1 to m). m), one of the switch transistors Q _Bj (j=1 to m) is made conductive, and the embedded line BL _j (j
=1~m) is set to the ground potential, and at the same time, one row of the pixels C _ij (i=1~n) is selected, and the pixel C _ij
(i=1 to n), the capacitor C _TLi (i=1 to n) and the capacitor C _SLi
(i=1 to n) is discharged and the transfer transistor Q _Ti (i=1 to n) is cut off, and then the horizontal address pulse φ _Si (i=1 to
n), the switch transistor Q _Si (i=1 to n) is sequentially made conductive, and the capacitor C _TLi (i=1 to n) is charged by the video power supply V _V. The load resistance R _L
A signal readout method for a solid-state imaging device, characterized in that a potential change appearing at an output terminal due to a voltage drop is read out as optical information of a row of the pixels C _ij (i=1 to n). 2. A signal readout method for a solid-state imaging device according to claim 1, wherein the electrostatic induction phototransistor constituting each pixel according to claim 1 is of an upright type. . 3. A signal readout method for a solid-state imaging device according to claim 1, wherein the electrostatic induction phototransistor constituting each pixel according to claim 1 is of an inverted type.