JPH04367268A - Thin film transistor array device - Google Patents
Thin film transistor array deviceInfo
- Publication number
- JPH04367268A JPH04367268A JP3168996A JP16899691A JPH04367268A JP H04367268 A JPH04367268 A JP H04367268A JP 3168996 A JP3168996 A JP 3168996A JP 16899691 A JP16899691 A JP 16899691A JP H04367268 A JPH04367268 A JP H04367268A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- film transistor
- glass substrate
- array device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011521 glass Substances 0.000 claims abstract description 17
- 239000011159 matrix material Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000005611 electricity Effects 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、薄膜トランジスタアレ
イ装置に関し、特にアクティブマトリックス型カラー液
晶表示装置等に使用される薄膜トランジスタアレイ装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array device, and more particularly to a thin film transistor array device used in active matrix color liquid crystal display devices and the like.
【0002】0002
【従来の技術】図2はこの種従来の薄膜トランジスタア
レイ装置の断面図である。同図において、1はガラス基
板、2はガラス基板1の裏面全体に形成されたITO膜
、4はCr膜からなるゲート電極、5はゲート絶縁膜を
構成する窒化シリコン膜、6は活性層となるノンドープ
アモルファスシリコン膜(以下、a−Si膜と記す)、
7は、コンタクト層を構成する、高濃度にリン(P)が
ドープされたアモルファスシリコン膜(以下、n+ 型
a−Si膜と記す)、8、9は、それぞれCr膜からな
るドレイン電極とソース電極、10はITO膜からなる
画素電極、11は保護膜として全面に被着された窒化シ
リコン膜である。2. Description of the Related Art FIG. 2 is a sectional view of a conventional thin film transistor array device of this type. In the figure, 1 is a glass substrate, 2 is an ITO film formed on the entire back surface of the glass substrate 1, 4 is a gate electrode made of a Cr film, 5 is a silicon nitride film forming a gate insulating film, and 6 is an active layer. A non-doped amorphous silicon film (hereinafter referred to as a-Si film),
7 is an amorphous silicon film doped with phosphorus (P) at a high concentration (hereinafter referred to as an n+ type a-Si film) constituting a contact layer; 8 and 9 are a drain electrode and a source made of a Cr film, respectively; The electrodes 10 are pixel electrodes made of an ITO film, and 11 is a silicon nitride film deposited over the entire surface as a protective film.
【0003】ここで、基板裏面に被着されたITO膜2
は、製造工程中において、治工具、人体との接触により
ガラス基板が局部的に帯電するのを防止するために、お
よび液晶パネルに組み立てられた後に、内部デバイスを
静電シールドするために設けられた膜である。[0003] Here, the ITO film 2 deposited on the back surface of the substrate
is provided to prevent the glass substrate from becoming locally charged due to contact with jigs and the human body during the manufacturing process, and to electrostatically shield internal devices after it is assembled into an LCD panel. It is a membrane.
【0004】0004
【発明が解決しようとする課題】上述した従来の薄膜ト
ランジスタアレイ装置では、ガラス基板裏面への局部的
帯電は防ぐことはできるものの、ガラス基板上に形成さ
れる各絶縁膜へ与えられる、製造工程中での局部的帯電
は避けることができない。そのため、従来例では局部的
な過大電圧の発生が起こりやすく、デバイスの劣化や破
壊を完全に防ぐことができなかった。[Problems to be Solved by the Invention] In the conventional thin film transistor array device described above, although it is possible to prevent local charging on the back surface of the glass substrate, it is possible to prevent local charging from occurring on the back surface of the glass substrate. Localized charging cannot be avoided. Therefore, in the conventional example, localized overvoltage is likely to occur, and deterioration or destruction of the device cannot be completely prevented.
【0005】[0005]
【課題を解決するための手段】本発明の薄膜トランジス
タアレイ装置は、表面、裏面および側面に透明導電性薄
膜が形成されたガラス基板上に、絶縁膜を介して複数の
薄膜トランジスタとそれぞれの薄膜トランジスタに接続
された画素電極とを設けたものである。[Means for Solving the Problems] The thin film transistor array device of the present invention has a plurality of thin film transistors connected to each thin film transistor through an insulating film on a glass substrate having a transparent conductive thin film formed on the front, back and side surfaces. The pixel electrode is provided with a pixel electrode.
【0006】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の一実施例を示す断面図で
ある。本実施例を作製するには、まずガラス基板1上に
、スパッタ法でITO膜2を形成する。片面しか形成さ
れない通常のスパッタ装置を用いる場合、表側(素子形
成面側)と裏側との2回のスパッタが必要である。この
場合、治具の工夫により側面へもITOがスパッタされ
るようにしておく。側面については全領域に成膜される
ことが望ましいが、大部分の領域にITOが被着されそ
して表、裏面のITO膜が確実に接続されていれば、実
際上本発明の目的が損なわれることはない。Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing one embodiment of the present invention. To manufacture this example, first, an ITO film 2 is formed on a glass substrate 1 by a sputtering method. When using a normal sputtering device that can form only one side, sputtering is required twice: on the front side (element forming side) and on the back side. In this case, the jig is designed so that ITO is also sputtered onto the side surfaces. It is desirable that the film be formed on the entire side surface area, but if ITO is deposited on most areas and the ITO films on the front and back sides are securely connected, the purpose of the present invention will actually be defeated. Never.
【0007】ITO成膜時の温度は、200℃〜500
℃の範囲内で後工程の条件に応じて設定する。200℃
以下の低温でITO膜を形成してもよいが、この場合、
後の製造工程でのエッチング工程等でITO膜が除去さ
れてしまわないように、予め高温(200℃〜500℃
)でアニールしておくことが必要となる。[0007] The temperature during ITO film formation is 200°C to 500°C.
Set within the range of ℃ according to the conditions of the post-process. 200℃
The ITO film may be formed at a low temperature below, but in this case,
To prevent the ITO film from being removed during the etching process in the subsequent manufacturing process, the
) is required.
【0008】この後酸化シリコン膜3をスパッタ法で形
成し、その上にCr膜を被着し、これをパターニングし
てゲート電極4を形成し、さらにその上にプラズマCV
D法によりゲート絶縁膜となる窒化シリコン膜5を堆積
する。Thereafter, a silicon oxide film 3 is formed by sputtering, a Cr film is deposited on it, and this is patterned to form a gate electrode 4.
A silicon nitride film 5, which will become a gate insulating film, is deposited by method D.
【0009】次に、プラズマCVD法によりa−Si膜
6とn+ 型a−Si膜7とを成長させ、これを薄膜ト
ランジスタの領域としてパターニングする。続いて、C
r膜を被着しこれをパターニングしてドレイン電極8と
ソース電極9を形成し、両電極8、9間のn+ 型a−
Si膜7をエッチング除去する。Next, an a-Si film 6 and an n+ type a-Si film 7 are grown by plasma CVD and patterned to form a thin film transistor region. Next, C
A drain electrode 8 and a source electrode 9 are formed by depositing an r film and patterning it to form an n+ type a-
The Si film 7 is removed by etching.
【0010】次に、ITO膜をスパッタ法で成膜し、こ
れをパターニングして画素電極10を形成する。さらに
、保護膜となる窒化シリコン膜11をプラズマCVD法
により成長させる。Next, an ITO film is formed by sputtering and patterned to form the pixel electrode 10. Furthermore, a silicon nitride film 11 serving as a protective film is grown by plasma CVD.
【0011】本実施例においては、ITO膜で全表面が
覆われたガラス基板を用いているので、製造工程中に帯
電した治工具、人体等と接触してもガラス基板に局部的
帯電が行われることはなくなる。本実施例においても、
製造工程中に絶縁性被膜に局部的帯電がなされることは
起こりうる。しかし、比較的近傍に導電性薄膜が存在し
ていることにより、帯電は均等化されるためデバイスに
対する悪影響は回避できる。In this example, since a glass substrate whose entire surface is covered with an ITO film is used, the glass substrate will not be locally charged even if it comes into contact with charged jigs, tools, human bodies, etc. during the manufacturing process. You will no longer be exposed. Also in this example,
Localized charging of the insulating coating may occur during the manufacturing process. However, due to the presence of the conductive thin film relatively nearby, the charging is equalized, so that adverse effects on the device can be avoided.
【0012】なお、本発明は、上記実施例に限定される
ものではなく、例えばITO膜はSnO2 膜に置き替
えることができる。また、ガラス基板全面に導電性薄膜
を設けたことにより、ゲート電極と図示されていないゲ
ート電極バスラインの容量が増加するために、回路動作
上に悪影響が生じるような場合には、ゲート電極および
そのバスライン下のITO膜の一部または全部を除去す
ることができる。ドレイン電極と図示されていないドレ
インバスラインに関しても同様である。It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the ITO film can be replaced with a SnO2 film. In addition, if a conductive thin film is provided on the entire surface of the glass substrate, the capacitance of the gate electrode and the gate electrode bus line (not shown) will increase, so if the circuit operation is adversely affected, the gate electrode and Part or all of the ITO film under the bus line can be removed. The same applies to the drain electrode and the drain bus line (not shown).
【0013】[0013]
【発明の効果】以上説明したように、本発明は、透明導
電性薄膜により全面が被着されたガラス基板を用い、そ
の上に薄膜トランジスタと画素電極とを形成したもので
あるので、ガラス基板上に局部的帯電が発生することが
なくなり、また、薄膜トランジスタに関連した絶縁膜に
局部的帯電が発生した場合には速やかに放電が行われる
ので、デバイスの劣化や破壊は確実に回避できる。As explained above, the present invention uses a glass substrate whose entire surface is covered with a transparent conductive thin film, and a thin film transistor and a pixel electrode are formed on the glass substrate. Local charging will not occur in the thin film transistor, and if local charging occurs in the insulating film related to the thin film transistor, it will be discharged quickly, so deterioration and destruction of the device can be reliably avoided.
【0014】さらに、画素電極下に全面的に導電性薄膜
が形成されたことにより、画素電極の保持容量を大きく
確保することができるという副次的効果も有する。Furthermore, since a conductive thin film is formed entirely under the pixel electrode, there is also the secondary effect that a large storage capacity of the pixel electrode can be ensured.
【図1】 本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing one embodiment of the present invention.
【図2】 従来例の断面図。FIG. 2 is a sectional view of a conventional example.
1…ガラス基板、 2…ITO膜、 3…
酸化シリコン膜、 4…ゲート電極、 5
…窒化シリコン膜、 6…ノンドープアモルファ
スシリコン膜(a−Si膜)、 7…Pドープア
モルファスシリコン膜(n+ 型a−Si膜)、
8…ドレイン電極、 9…ソース電極、
10…画素電極、 11…窒化シリコン膜。1...Glass substrate, 2...ITO film, 3...
silicon oxide film, 4... gate electrode, 5
... silicon nitride film, 6... non-doped amorphous silicon film (a-Si film), 7... P-doped amorphous silicon film (n+ type a-Si film),
8...Drain electrode, 9...Source electrode,
10... Pixel electrode, 11... Silicon nitride film.
Claims (2)
膜が形成されているガラス基板と、前記ガラス基板の表
面上に形成された絶縁膜と、絶縁膜上にマトリックス状
に配置された複数の薄膜トランジスタと、各薄膜トラン
ジスタに接続された複数の画素電極と、を備えた薄膜ト
ランジスタアレイ装置。1. A glass substrate having a transparent conductive thin film formed on its front, back and side surfaces, an insulating film formed on the surface of the glass substrate, and a plurality of glass substrates arranged in a matrix on the insulating film. A thin film transistor array device including a thin film transistor and a plurality of pixel electrodes connected to each thin film transistor.
よびドレイン電極とドレイン電極バスライン下の前記透
明導電性薄膜の少なくとも一部分は除去されている請求
項1記載の薄膜トランジスタアレイ装置。2. The thin film transistor array device according to claim 1, wherein at least a portion of the transparent conductive thin film under the gate electrode and the gate electrode bus line and under the drain electrode and the drain electrode bus line are removed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3168996A JPH04367268A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor array device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3168996A JPH04367268A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor array device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04367268A true JPH04367268A (en) | 1992-12-18 |
Family
ID=15878422
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3168996A Pending JPH04367268A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor array device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04367268A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7491969B2 (en) | 2005-09-15 | 2009-02-17 | Au Optronics Corp. | Organic light emitting diode display |
CN102496625A (en) * | 2011-08-15 | 2012-06-13 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
CN102723310A (en) * | 2012-07-02 | 2012-10-10 | 深圳市华星光电技术有限公司 | Array substrate manufacturing method, array substrate and liquid crystal display device |
JP5310559B2 (en) * | 2007-10-03 | 2013-10-09 | コニカミノルタ株式会社 | Electrode manufacturing method, electronic circuit pattern, thin film transistor element and organic electroluminescence element |
US8900938B2 (en) | 2012-07-02 | 2014-12-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Manufacturing method of array substrate, array substrate and LCD device |
WO2024252675A1 (en) * | 2023-06-09 | 2024-12-12 | シャープディスプレイテクノロジー株式会社 | Method for manufacturing semiconductor device and method for manufacturing display device |
-
1991
- 1991-06-14 JP JP3168996A patent/JPH04367268A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7491969B2 (en) | 2005-09-15 | 2009-02-17 | Au Optronics Corp. | Organic light emitting diode display |
JP5310559B2 (en) * | 2007-10-03 | 2013-10-09 | コニカミノルタ株式会社 | Electrode manufacturing method, electronic circuit pattern, thin film transistor element and organic electroluminescence element |
CN102496625A (en) * | 2011-08-15 | 2012-06-13 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
US9117915B2 (en) | 2011-08-15 | 2015-08-25 | Au Optronics Corporation | Thin film transistor, pixel structure and method for fabricating the same |
CN102723310A (en) * | 2012-07-02 | 2012-10-10 | 深圳市华星光电技术有限公司 | Array substrate manufacturing method, array substrate and liquid crystal display device |
CN102723310B (en) * | 2012-07-02 | 2014-05-14 | 深圳市华星光电技术有限公司 | Array substrate manufacturing method, array substrate and liquid crystal display device |
US8900938B2 (en) | 2012-07-02 | 2014-12-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Manufacturing method of array substrate, array substrate and LCD device |
WO2024252675A1 (en) * | 2023-06-09 | 2024-12-12 | シャープディスプレイテクノロジー株式会社 | Method for manufacturing semiconductor device and method for manufacturing display device |
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