JPH04160821A - Pulse width modulator - Google Patents

Abstract

PURPOSE:To prevent deterioration in the entire conversion characteristic by applying leading edge modulation to a digital input signal and applying trailing edge modulation to a signal delaying the digital input signal by a period of word clock and adding the modulated signals. CONSTITUTION:The modulator is provided with two pulse width modulators 12, 13, the one pulse width modulator 12 applies leading edge modulation to a supplied digital signal, and the other pulse width modulator 13 applies trailing edge modulation to the supplied digital signal. In this case, A digital input signal from an input terminal 11 is fed to either of the pulse width modulators 12, 13, e.g. the leading edge modulation pulse width modulator 12 and fed to the other, e.g. the trailing edge modulation system pulse width modulator 13 via delay circuit 14 having a delay time by a period of a word clock period. Output signals from the pulse width modulators 12, 13 are added by an adder 15 and the result is extracted via an output terminal 16. Thus, the deterioration in the entire conversion characteristic is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation device, and particularly to a pulse width modulation device used, for example, when converting a digital input signal into an analog signal and outputting the analog signal.

[Summary of the invention]

The present invention provides a pulse width modulation device used to convert a digital input signal into an analog signal and output the digital input signal by using a leading edge modulation type pulse width modulator and a trailing edge modulation type pulse width modulator. is sent to one pulse width modulator, delayed by the word clock period and sent to the other pulse width modulator, and the output signals from these pulse width modulators are added together and output, thereby generating a modulated clock. This enables high-precision, high-resolution pulse width modulation without increasing the frequency.

[Conventional technology]

In recent years, an oversampling type 1-bit D/A conversion method has been attracting attention as a high-precision D/A conversion method used in audio equipment and the like. This method of D/A
The basic configuration of the conversion device is shown in FIG.

In FIG. 4, a digital signal supplied to an input terminal 21 is oversampled at an appropriate frequency by a digital filter 22 that performs oversampling processing, and then sent to a noise shaving circuit 23. This noise shaving circuit 23 feeds back the noise (quantization error) when requantizing the input digital signal into several bits (currently 1 to 5 bits), thereby reducing the noise in the high frequency range outside the audible band. A noise spectrum distribution is obtained in which the low frequency side is suppressed by shifting to the side. Several bits of data output from the noise shaving circuit 23 are converted into a 1-bit waveform by a 1-bit D/A converter 24 and taken out from an output terminal 25. The 1-bit waveform output signal from the output terminal 25 is sent to a low-pass filter (LPF) 26 to remove the sampling frequency component, and is output from the output terminal 27 as a continuous analog waveform signal.

1 pit D in such 1 bit D/A conversion method
As the /A converter 24, for example, a pulse width modulation device is used. An example of this pulse width modulation output waveform is shown in FIG. In this case, if the center position of the modulated waveform changes, it will result in a distorted analog signal, so a so-called symmetrical modulation method is used in which a symmetrical waveform whose center position does not change is output. If such pulse width modulation is used for 1-bit D/A conversion, there is an advantage that glitches and zero-cross distortions do not occur in principle. exceeds the maximum operating frequency of
There is a possibility that disadvantages such as an increase in unnecessary radiation may occur. For example, as shown in the pulse width modulation output waveform shown in FIG.
To obtain a resolution of 8 steps per sample (l word), the sample clock (word clock) period T
3 divided into 16, the period TM+(
That is, a master clock (modulation clock) of TMI=T8/I 6 is required. Generally speaking, when trying to obtain a resolution of n steps, 2n of the word clock frequency
A modulation clock with twice the frequency is required.

In order to solve this problem, a pulse width modulation device as shown in FIG. 6, for example, has been proposed.

In FIG. 6, the signal supplied to the input terminal 31 is, for example, a digital signal output from the noise shaving circuit 23 in FIG.
The signals are switched word by word by the changeover switch 32 and sent alternately to the respective pulse width modulators 33 and 34. These pulse width modulators 33 and 34 all operate with a master clock having a frequency half that of the master clock (modulation clock) shown in FIG.
The output waveform from the pulse width modulator 34 is as shown in FIG. 7A, and the output waveform from the pulse width modulator 34 is as shown in FIG. 7B. FIG. 7C shows a master clock serving as a modulation clock for these pulse width modulators 33 and 34, and has a period T.
1 is l of sample clock (word clock) period T8
/8 (T, 2"Ts/8). In this way, the pulse width modulators 33 and 34 alternately and symmetrically modulate and output each modulated signal, and the adder 35 adds the modulated outputs. By taking out from the output terminal 36, the master clock (
Modulation clock) can be reduced to 1/2 the frequency of the conventional one (FIG. 5B).

[Problem to be solved by the invention]

By the way, in the pulse width modulator as shown in FIG. 6, each pulse width modulator 33, 34 has one sample (
Since the input data is converted alternately every 1 word, that is, every 2 samples (2 words), there is a drawback that the conversion characteristics deteriorate if there are variations in the conversion gain. For example, even if the variation in resistance values formed inside an IC or the like is within 1%, the variation between the pulse width modulators 33 and 34 can reach up to 2%.

Specifically, it is assumed that seven-level digital data obtained by performing third-order noise shaving after 64 times oversampling is pulse width modulated using a pulse width modulation device as shown in Figure 6 above. The results of FFT (fast Fourier transform) analysis of this pulse width modulated output waveform are shown in FIGS. 8 and 9 depending on the presence or absence of the above-mentioned variations. That is, FIG. 8 shows the case where there is little or no variation between the pulse width modulators 33, 34, and FIG. 9 shows the case where the variation between the pulse width modulators 33, 34 is 2%. In the example in Figure 8, a dynamic range of approximately 120 dB or more is obtained in the audible frequency band (approximately 20 kHz or less), whereas in the example with 2% variation in Figure 9, the dynamic range deteriorates to approximately 70 dB. ing.

The present invention has been made in view of these points, and it is possible to achieve high resolution without increasing the modulation clock frequency of the pulse width modulator, and it is possible to achieve high resolution without increasing the modulation clock frequency of the pulse width modulator. An object of the present invention is to provide a pulse width modulation device that can prevent characteristic deterioration.

[Failure to solve the problem]

A pulse width modulation device according to the present invention is a pulse width modulation device that pulse width modulates a digital input signal and outputs the pulse width modulation device.
a first pulse width modulator for leading edge modulating the supplied digital signal; and a second pulse width modulator for trailing edge modulating the supplied digital signal.
a pulse width modulator; a delay circuit that delays the digital input signal by a word clock period and sends it to either the first or second pulse width modulator; and the first or second pulse width modulator. The above-mentioned problem is solved by comprising an adder that adds each output signal from the device.

[For production]

leading-edge modulating one of a digital input signal and a signal delayed by a word clock period of the digital input signal;
After performing trailing edge modulation on the other one, by adding them together, an l word digital input signal is converted into a modulation waveform for two word clock periods, and the first half of this modulation waveform is the leading edge modulation component. In addition, since the latter half of the modulation waveform is obtained as the trailing edge modulation component, the variations for each modulator are simultaneously included in one modulation waveform.
Deterioration of overall conversion characteristics can be prevented.

〔Example〕

FIG. 1 is a block circuit diagram showing an embodiment of a pulse width modulation device according to the present invention.

In the pulse width modulation device shown in FIG. 1, the signal supplied to the input terminal 11 is, for example, a digital signal output from the noise shaving circuit 23 shown in FIG. Period T8
It is updated every time. Here, this pulse width modulator has two pulse width modulators 12, 13, one pulse width modulator 12 leading-edge modulates the supplied digital signal, and the other pulse width modulator 12, 13 leading edge modulating the supplied digital signal. 13 performs trailing edge modulation on the supplied digital signal. Here, the above-mentioned leading edge modulation refers to modulation in which the leading edge of the modulated output pulse waveform changes depending on the input data value, as shown in FIG. 2A, for example, and the trailing edge of the modulated output pulse waveform. is fixed at the sample data boundary position, etc. On the other hand, the above-mentioned trailing edge modulation is, as shown in Figure 2B, in which the leading edge of the modulated output pulse waveform is fixed at the sample data boundary position, etc., and the trailing edge changes depending on the input data value. It refers to modulation.

The digital input signal from the input terminal 11 is supplied to one of the pulse width modulators 12 and 13, for example, the leading edge modulation type pulse width modulator 12, and is delayed by a word clock period Ts. The signal is supplied to the other pulse width modulator 13 using the trailing edge modulation method, for example, via a delay circuit 14 having a delay time τ (τ=T8). The output signals from these pulse width modulators 12.13 are sent to the adder 15.
and is taken out via the output terminal 16.

Each pulse width modulator 12, 13 is operated with a modulation clock having a frequency that is half the modulation clock (master clock) frequency required when using one pulse width modulator. That is, the master clock (
The same resolution can be obtained by setting the period TM2 of the modulation clock to twice the period TMI of the master clock shown in FIG. 5, and the modulation clock frequency can be reduced to 1/2. . Therefore, when digital data is sequentially input every word clock period T,
From the pulse width modulator 12, as shown in FIG.
4m, .
Ib, P 2b, P 2bs P 4b, . . . are output after being delayed by one period T8 with respect to the leading edge modulation pulse train.

By the way, the leading edge modulated pulse P1. corresponds to the first half of the pulse P1 of the modulated output waveform A in FIG. 7, and the trailing edge modulated pulse P1. corresponds to the latter half of the pulse P1, so by adding these pulses pla and Plb, the pulse P1 of the modulated output waveform A shown in FIG. 7 is obtained. Also, leading edge modulation output pulse P 2
m and the trailing edge modulated output pulse P2b, the pulse P2 of the modulated output waveform B in FIG. 7 is obtained, and in the same manner,
The leading edge modulated pulse trains P 3a, P 4m, . . . and the trailing edge modulated pulse trains P 2b, P 4b, .
The modulated output pulse trains P, , P, , . . . shown in the figure are obtained. Therefore, the circuit shown in Fig. 1 can obtain the same output as the circuit shown in Fig. 6, and can perform high-precision pulse width modulation at half the master clock (modulation clock) frequency of the conventional one (Fig. 5). can be carried out, and the effect of reducing unnecessary radiation can also be obtained.

Furthermore, since each pulse width modulator 12.13 converts all of the input digital data, even if the conversion gain varies among the pulse width modulators 12.13, the conversion of the entire device Almost no deterioration of characteristics occurs. Here, FIG. 3 is similar to the examples of FIG. 8 and FIG. 9 mentioned above,
For example, 7-value digital data obtained by applying 3rd order noise shaving after 64 times oversampling,
The results of FFT (Fast Fourier Transform) analysis of the output waveform obtained by pulse width modulation using the device shown in Figure 1, which has a 2% variation between each pulse width modulator 12 and 13, are shown. . According to this Figure 3, the above 2%
Despite this variation, the audible frequency band (approximately 20k
It is clear that a dynamic range of approximately 120 dB or more is obtained at frequencies (below Hz).

Note that the present invention is not limited to the above-mentioned embodiments; for example, the delay circuit 14 may be inserted and connected before the pulse width modulator 12 of the leading edge modulation method, and the delay circuit 14 may be connected to the pulse width modulator 13 of the trailing edge modulation method. may be directly supplied with a digital input signal from input terminal ll. Furthermore, the delay circuit 14 may be inserted and connected to the downstream side of the pulse width modulator 12 or 13.

〔Effect of the invention〕

As is clear from the above description, the D/A converter according to the present invention uses a leading edge modulation type pulse width modulator and a trailing edge modulation type pulse width modulator, and uses digital input. By sending the signal to one pulse width modulator, delaying it by a word clock period, and sending it to the other pulse width modulator, and adding the output signals from these pulse width modulators, the resolution can be increased. The modulation clock frequency is reduced by half without deteriorating the pulse width modulator, and even if there are variations in the conversion gain of each pulse width modulator, deterioration of the overall conversion characteristics is suppressed.

As a result, pulse width modulation with high resolution can be effectively realized within the limits of circuit operation speed or without reducing unnecessary radiation.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing an embodiment of the pulse width modulation device according to the present invention, Fig. 2 is a waveform diagram for explaining the operation of the embodiment, and Fig. 3 shows the conversion characteristics of the embodiment. A frequency characteristic diagram for explanation, FIG. 4 is a block circuit diagram showing a schematic configuration of an oversampling type 1-bit D/A converter, and FIG. 5 is a waveform diagram showing a modulated output waveform of a conventional pulse width modulation device. FIG. 6 is a block circuit diagram showing a conventional pulse width modulation device using two pulse width modulators;
The figure is a waveform diagram for explaining the operation of the device in Figure 6.
9 and 9 are frequency characteristic diagrams for explaining the conversion characteristics of the device shown in FIG. 6. 11...Input terminal 12...Leading edge modulation type pulse width modulator 13.
... Trailing edge modulation type pulse width modulator 14 ...
...Delay circuit 15...Adder 16...Output terminal

Claims (1)

[Claims] A pulse width modulator that pulse width modulates a digital input signal and outputs the pulse width modulator, comprising: a first pulse width modulator that modulates a leading edge of a supplied digital signal; and a first pulse width modulator that modulates a leading edge of a supplied digital signal; a second pulse width modulator that modulates the digital input signal; a delay circuit that delays the digital input signal by a word clock period and sends it to one of the first and second pulse width modulators; and an adder for adding each output signal from the pulse width modulator.