JP7501303B2 - Processed wafer, process for manufacturing processed wafer, and process for manufacturing silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a processed wafer having an epitaxial layer made of silicon carbide (hereinafter also simply referred to as SiC), a method for manufacturing the processed wafer, and a method for manufacturing a SiC carbide semiconductor device.

Conventionally, a trench-gate type SiC semiconductor device using a p-type epitaxial layer has been proposed (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, an ^n- type drift layer is formed on an n ⁺ type substrate made of SiC, and a p-type base layer is formed on the drift layer. Then, a plurality of trenches are formed so as to penetrate the base layer, and a gate insulating film and a gate electrode are formed in order in each trench. This forms a trench gate structure. Then, an n ⁺ type source region is formed in the surface layer portion of the base layer so as to contact the trench.

In the SiC semiconductor device, an upper electrode is formed so as to be electrically connected to the base layer and the source region, and a lower electrode is formed so as to be connected to the n ⁺ type substrate.

In such a SiC semiconductor device, a voltage equal to or greater than a predetermined threshold voltage is applied to the gate electrode, forming an n-type inversion layer (i.e., a channel region) in the portion of the base layer that contacts the trench. Then, electrons are supplied from the source region through the inversion layer to the drift layer, causing a current to flow between the upper electrode and the lower electrode.

The semiconductor device is manufactured as follows. First, a SiC wafer is prepared that has a plurality of device formation regions and is divided to form an n ⁺ type substrate in the SiC semiconductor device. Then, a drift layer constituting film that constitutes the drift layer and a base layer constituting the base layer are formed in order by epitaxial growth on the SiC wafer. After that, a source region, a trench gate structure, an upper electrode, a lower electrode, etc. are formed, and the SiC semiconductor device is manufactured by dividing the wafer into device formation regions.

JP 2018-037533 A

However, when forming a base layer constituting film by epitaxial growth as described above, there is a possibility that the film thickness and impurity concentration of the base layer constituting film in each device formation region may vary. In addition, in the above-described SiC semiconductor device, the threshold voltage varies depending on the film thickness and impurity concentration of the base layer that constitutes the channel region. For this reason, when manufacturing a SiC semiconductor device by forming a base layer constituting film by epitaxial growth and then dividing it into device formation regions, there is a possibility that the threshold voltage of each SiC semiconductor device may vary.

In view of the above, the present invention aims to provide a processed wafer that can suppress variations in threshold voltage, a method for manufacturing the processed wafer, and a method for manufacturing a SiC semiconductor device.

Claims 1 and 2 for achieving the above object provide a method for manufacturing a processed wafer for forming a SiC semiconductor device in which a base layer (3) is disposed on a drift layer (2) and a trench gate structure is formed through the base layer to reach the drift layer, the method comprising the steps of: preparing a SiC wafer (20) made of SiC, having a plurality of device formation regions (R), and being n-type or p-type; forming an n-type drift layer constituent film (2a) constituting the drift layer on the SiC wafer by epitaxial growth; and forming a p-type base layer constituent film (3a) constituting the base layer on the drift layer constituent film by epitaxial growth, and forming the base layer constituent film such that the in-plane distribution of the film thickness and the in-plane distribution of the impurity concentration are inversely correlated with each other by forming the base layer constituent film.
Furthermore, in claim 1, the base layer constituent film is formed by placing a silicon carbide wafer in a growth chamber (44) of an epitaxial film growth apparatus (30) and introducing a Si raw material containing gas, a C raw material containing gas, and a dopant gas containing a p-type impurity into the growth chamber to epitaxially grow the base layer constituent film, and the flow rates of the Si raw material containing gas and the C raw material containing gas are adjusted so that C/Si, which is the ratio of C contained in the C raw material containing gas to Si contained in the Si raw material containing gas, is 0.80 or less.
In claim 2, the base layer constituting film is formed by placing the silicon carbide wafer in a growth chamber (44) of the epitaxial film growth apparatus (30) and introducing a Si raw material containing gas, a C raw material containing gas, and a dopant gas containing a p-type impurity into the growth chamber to epitaxially grow the base layer constituting film, and the flow rates of the Si raw material containing gas and the C raw material containing gas are adjusted so that C/Si, which is the ratio of C contained in the C raw material containing gas to Si contained in the Si raw material containing gas, is 0.75 or less.

The threshold voltage of a SiC semiconductor device having a trench gate structure increases as the length of the portion of the base layer that contacts the trench gate structure (i.e., the channel length) increases, and increases as the impurity concentration increases. Therefore, by forming a base layer constituting film so that the in-plane distribution of film thickness and the in-plane distribution of impurity concentration are inversely correlated, it is possible to suppress variations in threshold voltage Vth in each SiC semiconductor device when the SiC semiconductor device is manufactured by dividing each device formation region.

Claims 4 and 5 provide a method for manufacturing a SiC semiconductor device having a trench gate structure, comprising the steps of: preparing a silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type; forming an n-type drift layer constituent film (2a) constituting a drift layer on the silicon carbide wafer by epitaxial growth; and forming a p-type base layer constituent film (3a) constituting a base layer on the drift layer constituent film by epitaxial growth; preparing a processed wafer (21) on which a base layer constituent film is formed such that the in-plane distribution of film thickness and the in-plane distribution of impurity concentration are inversely correlated by forming the base layer constituent film ; forming an n-type impurity region constituent film (4a) on a surface layer portion of the base layer constituent film; forming a trench (5) that penetrates the impurity region and the base layer constituent film to reach the drift layer constituent film; forming a gate insulating film (6) on a wall surface of the trench; and forming a gate electrode (7) on the gate insulating film to form a trench gate structure.
Furthermore, claim 4 provides a method for forming a base layer constituting film by preparing a processed wafer, the base layer constituting film being formed so that the portion located on the central side of the silicon carbide wafer is thinner in thickness than the portion located on the outer edge side and the portion located on the central side has a higher impurity concentration than the portion located on the outer edge side, and by forming an impurity region constituting film, the impurity region constituting film is formed by implanting ions into the base layer constituting film in which the portion located on the central side of the silicon carbide wafer is thinner in thickness than the portion located on the outer edge side.
In addition, claim 5 provides a method for forming a base layer constituting film by preparing a processed wafer, the base layer constituting film being formed so that the portion located on the central side of the silicon carbide wafer has a thinner film thickness than the portion located on the outer edge side and the portion located on the central side has a higher impurity concentration than the portion located on the outer edge side; and in forming an impurity region constituting film, an impurity region constituting film is formed on the base layer constituting film by epitaxial growth, and the base layer constituting film and the impurity region constituting film are formed so that the portion located on the central side of the silicon carbide wafer has a thinner film thickness than the portion located on the outer edge side.

This makes it possible to suppress variations in threshold voltages in each SiC semiconductor device when manufacturing the SiC semiconductor device by dividing each device formation region.

Claim 6 relates to a processed wafer for forming a SiC semiconductor device in which a base layer (3) is disposed on a drift layer (2) and a trench gate structure is formed through the base layer to reach the drift layer, the processed wafer comprising: a SiC wafer (20) made of SiC, having a plurality of device formation regions (R), and being made to be n-type or p-type; an n-type drift layer constituent film (2a) formed on the SiC wafer, made of an epitaxial film and constituting the drift layer; and a p-type base layer constituent film (3a) formed on the drift layer constituent film, made of an epitaxial film and constituting the base layer, The base layer constituent film has an in-plane distribution of film thickness and an in-plane distribution of impurity concentration that are inversely correlated, and further, the portion located on the central side of the silicon carbide wafer is made thinner than the portion located on the outer edge side, and the portion located on the central side has a higher impurity concentration than the portion located on the outer edge side. In each of the multiple device formation regions, a trench (5) is formed that penetrates the base layer and reaches the drift layer, and each of the trenches formed in the multiple device formation regions has a different length of contact with the base layer constituent film between the portion on the central side and the portion on the outer edge side of the base layer constituent film .

As a result, the in-plane distribution of film thickness in the base layer constituent film and the in-plane distribution of impurity concentration are inversely correlated, so that when each device formation region is divided to manufacture SiC semiconductor devices, it is possible to suppress variations in threshold voltage Vth in each SiC semiconductor device.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment. 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. 2B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2A. 2C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2B. FIG. 2 is a plan view of a SiC wafer. FIG. 2 is a schematic cross-sectional view of an epitaxial film growth apparatus. FIG. 2 is a plan view showing a SiC wafer placed on a mounting portion of a susceptor. 11 is a diagram showing the relationship between the distance from the center of the installation portion and the film thickness of the base layer constituting film. FIG. 13 is a diagram showing the relationship between the distance from the center of the installation portion and the impurity concentration of the base layer forming film. FIG. FIG. 13 is a diagram showing the relationship between the channel length and the impurity concentration of the base layer. 6A to 6C are cross-sectional views showing a manufacturing process of a SiC semiconductor device in the second embodiment. 9B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 9A.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
A first embodiment will be described with reference to the drawings. As shown in Fig. 1, the SiC semiconductor device of this embodiment is configured by forming a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor). Although not shown, the SiC semiconductor device has a cell region and an outer peripheral region formed to surround the cell region. The MOSFET is formed in the cell region of the SiC semiconductor device.

The SiC semiconductor device is configured using an n ⁺ type substrate 1 made of SiC. An n ^- type drift layer 2 and a p type base layer 3, both made of SiC, are epitaxially grown in this order on the surface of the substrate 1. An n ⁺ type source region 4 is formed in the surface layer portion of the base layer 3. In this embodiment, the source region 4 is formed by ion implantation. In this embodiment, the source region 4 corresponds to an impurity region.

The substrate 1 has, for example, an n-type impurity concentration of 1.0×10 ¹⁹ /cm ³ and a (0001) Si surface. The drift layer 2 has, for example, an n-type impurity concentration of 0.5 to 2.0×10 ¹⁶ /cm ³ and a thickness of 5 to 14 μm. In this embodiment, the substrate 1 constitutes a drain layer in a MOSFET.

The base layer 3 is a portion where the channel region is formed, and has, for example, a p-type impurity concentration of about 3.0×10 ¹⁷ /cm ³ and a thickness of 0.5 to 2 μm. The source region 4 has a higher impurity concentration than the drift layer 2, and has, for example, an n-type impurity concentration in the surface layer of 2.5×10 ¹⁸ to 1.0×10 ¹⁹ /cm ³ and a thickness of 0.5 to 2 μm. The film thicknesses of the drift layer 2, base layer 3 and source region 4 are arbitrary and are not limited to those described above.

A trench 5 is formed so as to penetrate the base layer 3 and the source region 4 and reach the drift layer 2. The base layer 3 and the source region 4 are arranged so as to contact the side of the trench 5. The base layer 3 in this embodiment is formed so that the length of the part contacting the trench 5 is equal to the film thickness. In other words, the film thickness of the base layer 3 in this embodiment is the channel length. Also, although FIG. 1 shows only one trench 5, the actual trench 5 is formed in a stripe shape with multiple trenches arranged at equal intervals in the left-right direction of the page.

A gate insulating film 6 is formed on the inner wall surface of the trench 5. A gate electrode 7 made of doped poly-Si is formed on the surface of the gate insulating film 6. The trench 5 is then completely filled with the gate insulating film 6 and the gate electrode 7. In this embodiment, the trench gate structure is configured in this manner.

Furthermore, between adjacent trenches 5, ap ⁺ type contact region 8 is formed on the opposite side of the trench 5 with the source region 4 in between. And, below the contact region 8, ap ⁺ type deep layer 9 is formed which is deeper than the base layer 3. In this embodiment, the contact region 8 and the deep layer 9 are integrally formed and have a higher impurity concentration than the base layer 3, and both have a p-type impurity concentration of 1.0×10 ¹⁸ /cm ³ to 1.0×10 ²⁰ /cm ³ .

An interlayer insulating film 10 is formed on the surface of the source region 4 and the surface of the gate electrode 7. A contact hole 10a is formed in the interlayer insulating film 10 to expose a part of the source region 4 and the contact region 8. An upper electrode 11 is formed on the interlayer insulating film 10 and is electrically connected to the source region 4 and the contact region 8.

In this embodiment, the upper electrode 11 is made of multiple metals, such as Ni/Al. The portion of the multiple metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 4) is made of a metal that can make ohmic contact with the n-type SiC. At least the portion of the multiple metals that contacts the p-type SiC (i.e., the contact region 8) is made of a metal that can make ohmic contact with the p-type SiC.

A lower electrode 12, which corresponds to a second electrode electrically connected to the substrate 1, is formed on the back side of the substrate 1. In this embodiment, this structure constitutes an n-channel type inversion type trench gate MOSFET. A cell region is formed by arranging multiple such MOSFETs.

The above is the configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, a voltage equal to or greater than a predetermined threshold voltage Vth is applied to the gate electrode 7, forming an n-type inversion layer (i.e., a channel region) in the portion of the base layer 3 that contacts the trench 5. Then, electrons are supplied from the source region 4 through the inversion layer to the drift layer 2, causing a current to flow between the upper electrode 11 and the lower electrode 12.

In addition, in this embodiment, a deep layer 9 is formed. As a result, the depletion layer at the pn junction between the deep layer 9 and the drift layer 2 extends significantly toward the drift layer 2, making it difficult for high voltage caused by the drain voltage to penetrate into the gate insulating film 6. This makes it possible to prevent the gate insulating film 6 from being destroyed, and to achieve high voltage resistance.

In such a SiC semiconductor device, the threshold voltage Vth increases as the length of the portion of the base layer 3 that contacts the trench 5 (i.e., the channel length) increases. That is, in this embodiment, the threshold voltage Vth increases as the thickness of the base layer 3 increases. Also, the threshold voltage Vth increases as the impurity concentration of the base layer 3 increases, because it becomes more difficult to form an inversion layer.

Next, the manufacturing method of the above-mentioned SiC semiconductor device will be described with reference to Figures 2A to 2C and Figures 3 to 8.

First, as shown in FIG. 2A and FIG. 3, a SiC wafer 20 is prepared in which a plurality of device formation regions R are partitioned by dicing lines DL, and the substrate 1 is formed by dividing the SiC wafer 20 along the dicing lines DL.

Then, as shown in FIG. 2B, a drift layer constituent film 2a and a base layer constituent film 3a made of SiC are epitaxially grown in this order on the main surface of the SiC wafer 20. In this embodiment, the base layer constituent film 3a is epitaxially grown to a thickness equivalent to the sum of the thicknesses of the base layer 3 and the source region 4 shown in FIG. 1. The drift layer constituent film 2a is a film that constitutes the drift layer 2 when divided into device units, and the base layer constituent film 3a is a film that constitutes the base layer 3 when divided into device units.

Here, the epitaxial film growth apparatus 30 for epitaxially growing the drift layer constituent film 2a and the base layer constituent film 3a of this embodiment will be described with reference to FIG. 4. In this embodiment, the epitaxial film growth apparatus 30 is a so-called horizontal hot wall apparatus in which the growth chamber 44 is heated as a whole and gas flows in the surface direction of the SiC wafer 20.

As shown in FIG. 4, the epitaxial film growth apparatus 30 of this embodiment is configured to include a furnace body 40, a gas inlet 50, a gas outlet 60, a susceptor section 70, and a heating section 80.

The furnace body 40 is configured such that the insulating material 42 and the heated portion 43 are arranged in this order inside the cover 41 made of quartz or the like, and is cylindrical with a hollow portion inside that forms the growth chamber 44. The insulating material 42 and the heated portion 43 are arranged inside the cover 41 so as to substantially surround the growth chamber 44. The heated portion 43 is the portion that is inductively heated by the heating portion 80 described later, and is made of, for example, carbon or the like.

The gas inlet 50 is an inlet for introducing gases for forming an epitaxial film into the growth chamber 44 of the furnace body 40, and is provided on one end side of the cylindrical furnace body 40. In this embodiment, a Si raw material-containing gas containing a Si raw material, a C raw material-containing gas containing a C raw material, a dopant gas, a carrier gas, and the like are introduced into the growth chamber 44 from the gas inlet 50.

As the Si raw material containing gas, for example, _SiH4 (silane) is used as a silane gas, and chlorine-based Si raw material containing gas ( _chloride -based raw material) containing Cl having an etching effect such as _SiH2Cl2 , _{SiHCl3 , SiCl4} , etc. is used. Also, as the Si raw material containing gas, for example, a gas in which HCl is added to silane is used. As the C raw material gas, for example, _C3H8 (propane) is used.

The dopant gas is a gas for controlling the conductivity type of the epitaxial film. When epitaxially growing the n-type drift layer-constituting film 2a, for example, a dopant gas containing _N2 (nitrogen) is used. When epitaxially growing the p-type base layer-constituting film 3a, for example, a dopant gas containing TMA (trimethylaluminum) is used.

A gas that does not contain Si or C is used as the carrier gas, and for example, an etching gas containing H ₂ (hydrogen) or an inert gas (rare gas) such as Ar (argon) or He (helium) is used. By using such a gas that does not contain Si or C, the diffusion of the source gas can be suppressed. Furthermore, by suppressing the diffusion of the source gas, the formation of unnecessary Si, C, or SiC products can be suppressed, and the generation of particle sources can be suppressed.

The gas exhaust port 60 is located on the opposite side of the furnace body 40 from the gas inlet port 50, and exhausts unreacted gases and the like that have passed through the SiC wafer 20. The gas exhaust port 60 is also connected to a suction section (not shown) or the like so that the atmospheric pressure in the growth chamber 44 can be appropriately adjusted, and the growth chamber 44 can be evacuated.

The susceptor section 70 is disk-shaped and has a mounting section 71 that constitutes a mounting surface on which the SiC wafer 20 is placed, and a shaft section 72 that extends downward from the center of the mounting section 71, and is disposed so that the mounting section 71 is located between the gas inlet 50 and the gas outlet 60. The susceptor section 70 is made rotatable by connecting the shaft section 72 to a rotation mechanism (not shown).

The heating section 80 is composed of a coil arranged to surround the furnace body 40. The heating section 80 inductively heats the heated section 43 by applying an alternating current. This maintains the inside of the growth chamber 44 at a predetermined temperature.

The above is the configuration of the epitaxial film growth apparatus 30 in this embodiment. When epitaxially growing the drift layer constituent film 2a and the base layer constituent film 3a, the SiC wafer 20 is placed on the mounting portion 71 of the epitaxial film growth apparatus 30 and epitaxially grown. In this embodiment, as shown in FIG. 5, three SiC wafers 20 are evenly arranged in the circumferential direction with the center C of the mounting portion 71 as a reference, and epitaxial growth is performed on the three SiC wafers 20 simultaneously.

Specifically, first, the pressure inside the growth chamber 44 is set to about 5 to 10 kPa by vacuum suction through the gas exhaust port 60, and the temperature of the growth chamber 44 is set to about 1600 to 1650°C by the heating unit 80. In addition, the susceptor rotation speed is set to 30 to 60 rpm.

When epitaxially growing, SiH ₄ as a Si source-containing gas is introduced into the growth chamber 44 from the gas inlet 50 at a flow rate of 25 to 30 sccm, and C ₃ H ₈ as a C source-containing gas is introduced into the growth chamber 44 at a flow rate of 5.5 to 7.5 sccm. Also, H ₂ as a carrier gas is introduced into the growth chamber 44 from the gas inlet 50 at a flow rate of 110 to 140 Slm. When epitaxially growing the n-type drift layer-constituting film 2a, N ₂ as a dopant gas is introduced into the growth chamber 44 from the gas inlet 50 at a flow rate of 1.0 to 1.5 sccm. When epitaxially growing the p-type base layer-constituting film 3a, 200 pm TMA as a dopant gas is introduced into the growth chamber 44 from the gas inlet 50 at a flow rate of 50 to 2000 sccm. As a result, various gases are introduced into the growth chamber 44, and a processed wafer 21 is formed in which the drift layer constituting film 2a and the base layer constituting film 3a are epitaxially grown in this order on the surface of the SiC wafer 20.

When forming a trench-gate MOSFET as described above, if the thickness and impurity concentration of the base layer constituting film 3a vary in each device forming region R, the threshold voltage Vth of the SiC semiconductor device may vary when the device forming regions R are divided to form the SiC semiconductor device. For this reason, in this embodiment, the base layer constituting film 3a is formed as follows.

First, when epitaxial growth is performed using the epitaxial film growth apparatus 30, the temperature of the installation portion 71 of the susceptor portion 70 is not constant due to heat radiation from the shaft portion 72 and outer edge of the susceptor portion 70, and the portion between the shaft portion 72 and the outer edge is likely to be hotter than the shaft portion 72 side and the outer edge side. The SiC wafer 20 installed on the installation portion 71 has a temperature distribution that depends on the temperature distribution of the installation portion 71, and the center side of the SiC wafer 20 has a higher temperature than the outer edge. For this reason, as shown in FIG. 6, the base layer constituting film 3a has a distribution in which the portion located on the center side of the SiC wafer 20 is thinner than the portion located on the outer edge side in the in-plane distribution of the film thickness. In other words, the base layer constituting film 3a has a downward convex distribution. That is, the base layer constituting film 3a has a thinner film thickness in the portion formed in the device formation region R on the center side of the SiC wafer 20 than in the portion formed in the device formation region R on the outer edge side of the SiC wafer 20.

6 shows the results when C/Si (hereinafter, simply referred to as C/Si), which is the ratio of C contained in the C raw material containing gas to Si contained in the Si raw material containing gas, is changed. FIG. 6 shows the results when C/Si is changed by changing the flow rate of C ₃ H ₈ , which is the C raw material containing gas, while keeping the Si raw material containing gas constant. In this case, it is confirmed that even if C/Si is changed, the in-plane distribution of the film thickness hardly changes. In addition, the distance from the center of the installation part in FIG. 6 corresponds to the distance r from the center C shown in FIG. 5. Similarly, the distance from the center of the installation part in FIG. 7, which will be described later, corresponds to the distance r from the center C shown in FIG. 5.

On the other hand, it has been confirmed that the in-plane distribution of the impurity concentration of the base layer constituting film 3a varies greatly by changing the C/Si, as shown in FIG. 7. In the inventors' experiments, it has been confirmed that the temperature coefficient of the amount of uptake of aluminum (i.e., TMA), which is a dopant constituting the p-type, depends on the C/Si. Specifically, it has been confirmed that the temperature coefficient of the amount of uptake is negative when the C/Si is high, and positive when the C/Si is low. Therefore, it is considered that the temperature distribution of the SiC wafer 20 and the C/Si dependence of the coefficient of the temperature dependence of the amount of uptake cause an in-plane distribution of the impurity concentration in the base layer constituting film 3a, as shown in FIG. 7.

The threshold voltage Vth of the SiC semiconductor device increases as the thickness of the base layer 3 increases and as the impurity concentration of the base layer 3 increases, as described above. Therefore, in order to reduce the variation in the threshold voltage Vth of the SiC semiconductor device obtained by dividing each device formation region R, the impurity concentration of the thin part of the base layer constituent film 3a should be high and the impurity concentration of the thick part should be low. In other words, the base layer constituent film 3a should have an in-plane distribution of impurity concentration that is convex upward, with the impurity concentration at the center side being higher than the impurity concentration at the outer edge side. In other words, the base layer constituent film 3a should have an inverse correlation between the in-plane distribution of film thickness and the in-plane distribution of impurity concentration.

As shown in FIG. 7, when C/Si is 0.85, the in-plane distribution of the impurity concentration of the base layer constituent film 3a is confirmed to be a distribution in which the impurity concentration is higher at the outer edge than at the center. In other words, when C/Si is 0.85, the in-plane distribution of the impurity concentration of the base layer constituent film 3a is confirmed to be the same as the in-plane distribution of the film thickness. On the other hand, when C/Si is 0.80, the in-plane distribution of the impurity concentration of the base layer constituent film 3a is confirmed to be a distribution in which the impurity concentration is lower at the outer edge than at the center. And when C/Si is 0.75, the in-plane distribution of the impurity concentration of the base layer constituent film 3a is confirmed to be a distribution in which the impurity concentration is further lower at the outer edge than at the center.

Therefore, in this embodiment, when the base layer constituting film 3a is epitaxially grown, the flow rates of the Si-containing raw material gas and the C raw material gas are adjusted so that C/Si is 0.80 or less. In this case, the flow rates of the Si-containing raw material gas and the C raw material gas are adjusted so that C/Si is 0.75 or less, so that the impurity concentration can be further lower on the outer edge side than on the center side. When C/Si is 0.80, for example, the flow rate of _SiH4 is 26.5 sccm and _the flow rate of _C3H8 is 7.1 sccm. When C/Si is 0.75, the flow rate of _SiH4 is 26.5 sccm and _the flow rate of _C3H8 is 6.6 sccm.

In addition, in the above-described SiC semiconductor device, as shown in FIG. 8, the ideal line I of the threshold voltage Vth depends on the channel length and the impurity concentration of the base layer 3, and the slope of the ideal line I (hereinafter, also simply referred to as the slope) is −3.1×10 ^21. For this reason, when the base layer constituting film 3a is formed as described above, the closer the slope of the approximation line (hereinafter, also simply referred to as the approximation line) obtained by plotting the relationship between the channel length and the impurity concentration in each device formation region R is to −3.1×10 ²¹ , the more the variation in the threshold voltage Vth can be reduced when the SiC semiconductor device is manufactured by performing each process described later. The slope of the ideal line I is a value defined by the amount of change in the impurity concentration relative to the amount of change in the channel length on the ideal line I. The slope of the approximation line is a value defined by the amount of change in the impurity concentration relative to the amount of change in the channel length on the approximation line.

8, when C/Si is 0.75, the plot showing the relationship between channel length and impurity concentration in each device formation region R is distributed along the ideal line I, compared to when C/Si is 0.80, so that a SiC semiconductor device with smaller variations in threshold voltage Vth can be manufactured. Therefore, it is preferable that the base layer constituting film 3a is formed so that the in-plane distribution of the film thickness and the in-plane distribution of the impurity concentration are inversely correlated with each other, and the slope of the approximation line approaches −3.1×10 ²¹ .

Specifically, by forming the base layer constituting film 3a so that the gradient of the approximation line is −4.6×10 ²¹ to −1.6×10 ²¹ [cm ⁻³ /cm], the variation in threshold voltage Vth caused by the base layer constituting film 3a in each SiC semiconductor device when the SiC semiconductor device is manufactured can be reduced to about 1.0 V. Also, by forming the base layer constituting film 3a so that the gradient of the approximation line is −3.9×10 ²¹ to −2.3×10 ²¹ [cm ⁻³ /cm], the variation in threshold voltage Vth caused by the base layer constituting film 3a in each SiC semiconductor device when the SiC semiconductor device is manufactured can be reduced to about 0.5 V. And, by forming the base layer constituting film 3a so that the gradient of the approximation line is −3.1×10 ²¹ [cm ⁻³ /cm], the variation in threshold voltage Vth caused by the base layer constituting film 3a in each SiC semiconductor device when the SiC semiconductor device is manufactured can be almost eliminated.

Therefore, in this process, it is preferable that the base layer constituting film 3a is formed according to the variation in threshold voltage Vth that is acceptable depending on the application. Currently, it is desired that the variation in threshold voltage Vth be about 1.0 V, and it is recommended that the variation in threshold voltage Vth be about 0.5 V. The film thickness and impurity concentration of the base layer constituting film 3a can be adjusted by changing the flow rates of the Si raw material containing gas and the C raw material containing gas during epitaxial growth.

Next, as shown in FIG. 2C, in this embodiment, ion implantation or the like is performed on the surface layer of the base layer forming film 3a to form a source region forming film 4a. The source region forming film 4a is a film that forms the source region 4 when divided into device units. In this embodiment, the source region forming film 4a corresponds to the impurity region forming film. After that, although not shown in the figure, a general semiconductor manufacturing process is performed to form the contact region 8, deep layer 9, trench gate structure, upper electrode 11, lower electrode 12, etc. Then, the device forming region R is divided along the dicing line DL to manufacture the above-mentioned SiC semiconductor device.

According to the present embodiment described above, when manufacturing a SiC semiconductor device, the base layer constituting film 3a is made thinner at the center than at the outer edge, and the impurity concentration at the center is made higher than at the outer edge. In other words, the base layer constituting film 3a is made to have an inverse correlation between the film thickness and the impurity concentration. In other words, the base layer constituting film 3a is made to have an impurity concentration at which the threshold voltage Vth is low in the film thickness where the threshold voltage Vth is high, and an impurity concentration at which the threshold voltage Vth is high in the film thickness where the threshold voltage Vth is low. Therefore, in this embodiment, when manufacturing SiC semiconductor devices, it is possible to suppress the variation in the threshold voltage Vth among the SiC semiconductor devices, and thus the variation in the on-resistance can be suppressed.

By forming the base layer constituent film by ion implantation, it is possible to suppress variations in the film thickness and impurity concentration of the base layer constituent film. However, when ion implantation is performed on SiC, since SiC is hard, large-scale equipment and detailed control are required to form a base layer with the desired depth, making the manufacturing process complicated.

On the other hand, in this embodiment, the threshold voltage Vth is prevented from varying depending on the relationship between the thickness and impurity concentration of the base layer constituting film 3a. The relationship between the thickness and impurity concentration of the base layer constituting film 3a can be adjusted by changing the flow rates of the Si raw material containing gas and the C raw material containing gas when epitaxially growing the base layer constituting film 3a. Therefore, according to this embodiment, it is possible to prevent the manufacturing process from becoming complicated while also preventing the threshold voltage Vth from varying.

(1) In this embodiment, C/Si is set to 0.80 or less. This makes it possible to suppress variations in threshold voltage Vth in each SiC semiconductor device. In this case, by setting C/Si to 0.75 or less, it is possible to further suppress variations in threshold voltage Vth.

(2) In this embodiment, the base layer constituting film 3a is formed so that the gradient of the approximation line is −4.6×10 ²¹ to −1.6×10 ²¹ [cm ⁻³ /cm]. Therefore, when a SiC semiconductor device is constructed, the variation in threshold voltage Vth can be reduced to approximately 1.0 V. In this case, by forming the base layer constituting film 3a so that the gradient of the approximation line is −3.9×10 ²¹ to −2.3×10 ²¹ [cm ⁻³ /cm], the variation in threshold voltage Vth can be further reduced.

Second Embodiment
A second embodiment will be described. In this embodiment, the source region 4 is formed by epitaxial growth in comparison with the first embodiment. As the rest is the same as the first embodiment, the description will be omitted here.

In this embodiment, after preparing the SiC wafer 20 shown in FIG. 2A, as shown in FIG. 9A, a drift layer constituent film 2a and a base layer constituent film 3a are formed to form a processed wafer 21. Note that the base layer constituent film 3a in FIG. 9A has a thinner film thickness than the base layer constituent film 3a in FIG. 2B described in the first embodiment. Next, as shown in FIG. 9B, a source region constituent film 4a is formed on the base layer constituent film 3a by epitaxial growth.

After that, similar to the first embodiment described above, a general semiconductor manufacturing process is performed, and then the device formation region R is divided along the dicing line DL to manufacture the SiC semiconductor device shown in FIG. 1.

As described above, according to this embodiment, the base layer constituting film 3a is formed so that the film thickness and the impurity concentration are inversely correlated, so that the same effect as in the first embodiment can be obtained.

(1) In this embodiment, the source region forming film 4a is formed by epitaxial growth, so the thickness of the base layer forming film 3a when epitaxially growing can be thinner than in the first embodiment. This makes it possible to reduce the variation in thickness of the base layer forming film 3a after epitaxial growth.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

In the above-mentioned embodiments, an example in which a MOSFET having a trench gate structure of an n-channel type is formed has been described. However, the SiC semiconductor device may be configured to have an IGBT having a similar structure formed therein in addition to the MOSFET. In the case of the IGBT, it is the same as the vertical MOSFET described in the first embodiment, except that the n ⁺ type substrate 1 in the above-mentioned embodiments is changed to a substrate 1 as a p ⁺ type collector layer.

In each of the above embodiments, when epitaxially growing the base layer constituent film 3a, the number of SiC wafers 20 placed on the mounting portion 71 of the susceptor portion 70 can be changed as appropriate, and may be two or less, or may be four or more. When placing one SiC wafer 20 on the mounting portion 71 of the susceptor portion 70, the SiC wafer 20 can be placed on the mounting portion 71 so that the center C of the mounting portion 71 and the center of the SiC wafer 20 coincide with each other.

Furthermore, in each of the above embodiments, the epitaxial film growth apparatus 30 may be a cold wall type that heats only the periphery of the SiC wafer 20, rather than a hot wall type that heats the entire growth chamber 44. Also, the epitaxial film growth apparatus 30 may be a vertical type in which the gas flows along the normal direction of the SiC wafer 20, rather than a horizontal type in which the gas flows along the planar direction of the SiC wafer 20. Note that when the base layer constituting film 3a is epitaxially grown using such an epitaxial film growth apparatus 30, the detailed values of the film thickness and impurity concentration change, but the in-plane distribution (i.e., the shape) does not change. Therefore, when epitaxially growing the base layer constituting film 3a, the same effect as in each of the above embodiments can be obtained by setting C/Si to 0.80 or less as described above.

2 drift layer 2a drift layer constituent film 3 base layer 3a base layer constituent film 20 SiC wafer R device formation region

Claims (9)

A method for manufacturing a processed wafer for forming a silicon carbide semiconductor device in which a base layer (3) is disposed on a drift layer (2) and a trench gate structure is formed through the base layer to reach the drift layer, comprising:
Preparing a silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type;
forming an n-type drift layer forming film (2 a) constituting the drift layer on the silicon carbide wafer by epitaxial growth;
forming a p-type base layer constituting film (3 a) constituting the base layer on the drift layer constituting film by epitaxial growth;
forming the base layer constituting film so that the in-plane distribution of the film thickness and the in-plane distribution of the impurity concentration are inversely correlated;
Furthermore, in forming the base layer constituting film, the silicon carbide wafer is placed in a growth chamber (44) of an epitaxial film growth apparatus (30), and a Si source containing gas, a C source containing gas, and a dopant gas containing a p-type impurity are introduced into the growth chamber to epitaxially grow the base layer constituting film;
A method for manufacturing a processed wafer, in which the flow rates of the Si raw material containing gas and the C raw material containing gas are adjusted so that C/Si, which is the ratio of C contained in the C raw material containing gas to Si contained in the Si raw material containing gas, is 0.80 or less. A method for manufacturing a processed wafer for forming a silicon carbide semiconductor device in which a base layer (3) is disposed on a drift layer (2) and a trench gate structure is formed through the base layer to reach the drift layer, comprising:
Preparing a silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type;
forming an n-type drift layer forming film (2 a) constituting the drift layer on the silicon carbide wafer by epitaxial growth;
forming a p-type base layer constituting film (3 a) constituting the base layer on the drift layer constituting film by epitaxial growth;
forming the base layer constituting film so that the in-plane distribution of the film thickness and the in-plane distribution of the impurity concentration are inversely correlated;
Furthermore, in forming the base layer constituting film, the silicon carbide wafer is placed in a growth chamber (44) of an epitaxial film growth apparatus (30), and a Si source containing gas, a C source containing gas, and a dopant gas containing a p-type impurity are introduced into the growth chamber to epitaxially grow the base layer constituting film;
A method for manufacturing a processed wafer, in which the flow rates of the Si raw material containing gas and the C raw material containing gas are adjusted so that C/Si, which is the ratio of C contained in the C raw material containing gas to Si contained in the Si raw material containing gas, is 0.75 or less. 3. The method for manufacturing a processed wafer as described in claim 1 or 2, wherein the base layer constituting film is formed so that a portion located on the central side of the silicon carbide wafer has a thinner film thickness than a portion located on the outer edge side, and the base layer constituting film is formed so that the portion located on the central side has a higher impurity concentration than the portion located on the outer edge side. A method for manufacturing a silicon carbide semiconductor device having a trench gate structure, comprising:
A silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type is prepared; an n-type drift layer constituent film (2a) constituting a drift layer (2) is formed on the silicon carbide wafer by epitaxial growth; and a p-type base layer constituent film (3a) constituting a base layer (3) is formed on the drift layer constituent film by epitaxial growth, and a processed wafer (21) on which the base layer constituent film is formed is prepared such that an in-plane distribution of film thickness and an in-plane distribution of impurity concentration are inversely correlated by forming the base layer constituent film ;
forming an n-type impurity region forming film (4a) on a surface layer portion of the base layer forming film;
forming a trench (5) penetrating the impurity region forming film and the base layer forming film to reach the drift layer forming film, forming a gate insulating film (6) on a wall surface of the trench, and forming a gate electrode (7) on the gate insulating film to form the trench gate structure ;
By preparing the processed wafer, when forming the base layer constituting film, the base layer constituting film is formed so that the portion located on the central portion side of the silicon carbide wafer has a thinner film thickness than the portion located on the outer edge side, and the portion located on the central portion side has a higher impurity concentration than the portion located on the outer edge side;
A method for manufacturing a silicon carbide semiconductor device, in which the impurity region forming film is formed by implanting ions into the base layer forming film, the portion located on the central side of the silicon carbide wafer being thinner than the portion located on the outer edge side . A method for manufacturing a silicon carbide semiconductor device having a trench gate structure, comprising:
A silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type is prepared; an n-type drift layer constituent film (2a) constituting a drift layer (2) is formed on the silicon carbide wafer by epitaxial growth; and a p-type base layer constituent film (3a) constituting a base layer (3) is formed on the drift layer constituent film by epitaxial growth, and a processed wafer (21) on which the base layer constituent film is formed is prepared such that an in-plane distribution of film thickness and an in-plane distribution of impurity concentration are inversely correlated by forming the base layer constituent film ;
forming an n-type impurity region forming film (4a) on a surface layer portion of the base layer forming film;
forming a trench (5) penetrating the impurity region forming film and the base layer forming film to reach the drift layer forming film, forming a gate insulating film (6) on a wall surface of the trench, and forming a gate electrode (7) on the gate insulating film to form the trench gate structure ;
By preparing the processed wafer, when forming the base layer constituting film, the base layer constituting film is formed so that the portion located on the central portion side of the silicon carbide wafer has a thinner film thickness than the portion located on the outer edge side, and the portion located on the central portion side has a higher impurity concentration than the portion located on the outer edge side;
A method for manufacturing a silicon carbide semiconductor device, wherein the impurity region forming film is formed on the base layer forming film by epitaxial growth, and the base layer forming film and the impurity region forming film have thinner thicknesses at portions located toward the center of the silicon carbide wafer than at portions located toward the outer edge of the silicon carbide wafer . A processed wafer for forming a silicon carbide semiconductor device in which a base layer (3) is disposed on a drift layer (2) and a trench gate structure is formed through the base layer to reach the drift layer,
A silicon carbide wafer (20) made of silicon carbide, having a plurality of device formation regions (R), and being n-type or p-type;
An n-type drift layer-constituting film (2a) formed on the silicon carbide wafer and composed of an epitaxial film to constitute the drift layer;
a p-type base layer constituting film (3 a) formed on the drift layer constituting film and composed of an epitaxial film to constitute the base layer,
The base layer constituting film has an inverse correlation between an in-plane distribution of film thickness and an in-plane distribution of impurity concentration, and further, a portion located on the central side of the silicon carbide wafer has a thinner film thickness than a portion located on the outer edge side, and the portion located on the central side has a higher impurity concentration than a portion located on the outer edge side,
In each of the device formation regions, a trench (5) is formed penetrating the base layer and reaching the drift layer,
A processed wafer in which each of the trenches formed in the plurality of device formation regions has a length of contact with the base layer constituting film that differs between a portion on the central side of the base layer constituting film and a portion on the outer edge side of the base layer constituting film . The processed wafer according to claim 6, wherein the base layer constituting film has a slope of an approximation line obtained from the relationship between the film thickness [μm] of the portion of the base layer constituting film in contact with the trench gate structure in each of the plurality of device formation regions and the impurity concentration [cm ⁻³ ] of -4.6×10 ²¹ to -1.6×10 ²¹ [cm ⁻³ /cm]. The processed wafer according to claim 6, wherein the base layer constituting film has a slope of an approximation line obtained from the relationship between the film thickness [μm] of the portion of the base layer constituting film in contact with the trench gate structure in each of the plurality of device formation regions and the impurity concentration [cm ⁻³ ] of -3.9×10 ²¹ to -2.3×10 ²¹ [cm ⁻³ /cm]. The processed wafer according to claim 6, wherein the base layer constituting film has a slope of -3.1 x 1021 [cm- ³ /cm] obtained by the relationship between the film thickness [μm] of the portion of the base layer constituting film in contact with the trench gate structure ⁱⁿ each of the plurality of device formation regions and the impurity concentration [cm ^-3 ].

Images