JP7323422B2 - TRANSMISSION SYSTEM, TRANSMISSION DEVICE, AND CLOCK SYNCHRONIZATION METHOD - Google Patents

Description

TECHNICAL FIELD The present application relates to a transmission system, a transmission device, and a clock synchronization method.

For example, data signals such as audio and video for streaming distribution are packetized and transmitted between nodes on a route at a constant transmission rate. If the frequency of the clock signal for transmitting the data signal is not synchronized between the transmission devices of the transmitting side node and the receiving side node, the data signal will be delayed and the output will be stopped, resulting in deterioration of the quality of the streaming distribution service. There is a risk.

For this reason, in the case of a synchronous network such as a leased line, for example, a transmission device at each node is supplied with a highly accurate reference clock used for signal transmission. An asynchronous network such as a versatile Ethernet line is used. In the case of an asynchronous network, the transmission equipment of each node uses methods such as PTP (Precision Time Protocol) and Sync-E. Synchronization to a reference clock can be obtained.

However, even when using an asynchronous network, using a highly accurate reference clock increases network and device costs. For this reason, the transmission device of each node performs phase synchronization control using, for example, the count value of the clock signal extracted from the data signal without using the reference clock (see Patent Document 1, for example). According to the phase synchronization control, even if the delay time of the data signal fluctuates according to the state of the transmission line, the frequency of the clock signal can follow the fluctuation.

JP-A-2000-174742

However, the frequency of the clock signal may vary greatly depending on the state of the device from which the data signal is input. In this case, an error occurs in the frequency of the clock signal in each transmission device of the transmitting side node and the receiving side node, and it is difficult to quickly converge the frequency error by phase synchronization control and synchronize the clock signal frequencies. For this reason, an error occurs between the data signal input rate to the transmitting node transmission device and the data signal output rate from the receiving node transmission device.

On the other hand, it is possible to provide the transmission equipment of each node with a buffer that stores the amount of packets that can sufficiently absorb the rate difference, but the more the amount of buffer increases, the longer the retention time of packets in the transmission equipment. Therefore, the delay time of the data signal may increase.

An object of the present invention is to provide a transmission system, a transmission device, and a clock synchronization method capable of improving synchronization performance of clock frequencies between transmission devices.

In one aspect, a transmission system includes a first transmission device that generates and transmits a packet from a data signal, and a second transmission device that receives the packet and reproduces the data signal from the packet, The first transmission device includes an extraction unit for extracting an input data clock signal from the data signal, a multiplier for generating a multiplied clock signal by multiplying the input data clock signal, and a phase of the input data clock signal as: a first counter for counting pulses of the multiplied clock signal ; a first generator for generating a first device clock signal; and a frequency divider for generating a frequency-divided clock signal by frequency-dividing the input data clock signal. a first measuring unit for measuring a first frequency of said input data clock signal by counting pulses of said first device clock signal during a period of said divided clock signal; and when said packet is transmitted. and an imparting unit that imparts a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal to the packet, wherein the second transmission device adds the multiplied clock signal from the packet. an acquisition unit that acquires a pulse count value of a signal and a pulse count value of the first device clock signal ; a second generation unit that generates an output data clock signal; an output unit for outputting in synchronization with the output data clock signal; and a control unit for controlling the frequency of the output data clock signal based on the pulse count value of the multiplied clock signal and the pulse count value of the first device clock signal. and

In one aspect, in a transmission apparatus that generates packets from a data signal and transmits the data signal from the packets to another transmission apparatus that reproduces the data signal, the extraction unit extracts an input data clock signal from the data signal. a multiplier for generating a multiplied clock signal by multiplying the input data clock signal; a counter for counting pulses of the multiplied clock signal as the phase of the input data clock signal; and a first device clock signal . a frequency dividing unit for generating a frequency-divided clock signal by frequency-dividing the input data clock signal; and counting pulses of the first device clock signal during a period of the frequency-divided clock signal . a measurement unit for measuring the first frequency of the input data clock signal ; and an adding unit for adding to the packet.

In one aspect, a clock synchronization method includes clock synchronization between a first transmission device for generating and transmitting packets from a data signal and a second transmission device for receiving said packets and recovering said data signal from said packets. In the synchronization method, the first transmission device extracts an input data clock signal from the data signal , multiplies the input data clock signal to generate a multiplied clock signal, and uses the phase of the input data clock signal as the counting pulses of the multiplied clock signal to generate a first device clock signal ; dividing the input data clock signal to generate a divided clock signal; measuring a first frequency of the input data clock signal by counting pulses of the device clock signal; and determining a count of pulses of the multiplied clock signal and the number of pulses of the first device clock signal when the packet is transmitted; A pulse count value is given to the packet, and the second transmission device acquires the pulse count value of the multiplied clock signal and the pulse count value of the first device clock signal from the packet, and outputs data. A clock signal is generated, the data signal reproduced from the packet is output in synchronization with the output data clock signal, and a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal are generated. A method for controlling the frequency of the output data clock signal based on:

As one aspect, it is possible to improve synchronization performance of clock frequencies between transmission devices.

1 is a configuration diagram showing an example of an asynchronous network; FIG. 1 is a configuration diagram showing an example of a transmission system; FIG. 5 is a time chart showing an example of processing for adding a time stamp to a packet; 4 is a time chart showing an example of control for bringing the frequency of an output data clock signal closer to a target value; 9 is a flowchart illustrating an example of packet transmission processing; 4 is a flowchart showing an example of control processing for the frequency of an output data clock signal; 7 is a flowchart illustrating an example of target value determination processing; FIG. 4 is a diagram showing an example of changes in the frequencies of an input data clock signal and an output data clock signal with respect to time;

FIG. 1 is a configuration diagram showing an example of an asynchronous network. Asynchronous networks are used for data transmission services as an example. For example, a transmitting station 90 and a receiving station 91 are provided as facilities for the data transmission service.

One or more transmission devices 1 are provided in each of the transmitting station 90 and the receiving station 91 . The transmission device 1 accommodates digital data in a data signal and transmits the data signal. Data signals are packetized and transmitted on the transmission line between the transmitting station 90 and the receiving station 91 .

A data signal is transmitted from the transmitting station 90 to the receiving station 91 and transmitted to equipment (not shown) connected to the output side of the receiving station 91 .

The asynchronous network does not have provision for a common reference clock supplied to the transmission device 1 . Therefore, frequency synchronization of clock signals for transmitting data signals is established between the transmission devices 1 of the transmitting station 90 and the receiving station 91 .

If frequency synchronization is not established, for example, if the frequency of the clock signal of the transmission device 1 of the transmission station 90 is higher than the frequency of the clock signal of the transmission device 1 of the reception station 91, the input of the data signal to the transmission device 1 of the transmission station 90 Since the rate is higher than the output rate from the transmission device 1 of the receiving station 91 , data signal loss occurs within the transmission device 1 of the receiving station 91 . When the frequency of the clock signal of the transmission device 1 of the transmission station 90 is lower than the frequency of the clock signal of the transmission device 1 of the reception station 91, the input rate of the data signal to the transmission device 1 of the transmission station 90 is the transmission rate of the reception station 91. Since the output rate is lower than the output rate from the device 1, the output of the data signal is interrupted.

On the other hand, it is also possible to provide a buffer in the transmission device 1 for storing the amount of packets sufficient to absorb the rate difference. However, as the amount of buffering increases, the retention time of packets in the transmission device 1 increases, which may increase the delay time of the data signal. In particular, in the case of streaming distribution, service quality may deteriorate due to an increase in the delay time of data signals.

Therefore, the transmission device 1 of the transmission station 90 gives each packet a count value indicating the phase and frequency of the clock signal extracted from the input data signal, and transmits the packet to the transmission device 1 of the reception station 91 . The transmission device 1 of the receiving station 91 controls the frequency of the clock signal for outputting the data signal based on each count value. Combined use of frequency synchronization improves the synchronization performance of the frequency of the clock signal between the transmission device 1 of the transmitting station 90 and the transmission device 1 of the receiving station 91 compared to the case where only phase synchronization control is performed.

FIG. 2 is a configuration diagram showing an example of a transmission system. The transmission system includes a transmission unit 2 and a reception unit 3 connected to each other via a transmission line 9 such as a LAN (Local Area Network) cable or optical fiber. The transmission unit 2 is an example of a first transmission device, and is provided in the transmission device 1 of the transmission station 90 . The receiving unit 3 is an example of a second transmission device, and is provided in the transmission device 1 of the receiving station 91 . Note that the transmission device 1 may be provided with units other than the transmission unit 2 and the reception unit 3 as appropriate.

The transmission unit 2 extracts the input data clock signal CLKs from the input data signal S. The transmission unit 2 generates a time stamp TS#1 as a count value related to the phase of the input data clock signal CLKs, and generates a time stamp TS#2 as a count value related to the frequency of the input data clock signal CLKs. The transmission unit 2 generates a packet (PKT) from the data signal S and adds time stamps TS#1 and TS#2 to the packet when transmitting the packet.

The receiving unit 3 receives the packets from the transmitting unit 2, acquires the time stamps TS#1 and TS#2 from the packets, and determines the frequency Fr of the output data clock signal CLKr based on the time stamps TS#1 and TS#2. Control. The receiving unit 3 reproduces the data signal S from the packet and outputs it in synchronization with the output data clock signal CLKr. The configurations of the transmission unit 2 and the reception unit 3 are described below.

The transmission unit 2 includes a data writing unit 20, a buffer (BUFF) 21, a transmission unit 22, a clock (CLK) extraction unit 23, a time stamp (TS) addition unit 24, a phase time stamp generation unit 25, and a frequency time stamp generation unit 26. , and a transmitter clock source 27 . The data writing unit 20, the transmitting unit 22, the CLK extracting unit 23, the TS adding unit 24, the phase time stamp generating unit 25, and the frequency time stamp generating unit 26 are formed by circuits such as FPGA and ASIC, for example.

A data signal S is input to the data writing unit 20 and the CLK extracting unit 23 from another device (not shown). The data signal S is a continuous digital signal and contains audio data, video data, and the like.

The data writing unit 20 writes the data signal S to the buffer 21 . The buffer 21 is, for example, a storage space for video data and audio data allocated to a memory.

For example, when data for the payload of one packet is accumulated in the buffer 21 , the transmission unit 22 reads the data from the buffer 21 and adds a header to generate a packet PKT and outputs it to the transmission path 9 . Packet PKT includes, for example, an IP (Internet Protocol) packet, but is not limited to this.

The transmission unit 22 may have, for example, a light source and an optical modulator for converting the electrical signal of the packet PKT into an optical signal. An electric signal or an optical signal is input to the receiving unit 3 from the transmission line 9 .

The CLK extraction unit 23 extracts the input data clock signal CLKs from the data signal S. The CLK extractor 23 includes, for example, a PLL (Phase Locked Loop) circuit. The CLK extractor 23 outputs the input data clock signal CLKs to the phase timestamp generator 25 and the frequency timestamp generator 26 .

The phase timestamp generator 25 has a multiplier circuit 250 and a clock (CLK) counter 251 . The multiplier circuit 250 is an example of a multiplier, and generates a multiplied clock signal CLKsa by multiplying the input data clock signal CLKs. The multiplier circuit 250 outputs the multiplied clock signal CLKsa to the CLK counter 251 .

The CLK counter 251 is an example of a first counter, and counts the count value Na in synchronization with the input data clock signal CLKs. For example, the CLK counter 251 increases the count value Na by one each time a pulse of the multiplied clock signal CLKsa is input. Thereby, the CLK counter 251 can detect the phase of the input data clock signal CLKs based on the count value Na in units of the period of the multiplied clock signal CLKsa.

The count value Na is used as a time stamp TS#1 indicating the phase of the input data clock signal CLKs. The CLK counter 251 outputs the count value Na to the TS adding section 24 .

The frequency time stamp generator 26 has a frequency dividing circuit 260 and a frequency measuring section 261 . The frequency dividing circuit 260 is an example of a frequency dividing section, and generates a frequency-divided clock signal CLKsb by dividing the input data clock signal CLKs by n (where n is an integer equal to or greater than 2). The frequency dividing circuit 260 outputs the frequency-divided clock signal CLKsb to the frequency measuring section 261 .

The frequency measurement unit 261 is an example of a first measurement unit, and measures the frequency Fs of the input data clock signal CLKs by counting the count value Nb in synchronization with the transmitter clock signal CLK1d.

The transmitter clock source 27 is an example of a first generator, generates a transmitter clock signal CLK1d, and outputs it to the frequency measuring section 261 . The transmitter clock source 27 is, for example, a crystal oscillator with a fixed oscillation frequency. Note that the frequency Fs of the input data clock signal CLKs is an example of a first frequency, and the transmitter clock signal CLK1d is an example of a first device clock signal.

The frequency measurement unit 261 measures the frequency Fs of the input data clock signal CLKs by counting the cycle of the frequency-divided clock signal CLKsb as the count value Nb. Therefore, the frequency measurement unit 261 can measure the frequency Fs with higher precision than when counting the period of the input data clock signal CLKs.

The frequency measurement unit 261 is, for example, a counter circuit, and counts the count value Nb in synchronization with the transmitter clock signal CLK1d. The frequency measurement unit 261 holds the count value Nb for each cycle of the frequency-divided clock signal CLKsb, and outputs it to the TS provision unit 24 as the count value Nb indicating the length of one cycle of the frequency-divided clock signal CLKsb.

The TS adding unit 24 is an example of a adding unit, and adds the count values Na and Nb when the packet is transmitted from the transmitting unit 22 to the packet as time stamps TS#1 and TS#2, respectively. The transmission unit 22 outputs a transmission pulse signal PLs indicating the timing of transmitting the packet to the TS adding unit 24 . That is, the transmission unit 22 notifies the TS addition unit 24 of the packet transmission timing.

The TS adding unit 24 outputs the count values Na and Nb at the time of inputting the transmission pulse signal PLs to the transmitting unit 22 as time stamps TS#1 and TS#2, respectively. The transmitter 22 inserts the time stamps TS#1 and TS#2 into the header of the packet.

FIG. 3 is a time chart showing an example of processing for adding time stamps TS#1 and TS#2 to packets.

Symbol Ga indicates the process of adding time stamp TS#1. The CLK counter 251 increments the count value Na by one each time a pulse of the multiplied clock signal CLKsa is input. The count value Na is output to the TS adding section 24 .

Further, the transmitting unit 22 outputs, for example, a transmission pulse signal PLs indicating the leading positions of the packets PKT#1 and #2 to be transmitted to the TS adding unit 24 . The position indicated by the transmission pulse signal PLs is not limited. For example, the transmission pulse signal PLs may indicate the tail ends of the packets PKT#1 and PKT#2.

When the transmission pulse signal PLs is input at time t2, the TS adding unit 24 adds the count value Na=9 at time t2 to the packet PKT#1 as the time stamp TS#1. Further, when the transmission pulse signal PLs is input at time t4, the TS adding unit 24 adds the count value Na=902 at time t4 to the packet PKT#2 as the time stamp TS#1.

As described above, the time stamp TS#1 indicates the count value Na of the multiplied clock signal CLKsa when the packets PKT#1 and PKT#2 are transmitted. It corresponds to the phase of the input data clock signal CLKs with t2 and t4 as references.

Symbol Gb indicates the process of adding time stamp TS#2. The frequency measurement unit 261 increments the count value Nb by one each time a pulse of the transmitter clock signal CLK1d is input. The frequency measuring unit 261 holds the count value Nb and resets it to 1 for each cycle of the frequency-divided clock signal CLKsb. Frequency measuring section 261 outputs the held count value Nb (holding value) to TS adding section 24 when transmission pulse signal PLs is input.

When the falling edge of the frequency-divided clock signal CLKsb is input at time t1, the frequency measurement unit 261 resets the count value Nb to 1 after holding the count value Nb=103 at the time of input. When transmission pulse signal PLs is input at time t2 (>t1), TS adding section 24 adds count value Nb=103 (holding value) at time t2 to packet PKT#1 as time stamp TS#2.

Further, when the falling edge of the frequency-divided clock signal CLKsb is input at time t3, the frequency measurement unit 261 resets the count value Nb to 1 after holding the count value Nb=102 at the time of input. When transmission pulse signal PLs is input at time t4 (>t3), TS adding unit 24 adds count value Nb=102 (holding value) at time t4 to packet PKT#2 as time stamp TS#2.

Thus, the time stamp TS#2 indicates the counter value Nb for one cycle of the frequency-divided clock signal CLKsb when the packets PKT#1 and PKT#2 are transmitted. corresponds to the frequency Fs of the input data clock signal CLKs based on the times t2 and t4 at which is transmitted.

Referring to FIG. 2 again, the packets with time stamps TS#1 and TS#2 are input from the transmission line 9 to the receiving unit 3. FIG.

The receiver unit 3 has a receiver 30 , a buffer (BUFF) 31 , a signal regenerator 32 , a phase controller 33 , a frequency comparator 34 and a receiver clock source 35 . The receiver 30, the signal reproducer 32, the phase controller 33, and the frequency comparator 34 are formed by circuits such as FPGA and ASIC, for example.

The receiving unit 30 receives packets input from the transmission line 9 . The receiving unit 30 may include, for example, a light source and a demodulator for converting optical signals to electrical signals and regenerating packets.

The receiver 30 removes the header from the packet, extracts data from the payload of the packet, and stores it in the buffer 31 . The buffer 31 is, for example, a storage space for video data and audio data allocated to a memory. The capacity of the buffer 31 is set based on, for example, the variation in packet delay time in the transmission line 9 and the phase difference between the input data clock signal CLKs and the output data clock signal CLKr.

The signal reproducing section 32 is an example of an output section, and outputs the data signal S reproduced from the packet to another unit (not shown) in synchronization with the output data clock signal CLKr. The signal reproducing unit 32 reproduces the data signal S by reading data from the buffer 31 according to the output data clock signal CLKr. Data signal S is output at a rate according to frequency Fr of output data clock signal CLKr.

Also, the receiving unit 30 is an example of an acquiring unit, and acquires the time stamps TS#1 and TS#2 from the header of the packet. That is, the receiving unit 30 acquires the count values Na and Nb when each packet is transmitted. The receiving unit 30 outputs the time stamp TS#1 together with the received pulse signal PLr to the phase control unit 33, and outputs the time stamp TS#2 to the frequency comparing unit .

The phase control section 33 has a phase difference calculation section 330 , a smoothing processing section 331 , a target value setting section 332 , a voltage control section 333 , a VCO (Voltage-Controlled Oscillator) 334 and a clock (CLK) counter 335 . Some of these processes may be realized by software processing in which a CPU (Central Processing Unit) reads a program from memory instead of hardware.

The VCO 334 is an example of a second generator, and generates an output data clock signal CLKr with a frequency Fr corresponding to the voltage Vc controlled by the voltage controller 333 . The frequency Fr of the output data clock signal CLKr is the sum of the frequency Fs of the input data clock signal CLKs and the phase control error Δf caused by the phase controller 33 . The output data clock signal CLKr is input to the CLK counter 335 , the signal reproducing section 32 and the frequency comparing section 34 .

CLK counter 335 is an example of a second counter, and counts count value Nr in synchronization with output data clock signal CLKr. The count value Nr corresponds to the phase of the output data clock signal CLKr based on the time when the packet was received. The CLK counter 335 outputs the count value Nr to the phase difference calculator 330 .

The phase difference calculator 330 compares the count value Na of the time stamp TS#1 and the count value Nr of the CLK counter 335 according to the input of the received pulse signal PLr. That is, the phase difference calculator 330 compares the count value Na with the count value Nr when the packet was received. The received pulse signal PLr indicates the head position of the packet, but is not limited to this, and may indicate the tail end, for example.

The phase difference calculator 330 calculates the difference ΔN between the count values Na and Nr. A difference ΔN between the count values Na and Nr indicates a phase difference between the input data clock signal CLKs and the output data clock signal CLKr. The difference ΔN is output to the smoothing processing section 331 .

A smoothing processor 331 smoothes the difference ΔN. This suppresses the influence of fluctuations in the packet delay time in the transmission line 9 on the control of the frequency Fr of the output data clock signal CLKr. The smoothing processing unit 331 calculates the smoothed difference ΔNm from, for example, the time average of the difference ΔN or the average for each predetermined number of packets. The smoothed difference ΔNm is output to target value setting section 332 .

The target value setting unit 332 sets the target value Fo according to the comparison result of the count values Na and Nr. For example, the target value setting unit 332 sets the target value Fo of the frequency Fr of the output data clock signal CLKr based on the smoothed difference ΔNm. The target value Fo is input to the voltage control section 333 .

Voltage control unit 333 controls voltage Vc of VCO 334 according to target value Fo. Accordingly, the target value setting unit 332 and the voltage control unit 333 control the frequency Fr of the output data clock signal CLKr to approach the target value Fo.

FIG. 4 is a time chart showing an example of control for bringing the frequency Fr of the output data clock signal CLKr close to the target value Fo. In this example, it is assumed that the difference ΔN is the same value as the smoothed difference ΔNm.

CLK counter 335 counts count value Nr in synchronization with output data clock signal CLKr. For example, the CLK counter 335 increments the count value Nr by one each time a pulse of the output data clock signal CLKr is input.

Phase difference calculator 330 acquires time stamp TS#1 from the header of the packet in response to the input of received pulse signal PLr. For example, phase difference calculator 330 acquires time stamp TS#1 indicating count value Na=9 at time t5 when received pulse signal PLr is input. The phase difference calculator 330 calculates the difference ΔN=−3 (=9−12) between the count value Nr=12 at time t5 and the count value Na=9 at time stamp TS#1.

Target value setting unit 332 determines that count value Nr is ahead of count value Na based on difference ΔN=−3, and sets target value Fo of frequency Fr of output data clock signal CLKr to a value lower than a predetermined reference value. set. Voltage control unit 333 applies voltage Vc corresponding to target value Fo to VCO 334 .

Further, phase difference calculator 330 acquires time stamp TS#1 indicating count value Na=902 at time t6 when received pulse signal PLr is input. The phase difference calculator 330 calculates the difference ΔN=−1 (=902−903) between the count value Nr=903 at time t6 and the count value Na=902 at time stamp TS#1.

The target value setting unit 332 determines that the progress of the count value Nr with respect to the count value Na has decreased based on the difference ΔN=−1, and sets the target value Fo of the frequency Fr of the output data clock signal CLKr to the previous control value (for example -30) to a higher value (eg -10). Voltage control unit 333 applies voltage Vc corresponding to target value Fo to VCO 334 .

For example, the target value setting unit 332 calculates a value obtained by subtracting the previous smoothed difference ΔNm from the new smoothed difference ΔNm as the control amount of the frequency Fr. The voltage control unit 333 controls the voltage Vc so that the frequency Fr changes by the control amount.

Moreover, the target value setting unit 332 may calculate the control amount of the frequency Fr by PID (Proportional-Integral-Differential) control. In this case, the target value setting unit 332 calculates, from the average value of the plurality of differences ΔN, the difference of the frequency Fr used for the P term (proportional term), the phase error of the frequency Fr used for the I term (integral term), and the D term The rate of change of the frequency Fr used for the (differential term) is calculated.

The target value setting unit 332 calculates the sum of products of the P term, the I term, and the D term and their respective coefficients as the control amount of the frequency Fr. Voltage control unit 333 controls voltage Vc so that the control amount of frequency Fr becomes zero. As a result, the frequency Fr of the output data clock signal CLKr follows the target value Fo more smoothly than in the above case.

In this manner, the phase control unit 33 controls the frequency Fr of the output data clock signal CLKr so as to approach the target value Fo according to the comparison result of the count values Na and Nr. Therefore, the phase control section 33 can cause the phase of the output data clock signal CLKr to follow the phase fluctuation of the input data clock signal CLKs.

However, if the delay time of the packet in the transmission line 9 fluctuates or if the frequency Fs of the input data clock signal CLKs fluctuates greatly, the error between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr Since the phase control error Δf increases, the difference between the input rate of the data signal S to the transmitting unit 2 and the output rate from the receiving unit 3 also increases.

On the other hand, the receiving unit 3 may be provided with a buffer for storing the amount of packets that can sufficiently absorb the rate difference. , the delay time of the data signal S may increase.

Therefore, the target value setting unit 332 and the voltage control unit 333 shown in FIG. 2 control the frequency Fr of the output data clock signal CLKr based on the count values Na, Nb indicated by the time stamps TS#1, #2. Therefore, frequency Fr of output data clock signal CLKr is controlled from the phase of input data clock signal CLKs indicated by count value Na and the measured value of frequency Fs of input data clock signal CLKs indicated by count value Nb.

Here, since the count value Nb is counted by the transmission device clock signal CLK1d of the transmission unit 2, the measured value of the frequency Fs is not affected by variations in the packet delay time in the transmission line 9. FIG. Therefore, even if the frequency Fs of the input data clock signal CLKs changes greatly, in addition to the phase control of the output data clock signal CLKr based on the count value Na, the frequency Fr of the output data clock signal CLKr can be quickly controlled based on the count value Nb. becomes possible.

Therefore, the clock frequency synchronization performance between the transmitting unit 2 and the receiving unit 3 is improved. Note that the target value setting unit 332 and the voltage control unit 333 are examples of a control unit.

Target value setting unit 332 limits the range of target value Fo based on frequency difference Δfd input from frequency comparison unit 34 . The frequency comparator 34 detects the frequency difference Δfd between the input data clock signal CLKs and the output data clock signal CLKr based on the time stamp TS#2. The frequency difference Δfd is a value obtained by estimating a phase control error Δf that is an error between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr. The frequency difference Δfd includes a measurement error due to the precision of the transmitter clock signal CLK1d of the transmitter unit 2 and the receiver clock signal CLK2d of the receiver unit 3 .

The frequency comparing section 34 has a frequency estimating section 340 , an error detecting section 341 and a frequency measuring section 342 . Some of these processes may be realized by software processing in which the CPU reads programs from memory instead of hardware.

Frequency estimation section 340 estimates frequency Fs of input data clock signal CLKs from time stamp TS#2.

Nb=T×F1d Expression (1)
T≈n/Fs Expression (2)
Fs=n×F1d/Nbm Expression (3)

The count value Nb indicated by the time stamp TS#2 is expressed by the above equation (1) from the period T of the frequency-divided clock signal CLKsb and the frequency F1d of the transmitter clock signal CLK1d. Here, the period T is a value including quantization error, and is expressed by the above equation (2) from the frequency division number n of the frequency-divided clock signal CLKsb and the frequency Fs of the input data clock signal CLKs. . That is, the cycle T of the frequency-divided clock signal CLKsb is n times the cycle (1/Fs) of the input data clock signal CLKs.

Therefore, the frequency Fs of the input data clock signal CLKs can be calculated from the equations (1) and (2) as shown in the equation (3). Here, Nbm is the average value of the count value Nb at regular time intervals. For example, when timestamps TS#2 indicating count values Nb=103 and 102 are obtained from two packets received within a certain period of time, the average value Nbm is 102.5 (=(103+102)/2). becomes.

Frequency estimating section 340 estimates frequency Fs of input data clock signal CLKs by equation (3). Thus, frequency Fs is obtained from count value Nb of time stamp TS#2.

The measurement error of the frequency Fs generated by the frequency measurement unit 261 does not depend on the variation of the packet delay time in the transmission path 9, but depends on the accuracy ΔFosc (>0) of the frequency F1d of the transmitter clock signal CLK1d of the transmitter unit 2. Almost match. The frequency estimator 340 notifies the error detector 341 of the frequency Fs.

Also, the frequency measuring section 342 is an example of a second measuring section, and measures the frequency Fr of the output data clock signal CLKr based on the receiver clock signal CLK2d. The frequency measurement unit 342 receives the receiver clock signal CLK2d from the receiver clock source 35 and the output data clock signal CLKr from the VCO 334 .

The receiver clock source 35 is an example of a third generator and generates the receiver clock signal CLK2d. The receiver clock source 35 is, for example, a crystal oscillator with a fixed oscillation frequency. Note that the receiving device clock signal CLK2d is an example of a second device clock signal.

The frequency measuring section 342 counts the period of the output data clock signal CLKr based on the receiving device clock signal CLK2d, for example, using the same technique as the frequency measuring section 342 of the transmission unit 2 . The frequency measurement unit 342 holds, for example, a count value corresponding to the cycle for each falling edge of the output data clock signal CLKr, and calculates the frequency Fr (=1/cycle) of the output data clock signal CLKr from the count value.

The measurement error of the frequency Fr generated by the frequency measurement unit 342 does not depend on the variation of the packet delay time in the transmission line 9, but substantially matches the accuracy ΔFosc of the frequency F2d of the receiver clock signal CLK2d. In this example, the accuracy ΔFosc of the frequency F1d of the transmitter clock signal CLK1d and the frequency F2d of the receiver clock signal CLK2d are the same, but they may be different.

The frequency measurement unit 342 notifies the voltage control unit 333 and the error detection unit 341 of the frequency Fr. Voltage control unit 333 applies voltage Vc to VCO 334 according to the difference between target value Fo and frequency Fr.

The error detector 341 calculates a frequency difference Δfd (=Fr−Fs) as the difference between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr. The error detection unit 341 notifies the target value setting unit 332 of the frequency difference Δfd.

The target value setting unit 332 limits the range of the target value Fo based on the frequency difference Δfd. Thereby, the target value setting unit 332 can suppress the fluctuation of the target value Fo so that the phase control error Δf does not increase.

Δfd=Δf±2×ΔFosc Expression (4)

The frequency difference Δfd includes not only the phase control error Δf of the phase controller 33 but also the measurement errors ΔFosc of the frequency measurement units 261 and 342, and the total error is 2×ΔFosc. Therefore, the frequency difference Δfd is represented by Equation (4) above.

For example, when the accuracy ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d is ±10 (ppm), the total measurement error ΔFosc of the frequency measurement units 261 and 342 is approximately ±20 (ppm) (=2× 10). Therefore, the phase control error Δf may be 0 when the frequency difference Δfd is in the range of −20 to +20 (ppm), but the frequency difference Δfd is in the range of −20 to +20 (ppm). If it is outside, it will be greater than 0.

Therefore, if the frequency difference Δfd exceeds the measurement error range (−2×ΔFosc to +2×ΔFosc) based on the accuracies ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d, the target value setting unit 332 sets the target value Limit the range of Fo. Therefore, when there is a phase control error Δf, that is, when the error Δf is not 0, the target value setting unit 332 can appropriately suppress an increase in the error Δf by limiting the range of the target value Fo. can.

Here, since the frequency difference Δfd may be a positive value or a negative value, the range of the suppressed error Δf is twice the above error range. That is, the range of the error Δf is defined within the range of −4×ΔFosc to +4×ΔFosc. For example, if the accuracy ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d is ±10 (ppm), the range of the error Δf is −40 to +40 (ppm). By defining the error Δf in this way, the design of the transmission system is facilitated.

For example, the target value setting unit 332 excludes from the range of the target value Fo a range in which the measurement error based on the accuracies ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d is an abnormal value. Therefore, frequency Fs of input data clock signal CLKs and frequency Fr of output data clock signal CLKr can be synchronized with high precision.

Next, each process of the transmission unit 2 and the reception unit 3 will be described.

FIG. 5 is a flowchart illustrating an example of packet transmission processing. First, the data signal S is input to the data writing unit 20 (step St1).

The data writing unit 20 stores the data of the data signal S in the buffer 21 (step St2). The transmission unit 22 compares the amount of data stored in the buffer 21 with a predetermined amount M (step St3). The predetermined amount M is, for example, the amount of data that can be accommodated in the payload of a packet.

When the storage amount is less than the predetermined amount M (No in step St3), the transmission unit 22 executes the process of step St2 again. Further, when the storage amount is equal to or greater than the predetermined amount M (Yes in step St3), the transmission unit 22 reads data from the buffer 21 and generates a packet (step St4). After generating the packet, the transmission unit 22 outputs the transmission pulse signal PLs to the TS adding unit 24 .

The TS adding unit 24 acquires the count values Na and Nb from the CLK counter 251 and the frequency measuring unit 261 according to the transmission pulse signal PLs (step St5). The TS adding unit 24 adds time stamps TS#1 and TS#2 indicating the count values Na and Nb, respectively, to the header of the packet (step St6).

The transmitter 22 transmits the packet (step St7). Thus, packet transmission processing is executed.

FIG. 6 is a flowchart showing an example of control processing for the frequency Fr of the output data clock signal CLKr. First, the receiver 30 receives a packet from the transmission unit 2 (step St11). Receiving section 30 outputs reception pulse signal PLr in response to reception of a packet. Next, the receiver 30 acquires time stamps TS#1 and TS#2 from the packet (step St12). The subsequent steps St13, St14 and steps St15-17 may be executed in parallel.

Phase difference calculator 330 calculates difference ΔN between count value Na indicated by time stamp TS#1 and count value Nr synchronized with output data clock signal CLKr in response to input of received pulse signal PLr. It is calculated as a phase difference between CLKs and the output data clock signal CLKr (step St13). The smoothing processing unit 331 calculates a smoothed difference ΔNm from the differences ΔN for a plurality of packets, for example (step St14).

Further, frequency estimating section 340 estimates frequency Fs of input data clock signal CLKs from count value Nb indicated by time stamp TS#2 (step St15). The frequency measurement unit 342 measures the frequency Fr of the output data clock signal CLKr (step St16). The error detector 341 calculates the frequency difference Δfd between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr (step St17).

The target value setting unit 332 determines the target value Fo of the frequency Fr (step St18). The process of determining the target value Fo will be described later.

The voltage control unit 333 applies the voltage Vc corresponding to the target value Fo to the VCO 334 (step St19). In this manner, control processing of frequency Fr of output data clock signal CLKr is performed.

FIG. 7 is a flow chart showing an example of processing for determining the target value Fo. This process is executed in step St18 described above.

The target value setting unit 332 compares the absolute value of the frequency difference Δfd with the total error (2×ΔFosc) (step St31).

When the absolute value of the frequency difference Δfd is equal to or less than 2×ΔFosc (No in step St31), the target value setting unit 332 determines that the frequency difference Δfd is a normal value. A new target value Fo is determined from the amount of change per unit time (step St36). Note that the initial value of the target value Fo' may be set to 0, for example, or may be another value. Thereafter, the target value setting unit 332 sets the previous target value Fo' as the new target value Fo (step St34), and terminates the process.

When the absolute value of the frequency difference Δfd is larger than 2×ΔFosc (Yes in step St31), the target value setting unit 332 determines the frequency difference Δfd to be an abnormal value. Then, it is determined whether the frequency difference Δfd determined as an abnormal value is greater than 0, that is, whether it is a positive value or a negative value (step St32). Target value setting unit 332 calculates target value Fo depending on whether frequency difference Δfd is a positive value or a negative value.

Fo=Fo'-(Δfd-2×ΔFosc) Equation (5)

When the frequency difference Δfd is a positive value (Yes in step St32), the target value setting unit 332 sets the frequency difference Δfd and the total error ( 2×ΔFosc), the new target value Fo is calculated by subtracting the difference (Δfd−2×ΔFosc) (step St33). At this time, the target value setting unit 332 calculates the target value Fo from the above equation (5), for example.

As a result, the target value Fo decreases from the previous target value Fo' by a value obtained by subtracting the total error (2×ΔFosc) from the frequency difference Δfd. That is, when the frequency difference Δfd is a positive value exceeding 2×ΔFosc, the target value setting unit 332 reduces the target value Fo from the previous target value Fo′ so that the frequency difference Δfd falls within the normal range. .

For example, when the frequency difference Δfd=30 (ppm) and the accuracy ΔFosc=10 (ppm), the target value setting unit 332 determines that the frequency difference Δfd is abnormal because the frequency difference Δfd>20 (ppm) holds in step St31. value. Since the frequency difference Δfd is a positive value, the target value setting unit 332 calculates the target value Fo as Fo′−10 (ppm) (=30−2×10) in step St33. As a result, the frequency difference Δfd is reduced by 10 (ppm) from 30 (ppm) to 20 (ppm) (=30-10), and is therefore controlled within the range of normal values.

Fo=Fo'+(-Δfd-2×ΔFosc) Expression (6)

When the frequency difference Δfd is a negative value (No in step St32), the target value setting unit 332 adds (−Δfd) and the total error to the previous target value Fo′ so that the frequency difference Δfd is within the normal range. A new target value Fo is calculated by adding the difference (-.DELTA.fd-2.times..DELTA.Fosc) of (2.times..DELTA.Fosc) (step St35). At this time, the target value setting unit 332 calculates the target value Fo from the above equation (6), for example.

As a result, the target value Fo increases from the previous target value Fo' by a value obtained by subtracting the total error 2×ΔFosc from the frequency difference Δfd. That is, when the frequency difference Δfd is a negative value exceeding 2×ΔFosc, the target value setting unit 332 increases the target value Fo from the previous target value Fo′ so that the frequency difference Δfd falls within the normal range. .

For example, when the frequency difference Δfd=−30 (ppm) and the accuracy ΔFosc=10 (ppm), the target value setting unit 332 determines that the frequency difference Δfd<−20 (ppm) in step St31. is judged to be an outlier. Since the frequency difference Δfd is a negative value, the target value setting unit 332 calculates the target value Fo as Fo′+10 (ppm) (=−(−30)−2×10) in step St35. As a result, the frequency difference Δfd increases from −30 (ppm) by 10 (ppm) to −20 (ppm) (=−30+10), and is therefore controlled within the normal range.

In this way, the target value setting unit 332 sets the error based on the accuracy ΔFosc of each of the transmitter clock signal CLK1d and the receiver clock signal CLK2d from the range of the target value Fo, excluding the range where the frequency difference Δfd is determined to be abnormal. (−4×ΔFosc to +4×ΔFosc). As a result, an increase in the error Δf can be suppressed, and the worst value of the error Δf can be specified without depending on the delay variation of the transmission path.

Next, reduction of the delay time according to this embodiment will be described.

FIG. 8 is a diagram showing an example of changes with time in the frequencies Fs and Fr of the input data clock signal CLKs and the output data clock signal CLKr.

Symbol Gc indicates relative changes in frequencies Fs and Fr in the comparative example. In the comparative example, the target value setting unit 332 does not limit the target value Fo based on the frequency difference Δfd. In other words, the phase control unit 33 does not use the time stamp TS#2 for controlling the frequency Fr.

The frequency Fs of the input data clock signal CLKs increases by ΔFs (>0) at time Ta. The frequency Fr of the output data clock signal CLKr is the same as the frequency Fs before the time Ta, but at the time Ta, the difference from the frequency Fs is ΔFs.

However, the frequency Fr of the output data clock signal CLKr follows the frequency Fs due to the phase control of the phase controller 33, and matches the frequency Fs at the time Tb after the period K from the time Ta.

Symbol Gd indicates relative changes in frequencies Fs and Fr in the example. Also in this example, the frequency Fs of the input data clock signal CLKs increases by ΔFs (>0) at time Ta. At this time, the time required for the frequency Fr to follow the frequency Fs is K, assuming that the phase control by the phase controller 33 is the same as in the comparative example.

However, unlike the comparative example, the target value setting unit 332 limits the target value Fo of the frequency Fr based on the frequency difference Δfd. increase to As a result, the error .DELTA.f becomes 4.times..DELTA.Fosc at maximum based on the measurement errors of the frequencies Fs and Fr.

Here, the hatched areas Sa and Sb correspond to the amount of storage in the buffer 31 necessary for preventing packet loss during the period K until tracking of the frequency Fr is completed in the comparative example and the embodiment. It should be noted that a storage amount corresponding to variations in packet delay time in the transmission line 9 is separately required.

As an example, if ΔFs=200 (ppm), K=300 (sec), and ΔFosc=10 (ppm), the storage amount in the case of the comparative example corresponds to 30 (ms) (=200×300/2) The storage amount in the embodiment corresponds to 6 (ms) (=40×300/2). Therefore, in the case of the embodiment, the packet delay time is reduced more than in the case of the comparative example due to the limitation of the target value Fo.

The embodiments described above are examples of preferred implementations of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

Note that the following notes are further disclosed with respect to the above description.
(Appendix 1) a first transmission device that generates and transmits a packet from a data signal;
a second transmission device that receives the packet and reproduces the data signal from the packet;
The first transmission device,
an extraction unit for extracting an input data clock signal from the data signal;
a first counter that counts a first count value in synchronization with the input data clock signal;
a first generator for generating a first device clock signal;
a first measuring unit that measures a first frequency of the input data clock signal by counting a second count value in synchronization with the first device clock signal;
a adding unit that adds the first count value and the second count value to the packet when the packet is transmitted;
The second transmission device,
an acquisition unit that acquires the first count value and the second count value from the packet;
a second generator for generating an output data clock signal;
an output unit for outputting the data signal reproduced from the packet in synchronization with the output data clock signal;
and a control section for controlling the frequency of the output data clock signal based on the first count value and the second count value.
(Appendix 2) The second transmission device
a second counter that counts a third count value in synchronization with the output data clock signal;
a third generator for generating a second device clock signal;
a second measuring unit for measuring a second frequency of the output data clock signal based on the second device clock signal;
The control unit
controlling the second frequency to approach a target value according to a comparison result between the first count value and the third count value when the packet is received;
The transmission system according to appendix 1, wherein the range of the target value is limited based on a difference between the first frequency obtained from the second count value and the second frequency.
(Additional Note 3) If the difference between the first frequency and the second frequency exceeds the measurement error range based on the respective accuracies of the first device clock signal and the second device clock signal, the control unit controls the target 3. Transmission system according to clause 2, characterized in that it limits the range of values.
(Additional Note 4) The control unit is characterized in that, from the range of the target values, a range in which a measurement error based on the respective accuracies of the first device clock signal and the second device clock signal is determined to be abnormal. The transmission system according to Appendix 3.
(Appendix 5) The first transmission device has a frequency divider that generates a frequency-divided clock signal by frequency-dividing the input data clock signal,
5. The transmission system according to any one of appendices 1 to 4, wherein the first measurement unit measures the first frequency by counting the period of the frequency-divided clock signal as the second count value.
(Appendix 6) The first transmission device has a multiplier that generates a multiplied clock signal by multiplying the input data clock signal,
6. The transmission system according to any one of appendices 1 to 5, wherein the first counter counts the first count value in synchronization with the multiplied clock signal.
(Appendix 7) In a transmission device that generates a packet from a data signal and transmits the data signal from the packet to another transmission device that reproduces the data signal,
an extraction unit for extracting an input data clock signal from the data signal;
a counter that counts a first count value in synchronization with the input data clock signal;
a generator that generates a device clock signal;
a measurement unit that measures the frequency of the input data clock signal by counting a second count value in synchronization with the device clock signal;
and an adding unit that adds the first count value and the second count value to the packet when the packet is transmitted.
(Supplementary note 8) a frequency dividing unit that generates a frequency-divided clock signal by frequency-dividing the input data clock signal;
8. The transmission apparatus according to claim 7, wherein the measurement unit measures the first frequency by counting the period of the frequency-divided clock signal as the second count value.
(Appendix 9) A multiplier that generates a multiplied clock signal by multiplying the input data clock signal,
9. The transmission device according to appendix 7 or 8, wherein the counter counts the first count value in synchronization with the multiplied clock signal.
(Appendix 10) In a clock synchronization method between a first transmission device that generates and transmits packets from a data signal and a second transmission device that receives the packets and regenerates the data signals from the packets,
The first transmission device,
extracting an input data clock signal from the data signal;
counting a first count value in synchronization with the input data clock signal;
generating a first device clock signal;
measuring a first frequency of the input data clock signal by counting a second count value synchronously with the first device clock signal;
giving the packet the first count value and the second count value when the packet is transmitted;
The second transmission device,
obtaining the first count value and the second count value from the packet;
generate an output data clock signal,
outputting the data signal reproduced from the packet in synchronization with the output data clock signal;
A clock synchronization method, comprising: controlling the frequency of the output data clock signal based on the first count value and the second count value.
(Appendix 11) The second transmission device,
counting a third count value in synchronization with the output data clock signal;
generating a second device clock signal;
measuring a second frequency of the output data clock signal based on the second device clock signal;
controlling the second frequency to approach a target value according to a comparison result between the first count value and the third count value when the packet is received;
11. The clock synchronization method according to claim 10, wherein the range of the target value is limited based on the difference between the first frequency obtained from the second count value and the second frequency.
(Appendix 12) When the difference between the first frequency and the second frequency exceeds the measurement error range based on the accuracy of each of the first device clock signal and the second device clock signal, 12. The method of claim 11, wherein the target value range is limited.
(Supplementary Note 13) The second transmission device is characterized in that, from the range of the target values, a range in which a measurement error based on the respective accuracies of the first device clock signal and the second device clock signal is determined to be abnormal is excluded. 13. The clock synchronization method of claim 12.
(Additional Note 14) The first transmission device divides the frequency of the input data clock signal to generate a frequency-divided clock signal, and counts the period of the frequency-divided clock signal as the second count value. 14. A clock synchronization method according to any one of claims 10 to 13, characterized in that one frequency is measured.
(Appendix 15) The first transmission device generates a multiplied clock signal by multiplying the input data clock signal, and counts the first count value in synchronization with the multiplied clock signal. 15. A clock synchronization method according to any one of 10-14.

1 transmission device 2 transmission unit 3 reception unit 22 transmission unit 23 clock extraction unit 24 time stamping unit 27 transmission device clock source 30 reception unit 32 signal reproduction unit 35 reception device clock source 250 multiplication circuit 251, 335 clock counter 260 frequency division circuit 261, 342 frequency measuring unit 332 target value setting unit 333 voltage control unit 334 VCO

Claims (6)

a first transmission device that generates and transmits a packet from a data signal;
a second transmission device that receives the packet and reproduces the data signal from the packet;
The first transmission device,
an extraction unit for extracting an input data clock signal from the data signal;
a multiplier that generates a multiplied clock signal by multiplying the input data clock signal;
a first counter that counts pulses of the multiplied clock signal as the phase of the input data clock signal ;
a first generator for generating a first device clock signal;
a frequency divider that generates a frequency-divided clock signal by frequency-dividing the input data clock signal;
a first measuring unit for measuring a first frequency of the input data clock signal by counting pulses of the first device clock signal during a period of the divided clock signal ;
a adding unit that adds a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal to the packet when the packet is transmitted;
The second transmission device,
an acquisition unit configured to acquire a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal from the packet;
a second generator for generating an output data clock signal;
an output unit for outputting the data signal reproduced from the packet in synchronization with the output data clock signal;
and a control section for controlling the frequency of the output data clock signal based on the pulse count value of the multiplied clock signal and the pulse count value of the first device clock signal . The second transmission device,
a second counter that counts pulses of the output data clock signal as the phase of the output data clock signal;
a third generator for generating a second device clock signal;
a second measuring unit for measuring a second frequency of the output data clock signal by counting pulses of the second device clock signal during periods of the output data clock signal;
The control unit
The second frequency is controlled so as to approach a target value according to a comparison result between the pulse count value of the multiplied clock signal and the pulse count value of the output data clock signal when the packet is received. ,
2. The transmission system according to claim 1, wherein the range of the target value is limited based on the difference between the first frequency obtained from the pulse count value of the first device clock signal and the second frequency. . When the difference between the first frequency and the second frequency exceeds the range of measurement error based on the accuracies of the first device clock signal and the second device clock signal, the control unit changes the range of the target value. 3. Transmission system according to claim 2, characterized in that it limits. 4. The method according to claim 3, wherein the control unit excludes a range in which a measurement error based on the respective accuracies of the first device clock signal and the second device clock signal is determined to be abnormal from the range of the target values. The transmission system described. In a transmission device that generates a packet from a data signal and transmits the data signal from the packet to another transmission device that reproduces the data signal,
an extraction unit for extracting an input data clock signal from the data signal;
a multiplier that generates a multiplied clock signal by multiplying the input data clock signal;
a counter that counts the pulses of the multiplied clock signal as the phase of the input data clock signal ;
a generator for generating a first device clock signal;
a frequency divider that generates a frequency-divided clock signal by frequency-dividing the input data clock signal;
a measuring unit for measuring a first frequency of the input data clock signal by counting pulses of the first device clock signal during a period of the divided clock signal ;
and an adding unit that adds the pulse count value of the multiplied clock signal and the pulse count value of the first device clock signal to the packet when the packet is transmitted. A clock synchronization method between a first transmission device for generating and transmitting packets from a data signal and a second transmission device for receiving said packets and recovering said data signal from said packets, comprising:
The first transmission device,
extracting an input data clock signal from the data signal;
generating a multiplied clock signal by multiplying the input data clock signal;
counting pulses of the multiplied clock signal as the phase of the input data clock signal ;
generating a first device clock signal;
generating a frequency-divided clock signal by frequency-dividing the input data clock signal;
measuring a first frequency of the input data clock signal by counting pulses of the first device clock signal during a period of the divided clock signal;
when the packet is transmitted , giving the packet a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal ;
The second transmission device,
obtaining a pulse count value of the multiplied clock signal and a pulse count value of the first device clock signal from the packet;
generate an output data clock signal,
outputting the data signal reproduced from the packet in synchronization with the output data clock signal;
and controlling the frequency of the output data clock signal based on the pulse count value of the multiplied clock signal and the pulse count value of the first device clock signal .

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