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JP7293160B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7293160B2
JP7293160B2 JP2020052530A JP2020052530A JP7293160B2 JP 7293160 B2 JP7293160 B2 JP 7293160B2 JP 2020052530 A JP2020052530 A JP 2020052530A JP 2020052530 A JP2020052530 A JP 2020052530A JP 7293160 B2 JP7293160 B2 JP 7293160B2
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JP
Japan
Prior art keywords
layer
gold
semiconductor device
bonding
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2020052530A
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English (en)
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JP2021153095A (ja
Inventor
誠 水上
達也 平川
知洋 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to JP2020052530A priority Critical patent/JP7293160B2/ja
Priority to CN202010875372.4A priority patent/CN113451247A/zh
Priority to US17/008,378 priority patent/US11462508B2/en
Publication of JP2021153095A publication Critical patent/JP2021153095A/ja
Priority to US17/898,177 priority patent/US12080680B2/en
Application granted granted Critical
Publication of JP7293160B2 publication Critical patent/JP7293160B2/ja
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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Description

本発明の実施形態は、半導体装置に関する。
パワー半導体モジュールでは、例えば、金属ベースの上に、絶縁基板を間に挟んで半導体チップが実装される。半導体チップは、例えば、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）、又は、ダイオードである。
半導体チップは、例えば、絶縁基板の上の金属層に、はんだを接合材として用いて接合される。しかし、パワー半導体モジュールの動作温度の高温化に伴い、はんだを接合材として用いた接合の耐熱性が問題になる。
接合の耐熱性を向上させる接合材の候補として、銀ナノペーストがある。銀ナノペーストは、銀の微粒子を溶媒中に分散させたペーストである。銀ナノペーストは、室温ではペースト状であるが、加熱により溶媒を揮発させることで、銀の薄膜に変化する。得られた銀薄膜は高融点であることから、高い耐熱性を有する接合が実現できる。
特開２００６－２０２９３８号公報
本発明が解決しようとする課題は、高い信頼性を有する半導体装置を提供することにある。
本発明の一態様の半導体装置は、半導体層と、金属層と、前記半導体層と前記金属層との間に設けられ、複数の銀粒子と、前記複数の銀粒子の間に存在する金を含む領域と、を含む接合層と、前記半導体層と前記接合層との間に設けられ、ニッケルを含む第１の中間層と、を備え、前記第１の中間層の金の原子濃度は、前記接合層の金の原子濃度よりも低い。
実施形態の半導体装置の模式断面図。 実施形態の半導体装置の一部の拡大模式断面図。 実施形態の半導体装置の一部の拡大模式断面図。 実施形態の半導体装置の製造方法を示す図。 実施形態の半導体装置の製造方法を示す図。 実施形態の半導体装置の製造方法を示す図。 実施形態の半導体装置の製造方法を示す図。 実施形態の半導体装置の製造方法を示す図。 比較例の半導体装置の一部の拡大模式断面図。
本明細書中、同一又は類似する部材については、同一の符号を付し、重複する説明を省略する場合がある。
本明細書中、部品等の位置関係を示すために、図面の上方向を「上」、図面の下方向を「下」と記述する場合がある。本明細書中、「上」、「下」の概念は、必ずしも重力の向きとの関係を示す用語ではない。
本明細書中の半導体装置を構成する部材の化学組成の定性分析及び定量分析は、例えば、二次イオン質量分析法（Ｓｅｃｏｎｄａｒｙ Ｉｏｎ Ｍａｓｓ Ｓｐｅｃｔｒｏｓｃｏｐｙ：ＳＩＭＳ）、エネルギー分散型Ｘ線分光法（Ｅｎｅｒｇｙ Ｄｉｓｐｅｒｓｉｖｅ Ｘ－ｒａｙ Ｓｐｅｃｔｒｏｓｃｏｐｙ：ＥＤＸ）、３次元アトムプローブ（３ Ｄｉｍｅｎｓｉｏｎａｌ Ａｔｏｍ Ｐｒｏｂｅ）により行うことが可能である。また、半導体装置を構成する部材の厚さ、部材の粒径、部材間の距離等の測定には、例えば、透過型電子顕微鏡（Ｔｒａｎｓｍｉｓｓｉｏｎ Ｅｌｅｃｔｒｏｎ Ｍｉｃｒｏｓｃｏｐｅ：ＴＥＭ）、走査型電子顕微鏡（Ｓｃａｎｎｉｎｇ Ｅｌｅｃｔｒｏｎ Ｍｉｃｒｏｓｃｏｐｅ：ＴＥＭ）を用いることが可能である。
実施形態の半導体装置は、半導体層と、金属層と、半導体層と金属層との間に設けられ、複数の銀粒子と、複数の銀粒子の間に存在する金を含む領域と、を含む接合層と、を備える。
図１は、実施形態の半導体装置の模式断面図である。
実施形態の半導体装置は、パワー半導体モジュール１００である。図１に示すように、実施形態のパワー半導体モジュール１００は、２個のＭＯＳＦＥＴが直列に接続されている。実施形態のパワー半導体モジュール１００は、１モジュールでハーフブリッジ回路を構成できる、いわゆる「２ｉｎ１」タイプのモジュールである。例えば、実施形態のパワー半導体モジュール１００を３個用いることにより３相インバータ回路を構成できる。
実施形態のパワー半導体モジュール１００は、２個のＭＯＳＦＥＴ１０、金属ベース１４、絶縁基板１６、樹脂ケース１８、接合層２０、第１の電力端子２２、第２の電力端子２４、ボンディングワイヤ２６、封止樹脂２８を備える。絶縁基板１６は、セラミック層１６ａ、表面金属層１６ｂ（金属層）、及び、裏面金属層１６ｃを有する。
なお、パワー半導体モジュール１００は、図示しないＡＣ端子及びゲート端子を備える。また、パワー半導体モジュール１００は、図示しない樹脂蓋を、封止樹脂２８の上に備えても構わない。
ＭＯＳＦＥＴ１０は、半導体層１０ａ、上部電極１０ｂ、下部電極１０ｃを有する。半導体層１０ａは、例えば、単結晶の炭化珪素（ＳｉＣ）である。上部電極１０ｂ及び下部電極１０ｃは、金属である。
絶縁基板１６は、金属ベース１４の上に設けられる。絶縁基板１６は、金属ベース１４とＭＯＳＦＥＴ１０との間に設けられる。絶縁基板１６は、金属ベース１４と、ＭＯＳＦＥＴ１０を電気的に分離する機能を有する。
絶縁基板１６は、セラミック層１６ａ、表面金属層１６ｂ、及び、裏面金属層１６ｃを有する。セラミック層１６ａは、表面金属層１６ｂと裏面金属層１６ｃとの間に設けられる。
セラミック層１６ａは、例えば、酸化アルミニウム、窒化アルミニウム、又は、窒化シリコンである。表面金属層１６ｂ及び裏面金属層１６ｃは、例えば、銅である。
接合層２０は、ＭＯＳＦＥＴ１０と絶縁基板１６との間に設けられる。接合層２０は、半導体層１０ａと表面金属層１６ｂとの間に設けられる。接合層２０は、下部電極１０ｃ及び表面金属層１６ｂに接する。接合層２０は、ＭＯＳＦＥＴ１０と絶縁基板１６を固定する機能を有する。
図２は、実施形態の半導体装置の一部の拡大模式断面図である。図２は、ＭＯＳＦＥＴ１０、接合層２０、及び、絶縁基板１６の一部の拡大模式断面図である。図２は、半導体層１０ａ、下部電極１０ｃ、接合層２０、及び、表面金属層１６ｂを示す。
下部電極１０ｃは、ニッケルシリサイド層３０（第２の中間層）、チタン層３１（第３の中間層）、ニッケル層３２（第１の中間層）を含む。ニッケルシリサイド層３０は、ニッケルシリサイドを含む第２の中間層の一例である。チタン層３１は、チタンを含む第３の中間層の一例である。ニッケル層３２は、ニッケルを含む第１の中間層の一例である。
ニッケル層３２は、半導体層１０ａと接合層２０との間に設けられる。ニッケルシリサイド層３０は、半導体層１０ａとニッケル層３２との間に設けられる。チタン層３１は、ニッケル層３２とニッケルシリサイド層３０との間に設けられる。
図３は、実施形態の半導体装置の一部の拡大模式断面図である。図３は、接合層２０を示す。接合層２０は、複数の銀粒子２０ａ、金領域２０ｂ（領域）、及び、ボイド２０ｃを含む。金領域２０ｂは、金を含む領域の一例である。
銀粒子２０ａは、いわゆる銀ナノ粒子である。銀粒子２０ａの少なくとも一部は、互いに接する。銀粒子２０ａの形状は球形である。銀粒子２０ａの平均粒径は、例えば、１ｎｍ以上１００ｎｍ以下である。
金領域２０ｂは、金（Ａｕ）を含む。金領域２０ｂは、複数の銀粒子２０ａの間に存在する。金領域２０ｂは、複数の銀粒子２０ａを被覆する。
ボイド２０ｃは、銀粒子２０ａで囲まれた空孔である。ボイド２０ｃの内壁は、金領域２０ｂで被覆される。金領域２０ｂは、ボイド２０ｃの内壁を被覆する。
接合層２０に含まれる金（Ａｕ）の、接合層２０に含まれる金（Ａｕ）と銀（Ａｇ）との総和に対する原子比（Ａｕ／（Ａｕ＋Ａｇ））は、例えば、０．５％以上２０％以下である。
次に、実施形態の半導体装置の製造方法の一例について説明する。
図４は、実施形態の半導体装置の製造方法を示す図である。図４は、ＭＯＳＦＥＴ１０の製造方法の一例を示す。
最初に、単結晶の炭化珪素ウェハＷを準備する（図４（ａ））。炭化珪素ウェハＷの厚さは、例えば、２００μｍ以上１０００μｍ以下である。
次に、炭化珪素ウェハＷの表面に、公知のプロセス技術を用いて、ソース領域、ゲート領域、上部電極１０ｂ等のＭＯＳＦＥＴの構成要素を形成する（図４（ｂ））。図４（ｂ）には、上部電極１０ｂのみを明示する。
次に、炭化珪素ウェハＷを裏面から研削により薄膜化する。炭化珪素ウェハＷを、例えば、３０μｍ以上３００μｍ以下に薄膜化する（図４（ｃ））。その後、例えば、ドライポリッシュ法や、化学機械研磨法（ＣＭＰ法）を用いて、炭化珪素ウェハＷの裏面を平坦化する。
次に、炭化珪素ウェハＷの裏面に、下部電極１０ｃを形成する（図４（ｄ））。下部電極１０ｃの形成の詳細は、後述する。
次に、炭化珪素ウェハＷを、例えば、ブレードダイシング法により分割し、複数のＭＯＳＦＥＴ１０が製造される（図４（ｅ））。
図５は、実施形態の半導体装置の製造方法を示す図である。図５は、下部電極１０ｃの形成の詳細を示す。
炭化珪素ウェハＷの裏面を平坦化した後、炭化珪素ウェハＷの裏面側に、ニッケルシリサイド層３０を形成する（図５（ａ））。ニッケルシリサイド層３０は、ニッケル膜のスパッタ法による堆積と、レーザーアニールを用いた熱処理による、ニッケル膜と炭化珪素のシリサイド化反応で形成する。ニッケルシリサイド層３０を設けることにより、半導体層１０と下部電極１０ｃとの間のコンタクトがオーミックコンタクトとなる。
次に、ニッケルシリサイド層３０の上に、チタン層３１を形成する。チタン層３１は、スパッタ法により形成する。チタン層３１は、ニッケルシリサイド層３０の表面の酸化を防ぐ。
次に、チタン層３１の上に、ニッケル層３２を形成する（図５（ｂ））。ニッケル層３２は、スパッタ法により形成する。ニッケル層３２は、下部電極１０ｃと絶縁基板１６との接合性を向上させる。また、金の拡散防止層として機能し、ニッケル層３２に若干金が拡散する可能性もある。その場合、ニッケル層３２の金の原子濃度は、例えば、接合層２０の金の原子濃度よりも低い。
次に、ニッケル層３２の上に、金層４０を形成する（図５（ｃ））。金層４０は、後に接合層２０へ拡散する金の供給源となる。
図６、図７及び図８は、実施形態の半導体装置の製造方法を示す図である。図６は、接合層５０の形成の詳細を示す。
絶縁基板１６の表面金属層１６ｂの表面に銀ナノペースト４２を塗布する（図６）。銀ナノペースト４２は、例えば、スクリーン印刷法により塗布する。
次に、銀ナノペースト４２と、金層４０が接触するように、絶縁基板１６とＭＯＳＦＥＴ１０を貼り合わせる（図７）。その後、絶縁基板１６とＭＯＳＦＥＴ１０を加圧しながら熱処理を行う。熱処理は、例えば、１５０℃以上３００℃以下である。
熱処理により、銀ナノペースト４２の溶媒が揮発するとともに、銀ナノ粒子が焼結されて、接合層２０が形成される（図８）。熱処理の際に、金層４０から供給される金原子が銀粒子２０ａの粒界を拡散し、銀粒子２０ａを被覆する金領域２０ｂが形成される。
金領域２０ｂは、例えば、接合層２０の全域に、ほぼ一様に形成される。接合層２０に金原子が、ほぼ一様に分散される。
接合層２０により、絶縁基板１６の上にＭＯＳＦＥＴ１０が固定された後は、公知の製造方法によりパワー半導体モジュール１００が製造される。
次に、実施形態の半導体装置の作用及び効果について説明する。
図９は、比較例の半導体装置の一部の拡大模式断面図である。比較例の半導体装置は、実施形態のパワー半導体モジュール１００と同様のパワー半導体モジュールである。
図９は、比較例の接合層９０を示す。接合層９０は、複数の銀粒子９０ａ、及び、ボイド９０ｃを含む。比較例の接合層９０は、金を含む領域を含まない点で、実施形態の接合層２０と異なる。
接合層９０の中にボイド９０ｃが含まれると、ボイド９０ｃの内壁が反応活性となる。このため、接合層９０の酸化や硫化が生じやすくなる。したがって、接合層９０の高抵抗化、脆化、及び、動作／非動作時の温度変化の繰り返しによる破断が生じやすくなる。よって、パワー半導体モジュールの信頼性が低下するおそれがある。
また、接合層９０の中で、銀粒子９０ａが接触した部分のみが電流経路として機能する。このため、電流密度が局所的に高くなり、エレクトロマイグレーションが発生しやすくなる。エレクトロマイグレーションにより、更にボイド９０ｃが拡大し、パワー半導体モジュールの信頼性が低下するおそれがある。
実施形態のパワー半導体モジュール１００は、接合層２０が、複数の銀粒子２０ａの間に存在する金領域２０ｂを含む。ボイド２０ｃの内壁は、金領域２０ｂで被覆される。このため、ボイド２０ｃの内壁の反応性が乏しくなり、接合層２０の酸化や硫化が生じにくくなる。したがって、接合層２０の高抵抗化、脆化、及び、動作／非動作時の温度変化の繰り返しによる破断は生じにくくなる。よって、パワー半導体モジュール１００の信頼性が向上する。
また、接合層２０の中で、銀粒子２０ａが接触した部分のみならず、金領域２０ｂも電流経路として機能する。このため、電流密度の局所的上昇が生じにくく、エレクトロマイグレーションの発生が抑制される。エレクトロマイグレーションによるボイド２０ｃの拡大は抑制され、パワー半導体モジュール１００の信頼性が向上する。
接合層２０の形成の熱処理の際の、金領域２０ｂの形成は、ＭＯＳＦＥＴ１０の裏面の下部電極１０ｃの形成プロセスに関連すると考えられる。すなわち、炭化珪素ウェハＷの裏面薄膜化の際に行われる平坦化や、ニッケルシリサイド層３０の形成を、レーザーアニールを用いて行うことにより、絶縁基板１６とＭＯＳＦＥＴ１０との接合前の金層４０の表面の平坦性が高く保たれると考えられる。平坦性が高く保たれることにより、金原子の接合層２０への拡散が一様に進み、接合層２０の全域に、ほぼ一様に金領域２０ｂが形成できると考えられる。また、接合層２０の反対側に、金原子が拡散しにくいニッケル層３２を設けることも、接合層２０側への金の拡散を促進していると考えられる。
接合層２０に含まれる金（Ａｕ）の、接合層２０に含まれる金（Ａｕ）と銀（Ａｇ）との総和に対する原子比（Ａｕ／（Ａｕ＋Ａｇ））は、０．５％以上２０％以下であることが好ましい。上記原子比が０．５％以上あることにより、パワー半導体モジュール１００の高い信頼性が実現できる。また、原子比が２０％以下であることにより、接合層２０の電気抵抗が低くなり、パワー半導体モジュール１００のオン抵抗が低減する。
以上、実施形態によれば、接合層２０に金領域２０ｂを含むことにより、接合層２０の劣化が抑制され、高い信頼性を有する半導体装置が実現できる。
実施形態では、ＭＯＳＦＥＴを用いる場合を例に説明したが、実装される半導体チップはＭＯＳＦＥＴに限定されるものではない。例えば、ＩＧＢＴ、ＳＢＤ（Ｓｃｈｏｔｔｋｙ Ｂａｒｒｉｅｒ Ｄｉｏｄｅ）、ＰＩＮダイオードなど、その他のトランジスタやダイオードを適用することも可能である。また、トランジスタとダイオードの組み合わせを適用することも可能である。
実施形態では、実装される半導体チップの数が２個の場合を例に説明したが、半導体チップは、１個であっても、３個以上であっても構わない。
実施形態では、半導体層に炭化珪素を用いる場合を例に説明したが、半導体層は、炭化珪素を用いる場合に限定されない。例えば、炭化珪素層に、シリコン等、その他の半導体材料を適用することも可能である。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。例えば、一実施形態の構成要素を他の実施形態の構成要素と置き換え又は変更してもよい。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１０ａ 半導体層
１６ｂ 表面金属層（金属層）
２０ 接合層
２０ａ 銀粒子
２０ｂ 金領域（領域）
２０ｃ ボイド
３０ ニッケルシリサイド層（第２の中間層）
３１ チタン層（第３の中間層）
３２ ニッケル層（第１の中間層）
１００ パワー半導体モジュール（半導体装置）

Claims (7)

  1. 半導体層と、
    金属層と、
    前記半導体層と前記金属層との間に設けられ、複数の銀粒子と、前記複数の銀粒子の間に存在する金を含む領域と、を含む接合層と、
    前記半導体層と前記接合層との間に設けられ、ニッケルを含む第１の中間層と、
    を備え、
    前記第１の中間層の金の原子濃度は、前記接合層の金の原子濃度よりも低い、半導体装置。
  2. 前記複数の銀粒子の少なくとも一部は互いに接する請求項１記載の半導体装置。
  3. 前記領域は、前記複数の銀粒子を被覆する請求項１又は請求項２記載の半導体装置。
  4. 前記接合層はボイドを含み、前記領域は前記ボイドの内壁を被覆する請求項１ないし請求項３いずれか一項記載の半導体装置。
  5. 前記半導体層と前記第１の中間層との間に設けられ、ニッケルシリサイドを含む第２の中間層を、更に備える請求項１ないし請求項４いずれか一項記載の半導体装置。
  6. 前記第１の中間層と前記第２の中間層との間に設けられ、チタンを含む第３の中間層を、更に備える請求項５記載の半導体装置。
  7. 前記複数の銀粒子の平均粒径は、１ｎｍ以上１００ｎｍ以下である請求項１ないし請求項６いずれか一項記載の半導体装置。
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