[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP7194921B2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
JP7194921B2
JP7194921B2 JP2019077868A JP2019077868A JP7194921B2 JP 7194921 B2 JP7194921 B2 JP 7194921B2 JP 2019077868 A JP2019077868 A JP 2019077868A JP 2019077868 A JP2019077868 A JP 2019077868A JP 7194921 B2 JP7194921 B2 JP 7194921B2
Authority
JP
Japan
Prior art keywords
resin
plating
semiconductor device
forming
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019077868A
Other languages
Japanese (ja)
Other versions
JP2020177977A (en
Inventor
清一 糸井
大輔 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Priority to JP2019077868A priority Critical patent/JP7194921B2/en
Priority to TW109105152A priority patent/TWI837307B/en
Priority to CN202010215487.0A priority patent/CN111834240A/en
Publication of JP2020177977A publication Critical patent/JP2020177977A/en
Application granted granted Critical
Publication of JP7194921B2 publication Critical patent/JP7194921B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

本開示は、半導体装置の製造方法に関し、特に可溶性樹脂を用いた半導体装置の製造方法に関する。 The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using soluble resin.

近年、電子部品や電子デバイスの小型化、高機能化、および多機能化が進んでおり、求められるニーズに対応していくために、半導体素子の高密度化や、電極端子の多ピン化および狭ピッチ化が図られている。 In recent years, electronic parts and devices have become smaller, more sophisticated, and more multifunctional. A narrower pitch is achieved.

多ピン化および狭ピッチ化された半導体素子を基板へ実装する方法の一つとして、フリップチップ実装が一般的に知られている。このフリップチップ実装では、半導体素子の電極パッド上に形成された突起電極と、基板の接続端子とが例えば加熱、加圧、超音波の印加などにより接合され、電気的に接続される。 Flip-chip mounting is generally known as one of the methods for mounting a semiconductor element with a large number of pins and a narrow pitch on a substrate. In this flip-chip mounting, protruding electrodes formed on electrode pads of a semiconductor element and connection terminals of a substrate are joined and electrically connected by, for example, heating, pressurization, or application of ultrasonic waves.

上記突起電極としては、例えば、ワイヤーボンディング法、電解・無電解メッキ、または転写法などによって形成されるはんだバンプが知られている。しかし、ワイヤーボンディング法では、狭ピッチ化に限界がある。また、電解・無電解メッキや転写法では、狭ピッチ化することにより、ブリッジ不良が発生し易くなる。ブリッジ不良とは、実装時の加圧工程および加熱工程で溶融した、隣接するはんだバンプ同士が繋がる現象である。 Solder bumps formed by, for example, a wire bonding method, an electrolytic/electroless plating method, a transfer method, or the like are known as the projecting electrodes. However, the wire bonding method has a limit in narrowing the pitch. Further, in electrolytic/electroless plating and transfer method, narrowing of the pitch tends to cause bridge defects. A bridging defect is a phenomenon in which adjacent solder bumps melted in the pressure process and the heating process during mounting are connected to each other.

狭ピッチ化に対するこれらの改善策として、例えば特許文献1には、フォトリソグラフィにより、断面形状が逆テーパー形状の開口部(空洞部と言ってもよい)をレジストに形成し、その開口部にメッキ処理を施すことにより、金属バンプを形成する方法が開示されている。 As an improvement measure for narrowing the pitch, for example, in Patent Document 1, an opening having an inversely tapered cross-sectional shape (which may be called a cavity) is formed in a resist by photolithography, and the opening is plated. A method of forming metal bumps by treatment is disclosed.

ここで、図5A~図5Cを用いて、特許文献1の半導体装置の製造方法の概略について説明する。図5A~図5Cは、特許文献1に記載の半導体装置の製造方法の説明に供する模式図である。図5A~図5Cは、半導体装置の断面を模式的に示している。 Here, the outline of the manufacturing method of the semiconductor device of Patent Document 1 will be described with reference to FIGS. 5A to 5C. 5A to 5C are schematic diagrams for explaining the manufacturing method of the semiconductor device described in Patent Document 1. FIG. 5A to 5C schematically show cross sections of the semiconductor device.

まず、図5Aに示すように、シリコーン基板11上に絶縁膜12、アルミパッド13および保護膜14を形成する。その後、例えばTi(チタン)、Pt(白金)、W(タングステン)、Pd(パラジウム)等を5000~8000Å蒸着して2~3層からなるバリアメタル15を形成する。 First, as shown in FIG. 5A, an insulating film 12, an aluminum pad 13 and a protective film 14 are formed on a silicon substrate 11. Then, as shown in FIG. After that, Ti (titanium), Pt (platinum), W (tungsten), Pd (palladium), etc. are vapor-deposited to a thickness of 5000 to 8000 Å to form a barrier metal 15 consisting of two to three layers.

次に、ネガタイプのレジスト17をバリアメタル15上に塗布する。レジスト17の膜厚は、例えば15~20μmである。そして、パターン形成時に露光時間を通常より長くして(換言すれば、オーバー露光して)、図5Bに示すように、断面形状が逆テーパー状である開口部をレジスト17に形成する。次に、レジスト17をマスクとして、開口部をAu(金)の電解メッキ液にて電解メッキする。これにより、図5Cに示すように、断面形状が順テーパー形状であるバンプ16が形成される。 Next, a negative type resist 17 is applied on the barrier metal 15 . The film thickness of the resist 17 is, for example, 15 to 20 μm. Then, during pattern formation, the exposure time is set longer than normal (in other words, overexposure) to form an opening having a reverse tapered cross section in the resist 17 as shown in FIG. 5B. Next, using the resist 17 as a mask, the opening is electrolytically plated with an Au (gold) electrolytic plating solution. Thereby, as shown in FIG. 5C, a bump 16 having a forward tapered cross-sectional shape is formed.

特開平4-217324号公報JP-A-4-217324

上述した特許文献1の方法を用いて大口径のウェハに突起電極を形成する場合、レジストの膜厚形成工程、露光工程、現像工程における面内均一性が重要となる。しかし、特に現像工程においては、面内均一性だけでなく再現性の確保が難しく、突起電極の形状をいかに安定して形成するかが課題となっている。 When forming protruded electrodes on a large-diameter wafer using the method of Patent Document 1 described above, in-plane uniformity is important in the process of forming the resist film thickness, the exposure process, and the development process. However, especially in the development process, it is difficult to ensure not only in-plane uniformity but also reproducibility.

また、実装時の応力を突起電極で吸収することが重要となるため、突起電極の形状を先鋭形状とすることが有利とされる。しかし、先鋭形状を実現するためには、レジストの開口部の形状は、逆テーパー形状にする必要があり、露光工程および現像工程における突起電極の形状の安定化がより大きな課題となっている。 In addition, since it is important for the projecting electrodes to absorb the stress during mounting, it is advantageous to form the projecting electrodes in a sharp shape. However, in order to achieve a sharp shape, the shape of the opening of the resist must be a reverse tapered shape, and the stabilization of the shape of the projecting electrode in the exposure process and the development process has become a more important issue.

本開示の一態様の目的は、安定した形状の突起電極を実現することができる半導体装置の製造方法を提供することである。 An object of one aspect of the present disclosure is to provide a method for manufacturing a semiconductor device that can realize a bump electrode with a stable shape.

本開示の一態様に係る半導体装置の製造方法は、複数の電極パッドを含む半導体素子の表面を硬化樹脂で被覆する樹脂形成工程と、前記電極パッド上に前記硬化樹脂の突起部を形成し、前記突起部を硬化させる突起形成工程と、メッキ液耐性樹脂により前記突起部を被覆する樹脂供給工程と、前記メッキ液耐性樹脂の一部を除去することにより、前記メッキ液耐性樹脂の表面上に前記突起部の一部を露出させる樹脂露出工程と、前記突起部に相当する前記硬化樹脂を除去することにより、前記メッキ液耐性樹脂に空洞部を形成する溶解工程と、前記空洞部にメッキを充填するメッキ工程と、前記メッキ液耐性樹脂を除去する樹脂除去工程と、を含む。 A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a resin forming step of coating a surface of a semiconductor element including a plurality of electrode pads with a cured resin, forming projections of the cured resin on the electrode pads, A projection forming step of curing the projection, a resin supply step of coating the projection with the plating solution resistant resin, and removing a part of the plating solution resistant resin to form a coating on the surface of the plating solution resistant resin. a resin exposing step of exposing a portion of the protrusion; a dissolving step of forming a cavity in the plating solution resistant resin by removing the cured resin corresponding to the protrusion; and plating the cavity. A filling plating step and a resin removing step of removing the plating solution resistant resin are included.

本開示によれば、安定した形状の突起電極を実現することができる。 According to the present disclosure, it is possible to realize a projection electrode with a stable shape.

本開示の実施の形態1に係る樹脂形成工程の説明に供する模式図Schematic diagram for explaining a resin forming step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係る突起形成工程の説明に供する模式図Schematic diagram for explaining a projection forming step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係る突起形成工程の説明に供する模式図Schematic diagram for explaining a projection forming step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係る突起形成工程の説明に供する模式図Schematic diagram for explaining a projection forming step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係る樹脂供給工程の説明に供する模式図Schematic diagram for explaining the resin supply process according to the first embodiment of the present disclosure 本開示の実施の形態1に係る樹脂露出工程の説明に供する模式図Schematic diagram for explaining a resin exposing step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係る溶解工程の説明に供する模式図Schematic diagram for explaining the dissolving step according to Embodiment 1 of the present disclosure 本開示の実施の形態1に係るメッキ工程の説明に供する模式図Schematic diagram for explaining the plating process according to the first embodiment of the present disclosure 本開示の実施の形態1に係る樹脂除去工程の説明に供する模式図Schematic diagram for explaining a resin removing step according to Embodiment 1 of the present disclosure 本開示の実施の形態2に係る残膜部除去工程の説明に供する模式図Schematic diagram for explaining the residual film removing step according to the second embodiment of the present disclosure 本開示の実施の形態2に係る残膜部除去工程の説明に供する模式図Schematic diagram for explaining the residual film removing step according to the second embodiment of the present disclosure 本開示の実施の形態4に係る突起電極の形状の一例を示す模式図Schematic diagram showing an example of the shape of a projecting electrode according to Embodiment 4 of the present disclosure 本開示の実施の形態4に係る突起電極の形状の一例を示す模式図Schematic diagram showing an example of the shape of a projecting electrode according to Embodiment 4 of the present disclosure 本開示の実施の形態4に係る突起電極の形状の一例を示す模式図Schematic diagram showing an example of the shape of a projecting electrode according to Embodiment 4 of the present disclosure 本開示の実施の形態4に係る突起電極の形状の一例を示す模式図Schematic diagram showing an example of the shape of a projecting electrode according to Embodiment 4 of the present disclosure 特許文献1の半導体装置の製造方法の説明に供する模式図Schematic diagram for explaining the manufacturing method of the semiconductor device of Patent Document 1 特許文献1の半導体装置の製造方法の説明に供する模式図Schematic diagram for explaining the manufacturing method of the semiconductor device of Patent Document 1 特許文献1の半導体装置の製造方法の説明に供する模式図Schematic diagram for explaining the manufacturing method of the semiconductor device of Patent Document 1

以下、本開示の各実施の形態について、図面を参照しながら説明する。なお、各図において共通する構成要素については同一の符号を付し、それらの説明は適宜省略する。 Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. In addition, the same code|symbol is attached|subjected about the component which is common in each figure, and those description is abbreviate|omitted suitably.

(実施の形態1)
本開示の実施の形態1に係る半導体装置の製造方法では、樹脂形成工程、突起形成工程、樹脂供給工程、樹脂露出工程、溶解工程、メッキ工程、樹脂除去工程がこの順で行われる。
(Embodiment 1)
In the method of manufacturing a semiconductor device according to the first embodiment of the present disclosure, a resin forming process, a protrusion forming process, a resin supplying process, a resin exposing process, a dissolving process, a plating process, and a resin removing process are performed in this order.

図1A~図1Iは、本実施の形態に係る半導体装置の製造方法を説明する図である。図1A~図1Iは、半導体装置の断面を模式的に示している。 1A to 1I are diagrams for explaining the method for manufacturing a semiconductor device according to this embodiment. 1A to 1I schematically show cross sections of semiconductor devices.

まず、図1Aを用いて、最初の工程である樹脂形成工程について説明する。 First, the resin forming process, which is the first process, will be described with reference to FIG. 1A.

図1Aに示すように、半導体素子1の表面には、複数の電極パッド2が形成されている。 As shown in FIG. 1A, a plurality of electrode pads 2 are formed on the surface of semiconductor element 1 .

樹脂形成工程では、まず、図1Aに示すように、電極パッド2を含む半導体素子1の表面全体を被覆するようにシード層3を形成する。 In the resin forming step, first, as shown in FIG. 1A, a seed layer 3 is formed so as to cover the entire surface of the semiconductor element 1 including the electrode pads 2 .

シード層3は、電解メッキを形成するための下地として使用される。シード層3の材質としては、例えば、Ni(ニッケル)、W(タングステン)、Cr(クロム)、Cu(銅)、Co(コバルト)、Ti(チタン)、Pd(パラジウム)などが用いられる。シード層3の厚み(図中の上下方向の長さ)は、例えば、0.01~1μmである。 The seed layer 3 is used as a base for forming electrolytic plating. Examples of materials for the seed layer 3 include Ni (nickel), W (tungsten), Cr (chromium), Cu (copper), Co (cobalt), Ti (titanium), and Pd (palladium). The thickness of the seed layer 3 (length in the vertical direction in the drawing) is, for example, 0.01 to 1 μm.

次に、図1Aに示すように、シード層3の表面全体を可溶性紫外線硬化樹脂4で被覆する。 Next, as shown in FIG. 1A, the entire surface of the seed layer 3 is covered with a soluble ultraviolet curable resin 4. Then, as shown in FIG.

このとき、可溶性紫外線硬化樹脂4(硬化樹脂の一例)は、例えばスピンコート、コーターなどにより、薄くかつ均一になるように設けられる。可溶性紫外線硬化樹脂4としては、例えば、アクリル系の紫外線硬化樹脂が挙げられる。可溶性紫外線硬化樹脂4の厚みは、例えば1~20μm程度であり、最終的に形成される突起電極7(図1I参照)の形状および高さに応じて設定される。また、可溶性紫外線硬化樹脂4の材料は、例えば、アルコール、または、アルコール以外の溶剤に可溶する紫外線硬化性樹脂である。 At this time, the soluble ultraviolet curable resin 4 (an example of a curable resin) is applied thinly and uniformly by, for example, spin coating or a coater. Examples of the soluble ultraviolet curable resin 4 include acrylic ultraviolet curable resins. The thickness of the soluble ultraviolet curable resin 4 is, for example, about 1 to 20 μm, and is set according to the shape and height of the projecting electrodes 7 (see FIG. 1I) to be finally formed. Also, the material of the soluble ultraviolet curable resin 4 is, for example, an ultraviolet curable resin soluble in alcohol or a solvent other than alcohol.

なお、本実施の形態では、紫外線の照射により硬化する可溶性紫外線硬化樹脂4を用いる場合を例に挙げて説明するが、紫外線の照射以外の方法により硬化する樹脂を用いてもよい。 In the present embodiment, the case of using the soluble ultraviolet curable resin 4 that is cured by irradiation with ultraviolet rays will be described as an example, but a resin that is cured by a method other than irradiation with ultraviolet rays may be used.

次に、図1B~図1Dを用いて、樹脂形成工程の次に行われる突起形成工程について説明する。 Next, with reference to FIGS. 1B to 1D, the process of forming projections that follows the process of forming resin will be described.

図1Bに示すように、インプリント型5(転写型の一例)は、各電極パッド2の位置に対応するように凹部5aが設けられている。凹部5aは、例えば、円錐状または角錐状である。 As shown in FIG. 1B, an imprint mold 5 (an example of a transfer mold) is provided with recesses 5a corresponding to the positions of the respective electrode pads 2. As shown in FIG. The recess 5a is, for example, conical or pyramidal.

突起形成工程では、まず、図1Bに示すように、各凹部5aと各電極パッド2との位置合わせを行う。 In the projection forming step, first, as shown in FIG. 1B, each concave portion 5a and each electrode pad 2 are aligned.

次に、図1Cに示すように、インプリント型5を可溶性紫外線硬化樹脂4に押し当てる(換言すれば、加圧する)。 Next, as shown in FIG. 1C, the imprint mold 5 is pressed (in other words, pressurized) against the soluble ultraviolet curable resin 4 .

次に、図1Cに示す状態において可溶性紫外線硬化樹脂4の表面に紫外線を照射することで、可溶性紫外線硬化樹脂4を硬化させる。図1Cの矢印Aは、紫外線の照射方向を示している。 Next, in the state shown in FIG. 1C, the soluble UV-curable resin 4 is cured by irradiating the surface of the soluble UV-curable resin 4 with UV rays. Arrow A in FIG. 1C indicates the irradiation direction of ultraviolet rays.

紫外線の照射後、半導体素子1からインプリント型5を離型する。 After the ultraviolet irradiation, the imprint mold 5 is released from the semiconductor element 1 .

インプリント型5の離型後、図1Dに示すように、凸型の可溶性紫外線硬化樹脂4、すなわち可溶性紫外線硬化樹脂4の突起部4a(以下、単に「突起部4a」という)が形成される。突起部4aの形状は、インプリント型5の凹部5aの形状と同じである。また、突起部4a以外の部分には、可溶性紫外線硬化樹脂4の残膜部4b(以下、単に「残膜部4b」という)が形成される。 After releasing the imprint mold 5, as shown in FIG. 1D, a convex soluble UV-curable resin 4, that is, a projection 4a of the soluble UV-curable resin 4 (hereinafter simply referred to as "projection 4a") is formed. . The shape of the protrusion 4 a is the same as the shape of the recess 5 a of the imprint mold 5 . A residual film portion 4b of the soluble ultraviolet curable resin 4 (hereinafter simply referred to as "remaining film portion 4b") is formed in a portion other than the protruding portion 4a.

なお、インプリント型5を可溶性紫外線硬化樹脂4に押し当てる前に、可溶性紫外線硬化樹脂4を加温してもよい。これにより、インプリント型5が押し当てられたときの可溶性紫外線硬化樹脂4の流動性が向上し、より安定した形状の突起部4aを形成することができる。さらに、真空中でインプリント型5を可溶性紫外線硬化樹脂4に当ててもよい。これにより、ボイドの巻き込みを抑制でき、パターン不良の発生を抑制できる。 Note that the soluble UV curable resin 4 may be heated before the imprint mold 5 is pressed against the soluble UV curable resin 4 . As a result, the fluidity of the soluble ultraviolet curable resin 4 is improved when the imprint mold 5 is pressed against it, and the protrusions 4a can be formed in a more stable shape. Furthermore, the imprint mold 5 may be applied to the soluble ultraviolet curable resin 4 in a vacuum. As a result, entrainment of voids can be suppressed, and occurrence of pattern defects can be suppressed.

また、インプリント型5を半導体素子1から離型する前に、可溶性紫外線硬化樹脂4を加温してもよい。これにより、離型時に可溶性紫外線硬化樹脂4がインプリント型5に付着することを抑制でき、離型性の向上を実現できる。 Further, the soluble ultraviolet curing resin 4 may be heated before the imprint mold 5 is released from the semiconductor element 1 . As a result, it is possible to prevent the soluble ultraviolet curable resin 4 from adhering to the imprint mold 5 at the time of mold release, and to improve mold releasability.

押し当て時および離型時に可溶性紫外線硬化樹脂4を加温する温度は、40~90度程度が好ましい。 The temperature at which the soluble ultraviolet curable resin 4 is heated during pressing and releasing is preferably about 40 to 90 degrees.

また、インプリント型5の材料としては、例えば、アクリル樹脂、シリコーン樹脂、ポリジメチルシロキサン(PDMS)、石英、またはガラスなどを用いることができる。なお、可溶性紫外線硬化樹脂4をインプリント型5により加圧転写させた状態(例えば、図1Cに示す状態)で紫外線硬化させる必要があるため、インプリント型5の材料としては、紫外線に対して50%以上の透過率を有する透明材料であることが好ましい。 As the material of the imprint mold 5, for example, acrylic resin, silicone resin, polydimethylsiloxane (PDMS), quartz, glass, or the like can be used. In addition, since it is necessary to UV-cure the soluble UV-curable resin 4 in a state where it is pressure-transferred by the imprint mold 5 (for example, the state shown in FIG. 1C), the material for the imprint mold 5 is A transparent material having a transmittance of 50% or more is preferred.

また、予めインプリント型5の表面に離型処理を施してもよい。これにより、離型時に可溶性紫外線硬化樹脂4がインプリント型5に付着することを抑制することができる。離型処理に用いられる材料としては、例えば、シリコーン、フッ素などの樹脂が好ましい。 Alternatively, the surface of the imprint mold 5 may be subjected to mold release treatment in advance. This can prevent the soluble ultraviolet curable resin 4 from adhering to the imprint mold 5 when the mold is released. Resins such as silicone and fluorine are preferable as the material used for the release treatment.

次に、図1Eを用いて、突起形成工程の次に行われる樹脂供給工程について説明する。 Next, with reference to FIG. 1E, the resin supplying process that follows the projection forming process will be described.

樹脂供給工程では、図1Eに示すように、突起部4aおよび残膜部4bをメッキ耐性樹脂6で被覆する。メッキ耐性樹脂6としては、例えば、レジストなどの材料であって、メッキ耐性を有する樹脂が挙げられる。 In the resin supply step, as shown in FIG. 1E, the projecting portion 4a and the residual film portion 4b are covered with a plating resistant resin 6. Then, as shown in FIG. As the plating-resistant resin 6, for example, a material such as a resist, which has plating resistance, can be used.

このとき、メッキ耐性樹脂6は、例えばスピンコート、コーターなどにより、薄くかつ均一になるように設けられる。メッキ耐性樹脂6の厚み(図中の上下方向の長さ)は、後述する樹脂露出工程における除去処理が短時間でできるように、例えば1~20μm程度であることが好ましい。 At this time, the plating resistant resin 6 is provided thinly and uniformly by, for example, spin coating or a coater. The thickness of the plating-resistant resin 6 (the length in the vertical direction in the figure) is preferably about 1 to 20 μm, for example, so that the removal process in the resin exposing process described later can be performed in a short time.

また、メッキ耐性樹脂6は、後述するメッキ工程においてメッキ液に浸漬されることになるため、メッキ液に耐性のあるレジストなどが用いられ、メッキ工程中においても形状を維持することができる。 In addition, since the plating resistant resin 6 will be immersed in the plating solution in the plating process, which will be described later, a resist resistant to the plating solution is used, and the shape can be maintained even during the plating process.

次に、図1Fを用いて、樹脂供給工程の次に行われる樹脂露出工程について説明する。 Next, with reference to FIG. 1F, the resin exposing step that follows the resin supplying step will be described.

樹脂露出工程では、図1Fに示すように、メッキ耐性樹脂6および各突起部4aの頂部を機械的方法または化学的方法により除去し、各突起部4aの水平断面(以下、露出面ともいう)をメッキ耐性樹脂6の表面上に露出させる。 In the resin exposing step, as shown in FIG. 1F, the plating resistant resin 6 and the top of each protrusion 4a are removed by a mechanical method or a chemical method, and a horizontal section (hereinafter also referred to as an exposed surface) of each protrusion 4a is exposed. is exposed on the surface of the plating resistant resin 6.

図1Fに示す突起部4aの厚み(図中の上下方向の長さ)は、後述するメッキ工程で形成される突起電極7(図1I参照)の高さに相当する。 The thickness of the protruding portion 4a shown in FIG. 1F (the length in the vertical direction in the figure) corresponds to the height of the protruding electrode 7 (see FIG. 1I) formed in the plating process described later.

また、突起部4aが円錐状である場合、その露出面は円形となる。その場合、その円形の径が少なくとも1μm程度であることが好ましい。また、突起部4aが角錐状である場合、その露出面が多角形となる。その場合、多角形の外接円の直径が少なくとも1μm程度であることが好ましい。径または外接円の直径を1μm程度とする理由は、後述するメッキ工程において溶媒などの液体を浸透させる必要があるためである。 Moreover, when the projection part 4a is conical, the exposed surface becomes circular. In that case, it is preferable that the circular diameter is at least about 1 μm. Moreover, when the projection part 4a is pyramid-shaped, the exposed surface becomes a polygon. In that case, it is preferable that the diameter of the circumscribed circle of the polygon is at least about 1 μm. The reason why the diameter or the diameter of the circumscribed circle is about 1 μm is that it is necessary to permeate a liquid such as a solvent in the plating process, which will be described later.

また、上記機械的方法としては、例えば、所定の器具を用いて樹脂を研削、研磨する方法が挙げられる。また、上記科学的方法としては、例えば、紫外線等の照射によりガスと樹脂とを化学反応させ、樹脂を剥離する光励起アッシング、または、ガスを高周波等でプラズマ化し、そのプラズマの照射により樹脂を剥離するプラズマアッシングなどが挙げられるが、これらに限定されない。 Moreover, examples of the mechanical method include a method of grinding and polishing the resin using a predetermined tool. In addition, as the above scientific method, for example, the gas and resin are chemically reacted by irradiation with ultraviolet rays, etc., and the resin is peeled off by photoexcited ashing, or the gas is converted to plasma with a high frequency or the like, and the resin is peeled off by irradiating the plasma. Examples include, but are not limited to, plasma ashing.

次に、図1Gを用いて、樹脂露出工程の次に行われる溶解工程について説明する。 Next, the dissolving process that follows the resin exposing process will be described with reference to FIG. 1G.

溶解工程では、図1Fに示した各突起部4aを溶解させ、除去する。これにより、図1Gに示すように、メッキ耐性樹脂6において各空洞部6aが形成される。 In the dissolving step, each protrusion 4a shown in FIG. 1F is dissolved and removed. Thereby, as shown in FIG. 1G, each cavity 6a is formed in the plating resistant resin 6. Next, as shown in FIG.

例えば、スピンナーやパドルなどを用いて、各突起部4aの露出面を溶媒に浸漬する。これにより、溶媒が各突起部4aの露出面から内部へ浸透し、各突起部4aは溶解され、最終的には完全に除去される。 For example, using a spinner or a paddle, the exposed surface of each protrusion 4a is immersed in the solvent. As a result, the solvent permeates into the inside from the exposed surface of each protrusion 4a, and each protrusion 4a is dissolved and finally completely removed.

電極パッド2上のシード層3の表面には、突起部4aおよびメッキ耐性樹脂6が設けられる(例えば図1F参照)が、突起部4aは溶媒によって溶解する特性を有し、メッキ耐性樹脂6は溶媒によって溶解しない特性を有する。よって、溶解工程では、図1Gに示したように、電極パッド2上のシード層3の表面に突起部4aの形状(例えば、円錐台状または角錐台状)と同じ形状の空洞部6aが形成される。 The surface of the seed layer 3 on the electrode pad 2 is provided with a protrusion 4a and a plating-resistant resin 6 (see, for example, FIG. 1F). It has the property of not being dissolved by solvents. Therefore, in the dissolution step, as shown in FIG. 1G, a hollow portion 6a having the same shape as the protrusion 4a (for example, a truncated cone shape or a truncated pyramid shape) is formed on the surface of the seed layer 3 on the electrode pad 2. be done.

次に、図1Hを用いて、溶解工程の次に行われるメッキ工程について説明する。 Next, the plating process that follows the dissolving process will be described with reference to FIG. 1H.

メッキ工程では、図1Gに示した空洞部6aにメッキ処理を施すことにより、図1Hに示すように突起電極7を形成する。突起電極7は、空洞部6aと同じ形状である。 In the plating step, the hollow portion 6a shown in FIG. 1G is plated to form the projecting electrodes 7 as shown in FIG. 1H. The projecting electrode 7 has the same shape as the cavity 6a.

メッキ処理としては、例えば電解メッキ法を用いることができる。具体的には、電解メッキ浴槽内に設けられた電極、および、シード層3を電源に接続した状態で、各空洞部6aを電解メッキ浴槽内に浸漬し、通電処理を行う。これにより、各空洞部6aにメッキ液が充填される。 As the plating treatment, for example, an electrolytic plating method can be used. Specifically, each cavity 6a is immersed in the electroplating bath while the electrodes provided in the electroplating bath and the seed layer 3 are connected to a power supply, and an energization process is performed. As a result, each cavity 6a is filled with the plating solution.

メッキ液としては、例えば、Cu(銅)やAu(金)などからなるボトムアップタイプのフィルメッキ液が好ましい。このようなメッキ液を用いることにより、各空洞部6aが微小である場合または複雑な形状である場合でも、各空洞部6aへのメッキ液の注入が容易になる。 As the plating solution, for example, a bottom-up type fill plating solution made of Cu (copper), Au (gold), or the like is preferable. By using such a plating solution, it is easy to inject the plating solution into each cavity 6a even if each cavity 6a is minute or has a complicated shape.

次に、図1Iを用いて、メッキ工程の次に行われる樹脂除去工程について説明する。 Next, with reference to FIG. 1I, the resin removal process that follows the plating process will be described.

樹脂除去工程では、図1Hに示したメッキ耐性樹脂6を除去する。これにより、図1Iに示すように、各突起電極7が露出した状態となる。 In the resin removing step, the plating resistant resin 6 shown in FIG. 1H is removed. As a result, as shown in FIG. 1I, each projecting electrode 7 is exposed.

メッキ耐性樹脂6を除去する方法としては、例えば、メッキ耐性樹脂6を剥離液に浸漬し、半導体素子1から剥離する方法や、各突起電極7をマスクで保護した上でドライエッチングによりメッキ耐性樹脂6を除去する方法などが挙げられる。 As a method of removing the plating resistant resin 6, for example, a method of immersing the plating resistant resin 6 in a stripping solution and peeling it off from the semiconductor element 1, or a method of protecting each projecting electrode 7 with a mask and then removing the plating resistant resin by dry etching. A method of removing 6 and the like can be mentioned.

以上説明したように、本実施の形態の半導体装置の製造方法によれば、インプリント型5の凹部5aの形状に基づいて突起電極7が形成される。よって、突起電極7について、大口径のウェハに対するフォトリソグラフィでは困難であった、突起電極7における任意の水平断面の面積や形状の安定化を容易に実現することができる。 As described above, according to the method for manufacturing a semiconductor device of the present embodiment, projecting electrode 7 is formed based on the shape of concave portion 5 a of imprint mold 5 . Therefore, it is possible to easily stabilize the area and shape of an arbitrary horizontal cross section of the protruded electrode 7, which has been difficult in photolithography for a large-diameter wafer.

(実施の形態2)
本開示の実施の形態2について説明する。
(Embodiment 2)
A second embodiment of the present disclosure will be described.

上述した突起形成工程の終了後では、図1Dに示したように、各突起部4a以外に、各電極パッド2の両側に残膜部4bが形成される。この残膜部4bは、上述した樹脂除去工程の後でも、図1Iに示したように残存する。 After the above-described projection forming step is completed, residual film portions 4b are formed on both sides of each electrode pad 2 in addition to each projection portion 4a, as shown in FIG. 1D. This residual film portion 4b remains as shown in FIG. 1I even after the resin removal step described above.

半導体装置の機能という点では、残膜部4bが残存しても問題はない。しかし、例えば、半導体装置がパッケージ化される際にアンダーフィルなどの樹脂との密着性が悪化し、信頼性が低下するという問題がある。また、例えば、半導体デバイスが中空構造を有する場合では、高温による熱処理や結露試験によって液滴が発生するという問題がある。 In terms of the function of the semiconductor device, there is no problem even if the residual film portion 4b remains. However, for example, when the semiconductor device is packaged, there is a problem that adhesion with resin such as underfill is deteriorated and reliability is lowered. Further, for example, in the case where the semiconductor device has a hollow structure, there is a problem that droplets are generated due to heat treatment at a high temperature or a dew condensation test.

このような問題を回避するため、本実施の形態では、上述した突起形成工程の次に、残膜部4bを除去する残膜部除去工程を行う。 In order to avoid such a problem, in the present embodiment, the residual film portion removing step of removing the residual film portion 4b is performed after the projection forming step described above.

残膜部除去工程では、図1Dに示した残膜部4bを例えばドライエッチングなどの方法により除去する。 In the remaining film portion removing step, the remaining film portion 4b shown in FIG. 1D is removed by a method such as dry etching.

これにより、図2に示すように、シード層3上には、電極パッド2の位置に対応した突起部4aのみが残存することとなり、次の工程が行われることになる。よって、最終工程である樹脂除去工程の後では、図3に示すように、シード層3上には突起電極7のみが形成されることになる。よって、上述した問題を解消することができる。 As a result, as shown in FIG. 2, only the protrusions 4a corresponding to the positions of the electrode pads 2 remain on the seed layer 3, and the next step is performed. Therefore, after the resin removing step, which is the final step, only the projecting electrodes 7 are formed on the seed layer 3 as shown in FIG. Therefore, the problem mentioned above can be eliminated.

(実施の形態3)
本開示の実施の形態3について説明する。
(Embodiment 3)
A third embodiment of the present disclosure will be described.

実施の形態2では、残膜部除去工程が突起形成工程の次に行われる場合を例に挙げて説明したが、残膜部除去工程は樹脂除去工程の次に行われてもよい。 In the second embodiment, the case where the residual film portion removing step is performed after the protrusion forming step has been described as an example, but the residual film portion removing step may be performed after the resin removing step.

例えば、図1Iに示した残膜部4bを例えばドライエッチングなどの方法により除去する。このとき、突起電極7が残膜部4bと一緒にエッチングされることを防止するためには、突起電極7の上部をマスクしてからエッチングを行うようにしてもよい。 For example, the remaining film portion 4b shown in FIG. 1I is removed by a method such as dry etching. At this time, in order to prevent the protruding electrode 7 from being etched together with the remaining film portion 4b, the upper portion of the protruding electrode 7 may be masked before etching.

これにより、図3に示すように、シード層3上には突起電極7のみが形成されることになる。よって、上述した実施の形態2で述べた問題を同様に解消することができる。 As a result, only the projecting electrodes 7 are formed on the seed layer 3, as shown in FIG. Therefore, the problem described in the second embodiment can be similarly resolved.

(実施の形態4)
本開示の実施の形態4について説明する。
(Embodiment 4)
A fourth embodiment of the present disclosure will be described.

実施の形態1では、円錐状または角錐状の凹部5a(図1B参照)を有するインプリント型5を用いることにより、円錐台状または角錐台状の突起電極7(図1I参照)が形成される場合を例に挙げて説明したが、突起電極7の形状は、これに限定されない。突起電極7の形状の各例を図4A~図7Dに示す。 In Embodiment 1, by using the imprint mold 5 having the conical or pyramidal concave portion 5a (see FIG. 1B), the truncated conical or pyramidal projection electrode 7 (see FIG. 1I) is formed. Although the case has been described as an example, the shape of the projecting electrode 7 is not limited to this. Examples of the shape of the projecting electrode 7 are shown in FIGS. 4A to 7D.

例えば、図4Aに示す突起電極7aは、2段構造である。突起電極7aの上段および下段は、それぞれ、円柱状または角柱状である。この突起電極7aを形成するためには、突起形成工程において、突起電極7aと同形状または略同形状の凹部を備えたインプリント型5を用いる。 For example, the projecting electrode 7a shown in FIG. 4A has a two-stage structure. The upper and lower stages of the projecting electrodes 7a are cylindrical or prismatic, respectively. In order to form the protruded electrodes 7a, an imprint mold 5 having recesses having the same shape or substantially the same shape as the protruded electrodes 7a is used in the process of forming the protruded electrodes.

例えば、図4Bに示す突起電極7bは、2段構造である。突起電極7bの上段は、円錐台状または角錐台状であり、突起電極7bの下段は、円柱状または角柱状である。この突起電極7bを形成するためには、突起形成工程において、突起電極7bと同形状または略同形状の凹部を備えたインプリント型5を用いる。 For example, the projecting electrode 7b shown in FIG. 4B has a two-stage structure. The upper stage of the projecting electrode 7b has a truncated cone shape or a truncated pyramid shape, and the lower stage of the projecting electrode 7b has a cylindrical or prismatic shape. In order to form the protruded electrodes 7b, an imprint mold 5 having recesses having the same shape or substantially the same shape as the protruded electrodes 7b is used in the process of forming the protruded electrodes.

例えば、図4Cに示す突起電極7cは、2段構造である。突起電極7cの上段および下段は、それぞれ、円錐台状または角錐台状である。この突起電極7cを形成するためには、突起形成工程において、突起電極7cと同形状または略同形状の凹部を備えたインプリント型5を用いる。 For example, the projecting electrode 7c shown in FIG. 4C has a two-stage structure. The upper and lower stages of the projecting electrode 7c are respectively shaped like a truncated cone or a truncated pyramid. In order to form the protruded electrodes 7c, an imprint mold 5 having recesses having the same shape or substantially the same shape as the protruded electrodes 7c is used in the process of forming the protruded electrodes.

例えば、図4Dに示す突起電極7dは、3段構造である。突起電極7dの上段、中段、および下段は、それぞれ、円錐台状または角錐台状である。この突起電極7dを形成するためには、突起形成工程において、突起電極7dと同形状または略同形状の凹部を備えたインプリント型5を用いる。 For example, a projecting electrode 7d shown in FIG. 4D has a three-step structure. The upper, middle, and lower portions of the protruding electrode 7d are each shaped like a truncated cone or a truncated pyramid. In order to form the protruding electrodes 7d, an imprint mold 5 having recesses having the same shape or substantially the same shape as the protruding electrodes 7d is used in the process of forming the protruding electrodes.

以上説明した突起電極7a~7dの形状は、例えば、電極パッド2の形状や半導体装置の実装時の応力吸収等を考慮して適宜選択されればよい。 The shape of the projecting electrodes 7a to 7d described above may be appropriately selected in consideration of, for example, the shape of the electrode pad 2 and stress absorption during mounting of the semiconductor device.

以上説明したように、本実施の形態では、形成したい突起電極の形状と同形状または略同形状の凹部を備えたインプリント型5を用いることにより、所望の形状の突起電極を安定的に形成することができる。よって、本実施の形態では、フォトリソグラフィにより突起電極を形成する場合に比べて、突起電極の形状の安定性および制限という点において有利である。 As described above, in the present embodiment, by using the imprint mold 5 having recesses having the same shape or substantially the same shape as the shape of the projected electrode to be formed, the desired shape of the projected electrode can be stably formed. can do. Therefore, the present embodiment is advantageous in terms of the stability and limitation of the shape of the protruded electrodes as compared with the case where the protruded electrodes are formed by photolithography.

なお、本開示は、上記各実施の形態の説明に限定されず、その趣旨を逸脱しない範囲において種々の変形が可能である。 It should be noted that the present disclosure is not limited to the description of each of the above embodiments, and various modifications are possible without departing from the scope of the present disclosure.

本開示の半導体装置の製造方法は、半導体素子上に複数の突起電極を安定的に形成することができ、小型化、多ピン化、狭ピッチ化等が進む半導体装置の製造に有用である。 The method of manufacturing a semiconductor device according to the present disclosure can stably form a plurality of projecting electrodes on a semiconductor element, and is useful for manufacturing semiconductor devices that are becoming smaller, have more pins, and have narrower pitches.

1 半導体素子
2 電極パッド
3 シード層
4 可溶性紫外線硬化樹脂
4a 突起部
4b 残膜部
5 インプリント型
5a 凹部
6 メッキ耐性樹脂
6a 空洞部
7、7a、7b、7c、7d 突起電極
11 シリコーン基板
12 絶縁膜
13 アルミパッド
14 保護膜
15 バリアメタル
16 バンプ
17 レジスト
REFERENCE SIGNS LIST 1 semiconductor element 2 electrode pad 3 seed layer 4 soluble ultraviolet curing resin 4a projection 4b residual film portion 5 imprint mold 5a recess 6 plating resistant resin 6a cavity 7, 7a, 7b, 7c, 7d projection electrode 11 silicone substrate 12 insulation Film 13 Aluminum pad 14 Protective film 15 Barrier metal 16 Bump 17 Resist

Claims (5)

複数の電極パッドを含む半導体素子の表面を硬化樹脂で被覆する樹脂形成工程と、
前記電極パッド上に前記硬化樹脂の突起部を形成し、前記突起部を硬化させる突起形成工程と、
メッキ液耐性樹脂により前記突起部を被覆する樹脂供給工程と、
前記メッキ液耐性樹脂の一部を除去することにより、前記メッキ液耐性樹脂の表面上に前記突起部の一部を露出させる樹脂露出工程と、
前記突起部に相当する前記硬化樹脂を除去することにより、前記メッキ液耐性樹脂に空洞部を形成する溶解工程と、
前記空洞部にメッキを充填するメッキ工程と、
前記メッキ液耐性樹脂を除去する樹脂除去工程と、を含む、
半導体装置の製造方法。
a resin forming step of coating a surface of a semiconductor element including a plurality of electrode pads with a cured resin;
a projection forming step of forming projections of the cured resin on the electrode pads and curing the projections;
a resin supply step of coating the protrusion with a plating solution resistant resin;
a resin exposing step of exposing a portion of the protrusion on the surface of the plating solution resistant resin by removing a portion of the plating solution resistant resin;
a dissolving step of forming a hollow portion in the plating solution resistant resin by removing the cured resin corresponding to the protrusion;
a plating step of filling the cavity with plating;
and a resin removal step of removing the plating solution resistant resin.
A method of manufacturing a semiconductor device.
前記突起形成工程では、
前記突起部に対応した形状を有する転写型を前記硬化樹脂に加圧することにより、前記突起部を形成する、
請求項1に記載の半導体装置の製造方法。
In the projection forming step,
forming the projection by pressing a transfer mold having a shape corresponding to the projection onto the cured resin;
2. The method of manufacturing a semiconductor device according to claim 1.
前記突起形成工程では、
前記硬化樹脂を加温した後で、前記突起部を形成する、
請求項1または2に記載の半導体装置の製造方法。
In the projection forming step,
forming the protrusion after heating the cured resin;
3. The method of manufacturing a semiconductor device according to claim 1.
前記突起部以外の部分である前記硬化樹脂の残膜部を除去する残膜部除去工程をさらに含む、
請求項1から3のいずれか1項に記載の半導体装置の製造方法。
Further comprising a residual film portion removing step of removing a residual film portion of the cured resin, which is a portion other than the protrusion,
4. The method of manufacturing a semiconductor device according to claim 1.
前記残膜部除去工程は、
前記突起形成工程の後または前記樹脂除去工程の後に行われる、
請求項4に記載の半導体装置の製造方法。
The residual film removing step includes:
performed after the protrusion forming step or after the resin removing step,
5. The method of manufacturing a semiconductor device according to claim 4.
JP2019077868A 2019-04-16 2019-04-16 Semiconductor device manufacturing method Active JP7194921B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2019077868A JP7194921B2 (en) 2019-04-16 2019-04-16 Semiconductor device manufacturing method
TW109105152A TWI837307B (en) 2019-04-16 2020-02-18 Semiconductor device and manufacturing method thereof
CN202010215487.0A CN111834240A (en) 2019-04-16 2020-03-24 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019077868A JP7194921B2 (en) 2019-04-16 2019-04-16 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
JP2020177977A JP2020177977A (en) 2020-10-29
JP7194921B2 true JP7194921B2 (en) 2022-12-23

Family

ID=72913921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019077868A Active JP7194921B2 (en) 2019-04-16 2019-04-16 Semiconductor device manufacturing method

Country Status (3)

Country Link
JP (1) JP7194921B2 (en)
CN (1) CN111834240A (en)
TW (1) TWI837307B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4234507A4 (en) 2020-10-23 2024-04-03 Sumitomo Electric Industries, Ltd. Multicore optical fiber

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3163823B2 (en) 1993-02-25 2001-05-08 松下電器産業株式会社 Semiconductor device and method of manufacturing the same
JP4217324B2 (en) 1999-01-08 2009-01-28 出光興産株式会社 Gas oil desulfurization method and gas oil desulfurization system
JP2009272383A (en) 2008-05-01 2009-11-19 Fujitsu Ltd Semiconductor device and bonding method of substrate
JP2009291920A (en) 2008-06-09 2009-12-17 Canon Inc Manufacturing method of three-dimensional structure
JP2013149884A (en) 2012-01-23 2013-08-01 Dainippon Printing Co Ltd Method for manufacturing pattern structure, nanoimprint lithography method, and imprint device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03163823A (en) * 1989-11-21 1991-07-15 Nec Corp Forming method of metal electrode pattern
JPH04217324A (en) * 1990-12-19 1992-08-07 Matsushita Electron Corp Manufacture of semiconductor device
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
JP2011067950A (en) * 2008-01-25 2011-04-07 Kyowa Hakko Chemical Co Ltd Method of forming metallic film pattern
KR20120045005A (en) * 2009-07-02 2012-05-08 플립칩 인터내셔날, 엘.엘.씨 Methods and structures for a vertical pillar interconnect
US8653658B2 (en) * 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
US9520375B2 (en) * 2015-04-30 2016-12-13 International Business Machines Corporation Method of forming a solder bump on a substrate
JP6550275B2 (en) * 2015-06-15 2019-07-24 東京応化工業株式会社 Composition for nanoimprinting, cured product, pattern forming method and article comprising pattern
US10115692B2 (en) * 2016-09-14 2018-10-30 International Business Machines Corporation Method of forming solder bumps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3163823B2 (en) 1993-02-25 2001-05-08 松下電器産業株式会社 Semiconductor device and method of manufacturing the same
JP4217324B2 (en) 1999-01-08 2009-01-28 出光興産株式会社 Gas oil desulfurization method and gas oil desulfurization system
JP2009272383A (en) 2008-05-01 2009-11-19 Fujitsu Ltd Semiconductor device and bonding method of substrate
JP2009291920A (en) 2008-06-09 2009-12-17 Canon Inc Manufacturing method of three-dimensional structure
JP2013149884A (en) 2012-01-23 2013-08-01 Dainippon Printing Co Ltd Method for manufacturing pattern structure, nanoimprint lithography method, and imprint device

Also Published As

Publication number Publication date
TWI837307B (en) 2024-04-01
JP2020177977A (en) 2020-10-29
TW202040704A (en) 2020-11-01
CN111834240A (en) 2020-10-27

Similar Documents

Publication Publication Date Title
JP5599276B2 (en) Semiconductor element, semiconductor element mounting body, and method of manufacturing semiconductor element
EP1777194A2 (en) Method for forming microelectronic spring structures on a substrate
KR20240023575A (en) Method of manufacturing semiconductor device
JP7573220B2 (en) Semiconductor device and method for manufacturing the same
JP7194921B2 (en) Semiconductor device manufacturing method
JP2001332658A (en) Semiconductor integrated circuit device and manufacturing method therefor
JP2013535093A (en) Method for manufacturing a chip stack and carrier for carrying out the method
JP2024009340A (en) Manufacturing method of semiconductor device and manufacturing equipment
JP2017228765A (en) Wiring board formation substrate and method of manufacturing the same, wiring board and method of manufacturing the same, and method of manufacturing semiconductor device
JP3423239B2 (en) Bump electrode formation method
JP2019197780A (en) Manufacturing method of semiconductor device, manufacturing device of semiconductor device, and semiconductor device
JP2002252258A (en) Method for manufacturing contact component and multi- layer interconnection substrate, and wafer batch- contact board
KR20060108104A (en) Method for manufacturing printed circuit board using imprinting process
JP3698223B2 (en) Manufacturing method of semiconductor device
JP2546351B2 (en) Semiconductor integrated circuit mounting method
WO2024116844A1 (en) Semiconductor device, and manufacturing method for same
KR20230042560A (en) Method for manufacturing semiconductor device and semiconductor device
JP2009059771A (en) Wafer level chip-size package and manufacturing method thereof
JPH08222840A (en) Circuit board with electrode pad and its manufacture
JP2024082302A (en) Bump formation method and bump
JP4461628B2 (en) Manufacturing method of semiconductor package
KR20090112026A (en) Method of forming a template and method of wafer level bumping using the same
JP2007116051A (en) Manufacturing method for semiconductor fabrication apparatus
JP2002202613A (en) Method of manufacturing substrate
JP2004336072A (en) Manufacturing method for flexible substrate

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20190625

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20191021

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211209

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20221128

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20221129

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221202

R151 Written notification of patent or utility model registration

Ref document number: 7194921

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151