JP5955124B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board for mounting a semiconductor element.

  Conventionally, a wiring board having a multilayer structure formed by a build-up method is used as a wiring board for mounting a semiconductor element. Conventional examples of such wiring boards are shown in FIGS. As shown in FIG. 4, the conventional wiring substrate 200 is formed by laminating buildup portions 32 on the upper and lower surfaces of the core substrate 31. The wiring board 200 is a rectangular flat plate having a length of about several tens of mm on one side and a thickness of about 250 to 1500 μm.

  The core substrate 31 includes a core insulating plate 34 having a plurality of through holes 33, and core wiring conductors 35 deposited in the through holes 33 and on the upper and lower surfaces of the core insulating plate 34. The core insulating plate 34 is formed of a fiber reinforced resin plate in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin. The thickness of the core insulating plate 34 is about 200 to 800 μm. The diameter of the through hole 33 is about 100 to 200 μm. The core wiring conductor 35 is made of copper foil or copper plating. The thickness of the core wiring conductor 35 is about 10 to 30 μm.

  The build-up unit 32 alternately includes build-up insulating layers 37 having a plurality of via holes 36 and build-up wiring conductors 38 deposited in the via holes 36 and on the surface of the build-up insulating layer 37 on the upper and lower surfaces of the core substrate 31. It is formed by laminating a plurality of layers. The buildup insulating layer 37 is formed of a filler-containing resin layer in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. The thickness of the buildup insulating layer 37 is about 25 to 50 μm. The diameter of the via hole 36 is about 50 to 100 μm. The build-up wiring conductor 38 is made of copper plating. The build-up wiring conductor 38 has a thickness of about 10 to 30 μm.

  A solder resist layer 39 for protecting the outermost buildup wiring conductor 38 is deposited on the surface of the upper and lower buildup portions 32. The solder resist layer 39 is made of a thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 39 is about 20 to 50 μm.

  A mounting portion 32A on which the semiconductor element S is mounted is formed at the center of the upper surface of the buildup portion 32 on the upper surface side. The mounting portion 32A is a rectangular region having a size corresponding to the semiconductor element S. In general, each side of the mounting portion 32 </ b> A is parallel to the outer periphery of the wiring board 200. On the mounting portion 32A, a plurality of semiconductor element connection pads 40 made up of the uppermost layer buildup wiring conductor 38 on the upper surface side are formed. The diameter of the semiconductor element connection pad 40 is about 50 to 150 μm. Several hundred to several thousand semiconductor element connection pads 40 are arranged in a lattice pattern. The arrangement of the semiconductor element connection pads 40 has lattice points parallel to each side of the square forming the mounting portion 32A at a pitch P1 of about 100 to 300 μm.

  A plurality of external connection pads 41 composed of a buildup wiring conductor 38 on the outermost layer on the lower layer side are formed on the lower surface of the buildup portion 32 on the lower surface side. The diameter of the external connection pad 41 is about 250 to 1000 μm. Several hundred to several thousand external connection pads 41 are arranged in a lattice pattern. The arrangement of the external connection pads 41 has lattice points parallel to the outer periphery of the wiring board 200 at a pitch P2 of about 500 to 2000 μm. Each semiconductor element connection pad 40 and the external connection pad 41 are electrically connected to each other via the build-up wiring conductor 38 and the core wiring conductor 35.

  By the way, in general, the current semiconductor elements have been noticeably increased in speed and capacity. Accordingly, a wiring board on which a semiconductor element is mounted is required to have a form with less electrical loss in high frequency transmission. For this reason, in particular, in a wiring board having a transmission path for transmitting a high-frequency signal, an increase in the number of transmission lines using a differential line as a transmission path for the high-frequency signal. In the differential line, two transmission lines are arranged adjacent to each other with a predetermined interval therebetween, and a transmission loss in high-frequency transmission is reduced by transmitting signals having opposite phases to the transmission lines. .

  Such a differential line will be described with reference to FIGS. FIG. 5 is a top view of the wiring board 200 shown in FIG. 4 and mainly shows two sets of differential lines. In FIG. 5, the outer shape of the wiring board 200 and the semiconductor element connection pads 40 are indicated by solid lines, and the wiring conductor 38 and the core wiring conductor 35 constituting the differential line are indicated by broken lines inside and under the wiring board 200. Yes. Further, the semiconductor element mounting portion 32A is indicated by a two-dot chain line. FIG. 6 is a perspective view showing only the differential line shown in FIG.

  As shown in FIGS. 5 and 6, the semiconductor element connection pad 40 has a pair 40A and 40B for differential lines. The semiconductor element connection pad pairs 40A and 40B are arranged adjacent to each other in a direction parallel to one side of the mounting portion 32A. The external connection pad 41 has pairs 41A and 41B corresponding to the semiconductor element connection pad pairs 40A and 40B. These pairs 41A and 41B are arranged adjacent to each other. The pair of semiconductor element connection pads 40A and 40B and the pair of external connection pads 41A and 41B correspond to the pair of strip-like wiring conductors 42A and 42A provided on the buildup wiring conductor 38 on the upper surface side. They are electrically connected to each other via 42B.

  The strip-like wiring conductor pairs 42A and 42B extend from below the corresponding semiconductor element connection pad pair 40A and 40B to above the external connection pad pair 41A and 41B, respectively. The pair of semiconductor element connection pads 40A and 40B and the pair of strip-shaped wiring conductors 42A and 42B are connected to each other via the buildup wiring conductor 38 on the upper surface side below the pair of semiconductor element connection pads 40A and 40B. . Also, the external connection pad pair 41A, 41B and the strip-like wiring conductor pair 42A, 42B are the upper-side build-up wiring conductor 38, the core wiring conductor 35, and the lower-surface side above the external connection pad pair 41A, 41B. They are electrically connected via a build-up wiring conductor 38. In this case, the through-hole pairs 33A and 33B for connecting the external connection pad pairs 41A and 41B and the strip-like wiring conductors 42A and 42B are disposed above the external connection pad pairs 41A and 41B. The pitch P3 of the through-hole pairs 33A and 33B is larger than the pitch P1 of the semiconductor element connection pads 40. As a result, the capacitance component in the through-hole pair 33A, 33B is reduced, and the reduction in characteristic impedance in the through-hole pair 33A, 33B is mitigated.

  By the way, in the wiring board 200 described above, the strip-shaped wiring conductor pairs 42A and 42B are provided only in the upper-side build-up portion 32. However, only the necessary number of strip-shaped wiring conductors are formed in the upper-side build-up portion 32. In some cases, such as when a pair cannot be provided, it may be necessary to provide a pair of strip-shaped wiring conductors also on the build-up portion 32 on the lower surface side. In such a case, as shown in FIGS. 7 and 8, in the buildup portion 32 on the lower surface side, the semiconductor element connection pad pair 40C and 40D extends from near the lower part to the upper part of the external connection pad 41C and 41D pair. The band-shaped wiring conductor pairs 42C and 42D are arranged, and the semiconductor element connection pad pair 40C and 40D and the band-shaped wiring conductor pair 42C and 42D are built up on the upper surface side in the vicinity below the semiconductor element connection pads 40C and 40D. The wiring conductor 38, the core wiring conductor 35, and the lower-side build-up wiring conductor 38 are connected, and the external connection pad pair 41C, 41D and the strip-shaped wiring conductor pair 42C, 42D are connected to the external connection pad pair 41C, 41D. It is necessary to connect via a build-up wiring conductor 38 on the lower surface side above. At this time, the through-hole pairs 33C and 33D for connecting the semiconductor element connection pad pairs 40C and 40D and the strip-like wiring conductor pairs 42C and 42D are disposed near the lower side of the semiconductor element connection pad pairs 40C and 40D. Is done.

  However, when the semiconductor element connection pad pair 40C and 40D and the corresponding through-hole pair 33C and 33D are arranged in a direction parallel to one side of the mounting portion 32A traversed by the strip-like wiring conductor pair 42C and 42D, It is necessary to widen the distance between the end portions on the mounting portion 32A side of the pair of strip-shaped wiring conductors 42C and 42D in a direction parallel to one side of the mounting portion 32A crossed by the pair of strip-shaped wiring conductors 42C and 42D. Therefore, there is less room for another wiring conductor to pass between the pair of strip-shaped wiring conductors 42C and 42D. Further, the adjacent pitch P3 in each of the through-hole pairs 33C and 33D cannot be secured sufficiently large in the first direction, and the deterioration of the characteristic impedance in the through-hole pair 33C and 33D is sufficiently suppressed. The problem of not being able to occur.

JP 2010-258390 A

  An object of the present invention is that there is a large room for passing other wiring conductors between a pair of strip-shaped wiring conductors connected to a pair of semiconductor element connection pads via a pair of through holes, and to a pair of semiconductor element connection pads. It is possible to secure a sufficient adjacent pitch in the connected through-hole pair to suppress a decrease in characteristic impedance in the through-hole pair, thereby enabling high-density wiring capable of transmitting a high-frequency signal with low loss. It is to provide a wiring board.

The wiring board according to the present invention includes a core substrate in which a core wiring conductor is deposited in the through hole of the core insulating plate having a plurality of through holes and upper and lower surfaces, and a plurality of via holes on the upper and lower surfaces of the core substrate. And a build-up portion formed by alternately laminating a plurality of build-up wiring conductors deposited on the surface of the build-up insulation layer including the inside of the via hole, and the build-up portion on the upper surface side. And a plurality of semiconductor element connection pads made of the build-up wiring conductor have first lattice points parallel to each side of the square. A plurality of external connections made of the build-up wiring conductor in a region including the outer peripheral portion of the lower surface of the build-up portion on the lower surface side. The pads are formed in an array having lattice points having a second pitch larger than the first pitch, and the semiconductor element connection pads are adjacent to each other in a first direction parallel to one side of the square. A pair of semiconductor element connection pads arranged side by side and a core wiring conductor in a pair of through-holes arranged adjacent to each other below the mounting portion are connected via the build-up wiring conductor on the upper surface side. A core wiring conductor in a pair of through holes and a pair of external connection pads arranged adjacent to each other on the outer peripheral portion are crossed over the one side in the build-up portion on the lower surface side, and the external connection is made from below the mounting portion. A wiring board having a differential line connected through a pair of strip-like wiring conductors that are formed of the build-up wiring conductors extending above a pair of pads, The pair is characterized in that arranged at the second said in the direction of the first pitch is greater than the third pitch that is perpendicular to the first direction.

According to the wiring board of the present invention, through-holes connected to the pair of semiconductor element connection pads arranged adjacent to each other at a first pitch in a first direction parallel to one side of the mounting portion are connected below the mounting portion. Since the pairs are arranged in a second direction orthogonal to the first direction, even if a plurality of pairs of semiconductor element connection pads are arranged in the first direction, the strip-like wiring connected to the pair of through holes There is no need to expand the pair of conductors in the first direction below the mounting portion. As a result, it is possible to leave a large room for passing other wiring conductors between the pair of strip-shaped wiring conductors. Also,
By expanding the adjacent interval in the pair of through holes in the second direction, it is possible to secure a sufficient adjacent interval and suppress a decrease in characteristic impedance in the pair of through holes. As a result, it is possible to provide a high-density wiring board capable of transmitting a high-frequency signal with low loss.

FIG. 1 is a schematic sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a perspective top view of an essential part showing an example of an embodiment of the wiring board of the present invention. FIG. 3 is a perspective view of a main part showing an example of an embodiment of the wiring board of the present invention. FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. FIG. 5 is a perspective top view of a main part showing a conventional wiring board. FIG. 6 is a perspective view showing a main part of a conventional wiring board. FIG. 7 is a perspective top view of a main part showing a conventional wiring board. FIG. 8 is a main part perspective view showing a conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a wiring board 100 of the present invention. As shown in FIG. 1, a wiring board 100 of the present invention is formed by laminating buildup portions 2 on the upper and lower surfaces of a core substrate 1. The wiring board 100 is a rectangular flat plate having a length of about several tens of mm on one side and a thickness of about 250 to 1500 μm.

  The core substrate 1 includes a core insulating plate 4 having a plurality of through holes 3, and core wiring conductors 5 attached to the through holes 3 and the upper and lower surfaces of the core insulating plate 4. The core insulating plate 4 is formed of a fiber reinforced resin plate in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin. The thickness of the core insulating plate 4 is about 200 to 800 μm. The diameter of the through hole 3 is about 100 to 200 μm. The core wiring conductor 5 is made of copper foil or copper plating. The thickness of the core wiring conductor 5 is about 10 to 30 μm. In the following description, the through-hole 3 means one including the core wiring conductor 5 deposited inside.

  The build-up unit 2 has a build-up insulating layer 7 having a plurality of via holes 6 and build-up wiring conductors 8 deposited in the via holes 6 and on the surface of the build-up insulating layer 7 alternately on the upper and lower surfaces of the core substrate 1. It is formed by laminating a plurality of layers. The build-up insulating layer 7 is formed of a filler-containing resin layer in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. The build-up insulating layer 7 has a thickness of about 25 to 50 μm. The diameter of the via hole 6 is about 50 to 100 μm. The build-up wiring conductor 8 is made of copper plating. The thickness of the buildup wiring conductor 8 is about 10 to 30 μm.

  A solder resist layer 9 for protecting the outermost buildup wiring conductor 8 is deposited on the surface of the upper and lower buildup portions 2. The solder resist layer 9 is made of a thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 9 is about 20 to 50 μm.

  A mounting portion 2A on which the semiconductor element S is mounted is formed at the center of the upper surface of the buildup portion 2 on the upper surface side. The mounting portion 2A is a square region having a size corresponding to the semiconductor element S. In general, each side of the mounting portion 2 </ b> A is parallel to the outer periphery of the wiring board 100. In the mounting portion 2A, a plurality of semiconductor element connection pads 10 composed of the uppermost layer buildup wiring conductor 8 on the upper surface side are formed. The diameter of the semiconductor element connection pad 10 is about 50 to 150 μm. Only a small number of semiconductor element connection pads 10 are shown for the convenience of drawing, but actually hundreds to thousands are arranged in a lattice pattern. The array of the semiconductor element connection pads 10 has lattice points parallel to each side of the square forming the mounting portion 2A at a pitch P1 of about 100 to 300 μm.

  A plurality of external connection pads 11 made of the outermost layer buildup wiring conductor 8 on the lower layer side are formed on the lower surface of the buildup portion 2 on the lower surface side. The diameter of the external connection pad 11 is about 250 to 1000 μm. Only a small number of external connection pads 11 are shown for the convenience of drawing, but actually hundreds to thousands are arranged in a grid. The arrangement of the external connection pads 11 has lattice points parallel to the outer periphery of the wiring board 100 at a pitch P2 of about 500 to 2000 μm. Each semiconductor element connection pad 10 and the external connection pad 11 are electrically connected to each other via the build-up wiring conductor 8 and the core wiring conductor 5.

  Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 10 via a solder bump, and the external connection pad 11 is connected to a wiring conductor of the external electric circuit board via a solder ball, whereby the mounting portion 2A is connected. The semiconductor element S to be mounted and the external electric circuit board are electrically connected.

  By the way, the wiring board 100 includes a differential line as a transmission path for high-frequency signals. In the differential line, two transmission lines are arranged adjacent to each other with a predetermined interval therebetween, and a transmission loss in high-frequency transmission is reduced by transmitting signals having opposite phases to the transmission lines. .

  Here, the example of the differential line in the wiring board 100 of this invention is demonstrated based on FIG. 2 and FIG. FIG. 2 is a top view of the wiring board 100 shown in FIG. 1, and mainly shows two sets of differential lines. In FIG. 2, the outline of the wiring board 100 and the semiconductor element connection pads 10 are indicated by solid lines, and the build-up wiring conductor 8 and the through hole 3 constituting the differential line are indicated by broken lines inside and under the wiring board 100. ing. The semiconductor element mounting portion 2A is indicated by a two-dot chain line. FIG. 3 is a perspective view showing only the differential line shown in FIG. In FIGS. 2 and 3, two sets of differential lines are shown as representatives, but a larger number of sets of differential lines are actually arranged.

  As shown in FIGS. 2 and 3, the semiconductor element connection pad 10 has a pair 10A and 10B for differential lines. The semiconductor element connection pad pairs 10A and 10B are arranged adjacent to each other in a first direction parallel to one side of the mounting portion 2A. The external connection pads 11 have external connection pad pairs 11A and 11B corresponding to the semiconductor element connection pad pairs 10A and 10B. These external connection pad pairs 11 </ b> A and 11 </ b> B are arranged adjacent to each other on the outer periphery of the lower surface of the wiring board 100. The semiconductor element connection pad pairs 10A and 10B and the external connection pad pairs 11A and 11B correspond to the strip-like wiring conductor pairs 12A and 12A provided on the buildup wiring conductor 8 on the lower surface side, respectively. They are electrically connected to each other via 12B.

  Through-hole pairs 3A and 3B are arranged below the mounting portion 2A at positions close to the semiconductor element connection pad pairs 10A and 10B. These through-hole pairs 3A and 3B are arranged at a pitch P3 in a direction orthogonal to the direction in which the semiconductor element connection pad pairs 10A and 10B are arranged. The semiconductor element connection pad pairs 10A and 10B are electrically connected to the corresponding through-hole pairs 3A and 3B via the build-up wiring conductor 8 on the upper surface side. In this case, even if the semiconductor element connection pad pairs 10A and 10B are arranged close to each other, the through-hole pairs 3A and 3B are orthogonal to the direction in which the semiconductor element connection pad pairs 10A and 10B are arranged. Since they are arranged in the direction, the pitch P3 in the through-hole pairs 3A, 3B can be expanded in a direction orthogonal to the direction in which the semiconductor element connection pad pairs 10A, 10B are arranged. Thereby, in each of the through-hole pairs 3A and 3B, a sufficient adjacent interval can be ensured between the through-holes 3 to suppress a decrease in characteristic impedance in the through-hole pair 3A and 3B. Therefore, according to the wiring board 100 of the present invention, a high frequency signal can be transmitted with low loss.

  Further, the strip-like wiring conductor pair 12A, 12B crosses one side parallel to the arrangement of the semiconductor element connection pad pair 10A, 10B in the mounting portion 2A so as to cross the external connection pad from below the through-hole pair 3A, 3B. It extends to above the pair 11A, 11B. The pair of strip-shaped wiring conductors 12A and 12B has an adjacent interval in the pair expanded so that the end on the mounting portion 2A side corresponds to the pair 3A and 3B of the through hole, and the expanded end and the through hole The pair 3A, 3B is electrically connected via the buildup wiring conductor 8 on the lower surface side. In this case, it is not necessary to extend the end portion on the mounting portion 2A side of the pair of strip-shaped wiring conductors 12A and 12B in a direction parallel to one side of the mounting portion 2A that the pair of strip-shaped wiring conductors 12A and 12B crosses. A large room for passing other wiring conductors between the conductor pairs 12A and 12B can be secured. Therefore, according to the wiring board 100 of the present invention, high-density wiring can be achieved.

DESCRIPTION OF SYMBOLS 1 ... Core substrate 2 ... Build-up part 2A ... Installation part 3 ... Through-hole 3A, 3B ... Through-hole pair 4 ... Core insulating plate 5 ... Core wiring conductor 6 ... Via hole 7 ... Build-up insulating layer 8 ... Build-up wiring conductor 10 ... Semiconductor element connection pad 10A , 10B... Semiconductor element connection pad pair 11... External connection pads 11A, 11B... External connection pad pair 12A, 12B... 2nd pitch P3 3rd pitch S Semiconductor element

Claims (1)

A core substrate in which a core wiring conductor is deposited on the upper and lower surfaces of the core insulating plate having a plurality of through holes, and a build-up insulating layer having a plurality of via holes on the upper and lower surfaces of the core substrate; A build-up portion formed by alternately laminating a plurality of build-up wiring conductors deposited on the surface of the build-up insulating layer including the inside of the via hole, and a semiconductor at the center of the upper surface of the build-up portion on the upper surface side A rectangular mounting portion on which elements are mounted and a plurality of semiconductor element connection pads made of the build-up wiring conductors are formed on the mounting portion in an array having grid points parallel to each side of the square at a first pitch. A plurality of external connection pads made of the build-up wiring conductor in the region including the outer peripheral portion on the lower surface of the build-up portion on the lower surface side. A semiconductor element connection formed in an array having lattice points with a second pitch larger than the pitch and adjacent to each other in a first direction parallel to one side of the square among the semiconductor element connection pads. A pair of pads and a core wiring conductor in a pair of adjacent through-holes arranged below the mounting portion are connected via the build-up wiring conductor on the upper surface side, and the inside of the pair of through-holes A core wiring conductor and a pair of external connection pads arranged adjacent to each other on the outer peripheral portion across the one side in the build-up portion on the lower surface side from above the mounting portion and above the pair of external connection pads A wiring board having a differential line connected through a pair of strip-like wiring conductors composed of the build-up wiring conductors extending to Wiring board, characterized in that arranged at the first pitch is greater than the third pitch in a second direction perpendicular to the direction.

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