JP5172590B2 - 積層配線基板の樹脂封止方法及び樹脂封止装置 - Google Patents
積層配線基板の樹脂封止方法及び樹脂封止装置 Download PDFInfo
- Publication number
- JP5172590B2 JP5172590B2 JP2008265235A JP2008265235A JP5172590B2 JP 5172590 B2 JP5172590 B2 JP 5172590B2 JP 2008265235 A JP2008265235 A JP 2008265235A JP 2008265235 A JP2008265235 A JP 2008265235A JP 5172590 B2 JP5172590 B2 JP 5172590B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- resin
- protective film
- recess
- upper mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C33/00—Moulds or cores; Details thereof or accessories therefor
- B29C33/56—Coatings, e.g. enameled or galvanised; Releasing, lubricating or separating agents
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14836—Preventing damage of inserts during injection, e.g. collapse of hollow inserts, breakage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
最初に、本実施形態で使用される積層配線基板について説明する。図4及び図5は本発明の実施形態の積層配線基板の樹脂封止方法で使用される積層配線基板を示す断面図である。
Claims (9)
- 下型と、
前記下型の上に配置されて、下面側に凹部が設けられ、前記凹部の底面周縁部に該凹部の開口部側に突出して部分的に底上げする突起部が設けられた上型と、
前記上型の下面側に設けられ、吸引吸着によって前記凹部の凹面に沿って密着する保護フィルムとを
含む樹脂封止装置と、
接続バンプを介して複数の配線基板が積層された積層配線基板とを用意する工程と、
前記下型と前記上型の凹部との間に前記積層配線基板を配置して挟んだ状態で、樹脂供給部から前記複数の配線基板の間を含むキャビティに溶融した樹脂を流入させて樹脂封止する工程とを有し、
前記樹脂封止する工程で、前記凹部の底面と前記突起部とにより前記保護フィルムが最上の前記配線基板の上面に押圧され、前記保護フィルムが前記最上の配線基板の上面全体に接触することを特徴とする積層配線基板の樹脂封止方法。 - 前記突起部の高さは、前記保護フィルムが前記上型の下面に吸引吸着される際に、前記上型の前記凹部の底面中央部と底面周縁部において、前記保護フィルムの下面が同一の高さになるように設定されることを特徴とする請求項1に記載の積層配線基板の樹脂封止方法。
- 前記上型の凹部の底面周縁部に設けられた突起部は、リング状に繋がって形成されていることを特徴とする請求項1に記載の積層配線基板の樹脂封止方法。
- 前記保護フィルムはテフロン(登録商標)からなることを特徴とする請求項1乃至3のいずれか一項に記載の積層配線基板の樹脂封止方法。
- 前記積層配線基板の下側の配線基板の上に半導体チップが実装され、前記半導体チップと上側の前記配線基板との間に前記樹脂が充填されることを特徴とする請求項1乃至3のいずれか1項に記載の積層配線基板の樹脂封止方法。
- 下型と、
前記下型の上に配置されて、下面側に凹部が設けられ、前記凹部の底面周縁部に該凹部の開口部側に突出して部分的に底上げする突起部が設けられた上型と、
前記上型の下面側に設けられ、吸引吸着によって前記凹部の凹面に沿って密着する保護フィルムとを有し、
接続バンプを介して複数の配線基板が積層された積層配線基板を、前記下型と前記上型の凹部との間に配置して挟んだ状態で、樹脂供給部から前記複数の配線基板の間を含むキャビティに溶融した樹脂を流入させて樹脂封止することを含み、
前記樹脂封止する際に、前記凹部の底面と前記突起部とにより前記保護フィルムが最上の前記配線基板の上面に押圧され、前記保護フィルムが前記最上の配線基板の上面全体に接触することを特徴とする樹脂封止装置。 - 前記突起部の高さは、前記保護フィルムが前記上型の下面に吸引吸着される際に、前記上型の前記凹部の底面中央部と底面周縁部において、前記保護フィルムの下面が同一の高さになるように設定されることを特徴とする請求項6に記載の樹脂封止装置。
- 前記上型の凹部の底面周縁部に設けられた突起部は、リング状に繋がって形成されていることを特徴とする請求項6又は7に記載の樹脂封止装置。
- 前記保護フィルムはテフロン(登録商標)からなることを特徴とする請求項6又は7に記載の樹脂封止装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008265235A JP5172590B2 (ja) | 2008-10-14 | 2008-10-14 | 積層配線基板の樹脂封止方法及び樹脂封止装置 |
US12/573,293 US8062571B2 (en) | 2008-10-14 | 2009-10-05 | Resin sealing method in stacked wiring substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008265235A JP5172590B2 (ja) | 2008-10-14 | 2008-10-14 | 積層配線基板の樹脂封止方法及び樹脂封止装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010097991A JP2010097991A (ja) | 2010-04-30 |
JP2010097991A5 JP2010097991A5 (ja) | 2011-09-15 |
JP5172590B2 true JP5172590B2 (ja) | 2013-03-27 |
Family
ID=42098142
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008265235A Active JP5172590B2 (ja) | 2008-10-14 | 2008-10-14 | 積層配線基板の樹脂封止方法及び樹脂封止装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8062571B2 (ja) |
JP (1) | JP5172590B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5778557B2 (ja) * | 2011-11-28 | 2015-09-16 | 新光電気工業株式会社 | 半導体装置の製造方法、半導体装置、及び半導体素子 |
JP5708688B2 (ja) * | 2012-08-27 | 2015-04-30 | 株式会社デンソー | センサパッケージの製造方法 |
US9245770B2 (en) * | 2012-12-20 | 2016-01-26 | Stats Chippac, Ltd. | Semiconductor device and method of simultaneous molding and thermalcompression bonding |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05190721A (ja) * | 1992-01-08 | 1993-07-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5292927A (en) * | 1992-02-26 | 1994-03-08 | The United States Of America As Represented By The Secretary Of The Navy | Fluorinated resins with low dielectric constant |
US5674343A (en) * | 1994-04-19 | 1997-10-07 | Nitto Denko Corporation | Method for manufacturing a semiconductor |
JP3214788B2 (ja) | 1994-11-21 | 2001-10-02 | アピックヤマダ株式会社 | 樹脂モールド装置および樹脂モールド方法 |
EP0730937B1 (en) | 1994-11-21 | 1998-02-18 | Apic Yamada Corporation | A resin molding machine with release film |
US5708300A (en) * | 1995-09-05 | 1998-01-13 | Woosley; Alan H. | Semiconductor device having contoured package body profile |
JP2971834B2 (ja) * | 1997-06-27 | 1999-11-08 | 松下電子工業株式会社 | 樹脂封止型半導体装置の製造方法 |
US5981312A (en) * | 1997-06-27 | 1999-11-09 | International Business Machines Corporation | Method for injection molded flip chip encapsulation |
KR100559664B1 (ko) * | 2000-03-25 | 2006-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US6770236B2 (en) * | 2000-08-22 | 2004-08-03 | Apic Yamada Corp. | Method of resin molding |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
US20040245674A1 (en) * | 2003-04-11 | 2004-12-09 | Yew Chee Kiang | Method for packaging small size memory cards |
US7147447B1 (en) * | 2005-07-27 | 2006-12-12 | Texas Instruments Incorporated | Plastic semiconductor package having improved control of dimensions |
TW200738076A (en) * | 2005-11-03 | 2007-10-01 | Endicott Interconnect Tech Inc | Dielectric composition for use in circuitized substrates and circuitized substrate including same |
WO2007069606A1 (ja) * | 2005-12-14 | 2007-06-21 | Shinko Electric Industries Co., Ltd. | チップ内蔵基板およびチップ内蔵基板の製造方法 |
JP2008066696A (ja) * | 2006-08-10 | 2008-03-21 | Denso Corp | 半導体製造装置および半導体製造方法 |
JP4842167B2 (ja) * | 2007-02-07 | 2011-12-21 | 新光電気工業株式会社 | 多層配線基板の製造方法 |
-
2008
- 2008-10-14 JP JP2008265235A patent/JP5172590B2/ja active Active
-
2009
- 2009-10-05 US US12/573,293 patent/US8062571B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8062571B2 (en) | 2011-11-22 |
US20100090369A1 (en) | 2010-04-15 |
JP2010097991A (ja) | 2010-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4504798B2 (ja) | 多段構成半導体モジュール | |
JP4208631B2 (ja) | 半導体装置の製造方法 | |
JP5579402B2 (ja) | 半導体装置及びその製造方法並びに電子装置 | |
US20110057327A1 (en) | Semiconductor device and method of manufacturing the same | |
JP2008166373A (ja) | 半導体装置およびその製造方法 | |
JP2012069903A (ja) | 半導体装置及びその製造方法 | |
TW201528460A (zh) | 半導體封裝結構以及其製造方法 | |
TW201336039A (zh) | 製造半導體裝置之方法 | |
JP2010186847A (ja) | 半導体装置及びその製造方法、並びに電子装置 | |
JP2009099697A (ja) | 半導体装置及びその製造方法 | |
JP2011249759A (ja) | 電子素子内蔵印刷回路基板及びその製造方法 | |
TW201620087A (zh) | 封裝結構及其製法 | |
JP2012212786A (ja) | 半導体装置の製造方法 | |
JP2014007228A (ja) | 半導体装置及びその製造方法 | |
TW201417661A (zh) | 具有電子元件之基板結構與製造具有電子元件之基板結構之方法 | |
JP2012221989A (ja) | 半導体装置製造装置、及び半導体装置の製造方法 | |
JP2012209449A (ja) | 半導体装置の製造方法 | |
JP2012146853A (ja) | 半導体装置の製造方法 | |
TW201507098A (zh) | 半導體裝置及其製造方法 | |
JP5172590B2 (ja) | 積層配線基板の樹脂封止方法及び樹脂封止装置 | |
US10804190B2 (en) | Multi-chip module and method for manufacturing same | |
JP2009135391A (ja) | 電子装置およびその製造方法 | |
KR101374146B1 (ko) | 반도체 패키지 제조 방법 | |
JP2012015554A (ja) | 半導体装置の製造方法、および積層型半導体装置の製造方法 | |
KR101494411B1 (ko) | 반도체패키지 및 이의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110802 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110802 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120629 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120710 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120827 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121211 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121226 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5172590 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |