JP4435052B2 - Manufacturing method of storage device - Google Patents

Description

  The present invention relates to a method for manufacturing a memory device using movement of particles between electrodes.

  In recent years, as the degree of integration of semiconductor devices has increased, the circuit patterns of LSI elements constituting the semiconductor devices have become increasingly finer. Such pattern miniaturization requires not only a reduction in line width but also an improvement in pattern dimensional accuracy and position accuracy. A memory device called a memory is no exception, and in a cell formed by making full use of high-precision processing technology, there is a continuing demand for holding a certain charge necessary for memory in a narrower region.

  Conventionally, various types of memories such as DRAM, SRAM, and flash have been manufactured. However, since these all use MOSFETs as memory cells, the dimensional accuracy at a ratio exceeding the ratio of miniaturization with the miniaturization of patterns. Improvement is demanded. For this reason, a large load is also imposed on the lithography technique for forming these patterns, which causes an increase in product cost (see, for example, Patent Documents 1 and 2).

On the other hand, as a technique for fundamentally solving such problems of microfabrication, there is an attempt to artificially synthesize a desired molecular structure and obtain a device having uniform characteristics by utilizing the uniformity of the obtained molecule. is there. However, in this type of method, there is a big problem in obtaining a technique for arranging the synthesized molecule at a desired position and obtaining electrical contact with the arranged electrode. In addition, since such an element stores data using a very small number of charges, there is a problem that the probability of malfunction due to disturbance such as natural radiation becomes very large.
Applied Physics Vol.69, No.10 pp1233-1240, 2000 "Semiconductor Memory; DRAM" Applied Physics Vol.69, No.12 pp1462-1466, 2000 “Flash Memory, Recent Topics”

  As described above, in the memory using the conventional MOSFET for the cell, as the pattern is miniaturized, the dimensional accuracy and alignment accuracy of the pattern become severe, and in addition to technical difficulties, the manufacturing cost increases. Have a factor. On the other hand, there is a concern that a memory using a molecular structure has a high probability of malfunction due to a disturbance in addition to problems related to molecular manipulation and contact with an electrode.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a storage device that can realize a highly integrated storage device that is not easily affected by disturbance at low cost. It is in. More specifically, an object of the present invention is to provide a method for manufacturing a storage device that can improve the manufacturing efficiency by preventing the aggregation of the fine particles when manufacturing the storage device using the fine particles.

  In order to solve the above problems, the present invention adopts the following configuration.

  In other words, according to one embodiment of the present invention, a first substrate provided with a plurality of row lines arranged in parallel and a plurality of column lines arranged in parallel are provided, and the column lines intersect the row lines. The second substrate disposed opposite to the first substrate with a gap between the first substrate and the row line and the column line, and selectively disposed at each intersection of the row line and the column line, and between the opposing row line and the column line. And a method of manufacturing a storage device comprising particles movable between adjacent intersections, wherein the particles are arranged at the intersections before the first and second substrates are opposed to each other. The solution in which the particles are dispersed in a solvent is discharged as droplets from a supply port to which an electric field is applied toward the row line forming surface of the first substrate or the column line forming surface of the second substrate. It is characterized by making it.

According to another aspect of the present invention, a first substrate provided with a plurality of row lines arranged in parallel and a plurality of column lines arranged in parallel are provided, and the column lines are the row lines. A second substrate disposed opposite to the first substrate via a gap so as to intersect with the first substrate, and a row line and a column which are selectively disposed at each intersection of the row line and the column line and which are opposed to each other. A method of manufacturing a storage device comprising particles that are movable between lines and between adjacent intersections, wherein the first and second substrates are arranged to face each other in order to arrange the particles at the intersections. Before, a solution in which the particles are dispersed in a solvent and a high viscosity resin soluble in the solvent is further mixed on the row line forming surface of the first substrate or the column line forming surface of the second substrate is rotated. It is characterized by removing components other than the particles in the solution by applying and subsequently performing an ashing treatment .

  According to the present invention, it is possible to function as a storage device by utilizing the presence or absence of particles between row lines and column lines, and in addition, in the production, particle aggregation is prevented and an efficient production method is realized. can do. In this case, as the circuit pattern of the memory portion, only the wiring of the first electrode and the second electrode need be formed, the structure is very simple, and the position in the cell compared to the case of using the MOSFET. Since the alignment and pattern dimensional accuracy become loose, the manufacturing cost can be suppressed. Furthermore, since the location of particles is used for data storage instead of charge accumulation, it is highly resistant to the influence of disturbance.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a perspective view showing a cell unit configuration of a storage device according to the first embodiment of the present invention. This device has already been filed by the present inventors as Japanese Patent Application No. 2004-171260.

  A plurality of row lines 11 arranged in parallel are embedded in the surface portion of the first substrate 10, and a plurality of column lines 21 arranged in parallel are embedded in the surface portion of the second substrate 20. Yes. The substrates 10 and 20 are arranged to face each other with a predetermined gap d so that the surface portions thereof face each other and the row lines 11 and the column lines 21 are orthogonal to each other.

  Here, the row line 11 is referred to as a word line and the column line 21 is referred to as a bit line in accordance with a normal MOS type memory cell.

  The intersection between the word line 11 and the bit line 21 corresponds to a memory cell, and fine particles 30 that can move between adjacent electrodes are selectively inserted into the gap between the word line 11 and the bit line 21 at each intersection. Has been placed. Here, the fine particles 30 can move not only in a direction perpendicular to the word lines 11 and the bit lines 21 but also in a direction parallel to the word lines 11 or the bit lines 21. That is, it can move between adjacent word lines or between adjacent bit lines along with the opposing direction of the substrates 10 and 20.

  In such a structure, the word lines 11 provided on the first substrate 10 and the bit lines 21 provided on the second substrate 20 are simple line-and-space patterns, and the word lines 11 and the bit lines 21 are orthogonal to each other. There is no need to consider the shift in the word line direction and the bit line direction. Therefore, the alignment accuracy in the cell is not required during manufacturing, and manufacturing can be easily performed.

  The operating principle of this structure will be explained using FIG. FIG. 2 is a schematic diagram for explaining the operation principle of the present embodiment, and corresponds to the AA cross section of FIG.

When the fine particle 30 of radius a on the electrode (word line 11, bit line 21) has a charge q and the fine particle 30 is placed in the electric field E by the voltage applied to the electrode, the fine particle 30 is charged. In addition to the force received from the electric field, a mirror image charge induced on the electrode and a force received from the mirror image dipole are added. These resultant forces F are given by the following equation (1) when approximated when the electrodes are infinitely wide.

Where ε ₀ is the dielectric constant of vacuum (about 8.85 × 10 ⁻¹² F / m), and ε _r is the relative dielectric constant of the fine particles.

Strictly speaking, when the gap is in the atmosphere, it is necessary to correct the dielectric constant, but the difference is extremely small and can be ignored, and the equation (1) can be used as it is. Since the charge q is always an integral multiple of the elementary charge e (about 1.6 × 10 ⁻¹⁹ C), it can be expressed as q = ne. The electric field E can be approximated by E = V / d, where V is the potential difference between the opposing electrodes and d is the interval.

On the other hand, the electrostatic capacity C of the fine particles 30 is given by C = 4πε ₀ a, and the charging energy by this is (½) q ² / C = n ² e ² / 8πε ₀ a. There is a phenomenon called a Coulomb barrier in which only electrons (or holes) having energy exceeding this energy can move to the fine particles 30. Therefore, the n-th electron (or hole) moves to the fine particle 30 only when the potential difference V satisfies eV> n ² e ² / 8πε ₀ a. In consideration of these circumstances, when the force F acting on the fine particles 30 defined by the equation (1) is graphed, FIG. 3 is obtained.

  FIG. 3 shows only the case of n = 1 and n = 2, which is sufficient for the description of this embodiment. Due to the existence of the aforementioned Coulomb barrier, each charged state is realized on the right side of the portion indicated by the dotted lines A1 and A2 in the figure, and until the electric field becomes a certain intensity or more even if charged, it is a mirror image. It can be seen that the attractive force due to is excellent and the fine particles do not leave the electrode. The most important thing is that separation always occurs under the condition of n = 1 in the section indicated by hatching in FIG. In FIG. 3, E1 represents a lower limit electric field necessary for separation when n = 1, and E2 represents a lower limit voltage (Coulomb barrier) necessary for charging when n = 2.

  The fine particles detached from the electrode are accelerated and reach the opposite electrode, whereupon the charge is released, and a new charge of the opposite sign is received, and the process of separating again and reaching the original electrode is repeated. Since electric charge is carried by this series of processes, it can be detected as a current between the electrodes. As described above, when these processes always occur at n = 1, a constant current flows and the presence or absence of fine particles can be easily detected. Furthermore, when two fine particles exist between the same electrodes, the carrier carrying the charge is doubled, and the moving distance is shortened, so that a current more than double is detected. It can be clearly detected that there is an individual.

  Specifically, when the radius a of the fine particles is 10 nm and the distance d between the electrodes is 60 nm, the separation and reciprocation of the fine particles in the above-described state of n = 1 may cause the voltage V between the electrodes to be 0.22 V to 0.29 V. Happens in the range. The interelectrode voltage V is 0.28V, + 0.14V corresponding to V / 2 is set for the upper electrode for selecting the intersection point, and -0.14V corresponding to -V / 2 is set for the lower electrode for selecting the intersection point. The other electrode was set to 0V. In this case, the force acting on the fine particles immediately after separation existing at the selected intersection is about 0.2 pN, and the time required for one-way movement is estimated to be about 70 nsec. It can be seen that a current of about 2 pA is detected because one charge is carried per one-way movement of one particle. Therefore, by measuring this current, it is possible to detect the presence / absence (number) of fine particles present at the intersection of the upper and lower electrodes.

  At the same time, an electric field is applied to neighboring fine particles, particularly fine particles existing in adjacent portions on the same electrode, but the intensity is inversely proportional to the distance. For this reason, when the pitch p in the lateral direction of the electrodes is 40 nm, the electric field for the nearest fine particles is reduced to about 83% and the electric field for the second adjacent fine particles is reduced to about 73%. When the voltage V between the electrodes is 0.28 V as described above, the nearest fine particles can be detached, but the electric field applied to the second neighboring fine particles does not reach the lower limit necessary for the separation. For this reason, only the latest fine particles become the object of interaction and, as will be described later, are used for the writing operation. When the voltage V between the electrodes is 0.26 V or less, the electric field applied to the latest fine particles does not reach the lower limit necessary for separation, and therefore, it can be used as a read-only mode without interaction.

  Further, the smallest unit constituting this embodiment is one linear electrode, at least two electrodes opposed to this via a gap, and at least one fine particle disposed in the gap, It can be seen that information is stored by utilizing the fact that the fine particles can move two-dimensionally between the electrodes.

Note that the size of each parameter can be selected from a wide range without being limited to the above-described example, and the range described below is theoretically possible based on the above approximation. In order to simplify the equation, the ratio between the electrode spacing d and the particle radius a is k (d = ka), and the ratio between the electrode horizontal pitch p and the electrode spacing d is κ (p = κd). b and β are defined by the following equations (2) and (3).

At this time, when using in an interactive mode, it is possible to select parameters within a range where the following expression (4) holds.

When used in the read-only mode, it is possible to select parameters within a range where the following expression (5) holds.

On the other hand, in order not to cause the interaction with the second adjacent fine particles as described above, it is necessary to design in advance that the following equation (6) is satisfied, or to use it under the condition that satisfies the equation (7). Become.

Further, the voltage application to the selected intersection is not limited to the method of applying the inter-electrode voltage V to + V / 2 and −V / 2 and applying it to the upper and lower selection lines as described above. It is possible to select within the range that satisfies the condition. The potential of the non-selection line is set to 0 V, the absolute values of the voltages applied to the upper and lower selection lines are compared, the larger one is set to Vm, and the ratio to the interelectrode voltage V is set to γ (Vm = γV, 0.5 ≦ γ ≦ 1). At this time, it is required that the following equation (8) is used or a design that satisfies equation (9) is used in advance.

For reference, if the values of the respective parameters in the above example are specified, k = 6, κ = 2/3, b = 1.005, β = 1.39 × 10 ⁹ [1 / V · m], γ = 0 .5.

  The interaction between the intersections only needs to be considered at the four most recent points, and the phenomenon that actually occurs is the movement of particles from the closest region to the selected intersection, but in the example of the electric field distribution described above, the movement is horizontal. It does not wake up in the direction, and it always moves up and down. That is, as shown in FIG. 4, there is a feature that the fine particles 30 on the same wiring as the selected intersection 31 move to the opposite side of the selected intersection 31. If it does not exist on the wiring, no movement occurs.

  Therefore, when it is desired to surely move the fine particles existing at a certain intersection point a to another nearest intersection point b, it is necessary to do the following. That is, a predetermined voltage is applied to the intersection point b, whether or not the current detected at the intersection point b becomes a predetermined value, and if not, the voltage is applied to the intersection point a. It is necessary to repeat the procedure of swinging the vertical position of the fine particles at the intersection point a and applying a predetermined voltage again to the intersection point b until the current detected at the intersection point b reaches a predetermined value.

  In view of this situation, three examples schematically shown in FIG. 5 are used as a writing method to the storage device. The portion shown in FIG. 5 is a part of the memory cell array 41 of FIG. 6, and similarly to the conventional memory, each row wiring includes a row decoder 42 and each column wiring includes a readout circuit. A driver 43 and a column decoder 44 are connected. Each decoder 42, 44 is connected to a higher level block 45 for giving address data and inputting / outputting data. By adopting such a configuration, it becomes possible to read out information of all columns included in the same row all at once.

  FIG. 5A shows a method in which one cell is formed at one intersection and 1-bit information is assigned thereto, and information on whether the number of particles present at the intersection is larger or smaller than a predetermined value is shown. Based on this, it stores whether the corresponding bit is “0” or “1”. The relationship between the number of particles and the correspondence between the bits “0” and “1” are arbitrary, and either one can be selected. Here, the bit is set when the number of particles is smaller than a predetermined value. The value “0” is associated with the bit value “1” when the value is large. As described above, since there is a clear correspondence between the number of fine particles present at the intersection and the current flowing through the intersection, the bit information is read when the voltage in the above-described reading mode is applied and the current flowing through the intersection. Is compared with a predetermined reference value.

  For reading, so-called random access in which an arbitrary intersection is selected is possible, but for writing, the following method is used. A reservoir of fine particles is formed outside the last row of the memory cell array 41. First, data to be written to the first row of the memory cells from the intersection of the last row (n-th row) of the memory cells. A predetermined voltage is applied to the intersection corresponding to the column to capture the fine particles.

  Specifically, in a state where only the last row (n-th row) is selected by the row decoder 42, only the column in which the bit value “1” is to be written to the first row is selected by the column decoder 44, and the last row (n-th row) is selected. The contents of the first line are formed in (line). Next, with the selection state of the column decoder 44 maintained, the operation of the row decoder 42 turns off the selection of the last row (n-th row) and the selection of the (n-1) -th row.

  As described above, all the fine particles may not move from the nth row to the (n−1) th row in one operation. Therefore, the current in each column is detected as it is, and the contents of the (n−1) th row are read. If the desired state is not reached, the selection of the (n−1) th row remains on and the nth row remains on. A series of operations of turning on the selection of the first row, turning off the selection of the nth row after one clock cycle or more and confirming the contents of the data of the (n-1) th row again, ) Repeat until the contents of the line are in the desired state. When the selection of the n-th row is turned on, the selection of the (n-1) -th row is also kept on, thereby preventing the particles from returning from the (n-1) -th row to the n-th row. However, it is possible to swing the vertical position of the fine particles left in the nth row.

  Subsequently, while maintaining the selected state of the column decoder 44, the contents of the (n-1) th row are moved to the (n-2) th row by the similar operation of the row decoder 42.

  By repeating this operation in order, the contents of the first row can be set to a desired state. Similarly, the data row to be written in the second row is also transferred to the third row by moving sequentially from the nth row, but first the selection of the first row is turned on before moving to the second row. In this state, an operation to turn on the selection of the second row is performed. As a result, the fine particles in the first row can be moved to the second row while preventing the fine particles in the first row from returning to the second row.

  Hereinafter, similarly, writing to the third row is performed. However, the selection of the first row and the second row may be kept on until the last row is moved from the fourth row to the third row. When the selection of the first row and the second row is turned off during the movement from the nth row to the fourth row, both are turned off and turned on at the same time in order to protect the written data. There is a need. Similarly, all data in the memory cell can be set to a desired state by executing writing to the fourth row, writing to the fifth row, and writing to the nth row.

  At the time of erasing, with all the columns selected by the column decoder 44, the same procedure as that at the time of writing is used to move all the particles in the n-th row to the reservoir, and subsequently (n-1) ) Move the fine particles in the row to the reservoir via the nth row. By sequentially performing this procedure up to the first row of fine particles, all fine particles are removed from the memory cell array, and the erase operation is completed. This method has the advantage of high integration, although the write / erase operation is complicated.

  FIG. 5B shows a method of assigning 1-bit information to a cell composed of two adjacent intersections, and the corresponding bit is “0” corresponding to which of the two intersections has more fine particles. "Or" 1 "is stored. It is arbitrary whether the adjacent intersection is in the vertical direction or the horizontal direction, or whether the case where many fine particles are present in the vertical and horizontal directions corresponds to the bit value “1”. In the illustrated example, the left and right pairs arranged in the row direction are used, and when the number of particles present at the right intersection is greater than that at the left, a bit value “1” is associated, and the particles present at the right intersection are detected. When the number is smaller than the left side, the bit value “0” is associated.

  In this method, bit information is read out by selecting a corresponding intersection point by the row decoder 42 and the column decoder 44, and according to the sign of the value obtained by subtracting the current flowing through the left intersection from the current flowing through the right intersection. Alternatively, it is performed by making "0" correspond.

  Specifically, the current flowing through the right intersection is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. After the current flowing through the left intersection is converted into a voltage using the reference resistor, the differential amplifier By inputting to the negative input terminal and detecting the sign of the output of the differential amplifier, the bit value “1” or “0” is made to correspond to the sign of the sign. In this reading method, since the bit value is determined using the difference in current flowing in the common row address line, even when there is a variation in resistance of the row address line, it can be detected with high accuracy, and the margin can be reduced. It is possible to expand. As for the column address line, since the difference detection is performed using the high-density adjacent wiring, it can be understood that the global resistance variation has the same effect.

  Conventionally, in a memory device in which a driving MOSFET is provided for each cell, it is necessary to control the threshold value of the MOSFET. Therefore, it is necessary to suppress the line width variation to 10% or less, preferably 5% or less of the line width. On the other hand, by using the present embodiment, it is possible to easily configure a cell without requiring such strict line width control.

  When writing "1", first, the right intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, and a predetermined voltage is applied for a predetermined time. As described above, since the fine particles may not move in one operation, the read operation in this state, that is, the right intersection and the left intersection are selected by the column decoder 44, and the currents flowing through them are compared. If the desired state is not reached, the right intersection is selected again by using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, and the data contents of the corresponding cell are confirmed again. A series of operations is repeated until a desired state is achieved.

  Alternatively, the right intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, the left intersection is additionally selected as it is, and the current at the corresponding intersection is detected. Read the contents. If the read result is not in the desired state, the selection of the left intersection is turned off while the selection of the right intersection is turned on, the selection of the left intersection is turned on after one clock cycle or more has passed, and the corresponding is applied again. A series of operations of confirming the contents of cell data is repeated until a desired state is achieved.

  In this method, the number of switching between selection and non-selection by the decoders 42 and 44 can be reduced. When writing “0”, the left and right may be interchanged with those when writing “1”. First, the left intersection of the corresponding cell is selected using the row decoder 42 and the column decoder 44, and a predetermined voltage is selected for a predetermined time. Apply. As described above, since the fine particles may not move in one operation, the read operation, that is, the left intersection and the right intersection are selected by the column decoder 44 in this state, and the currents flowing through them are compared. If the desired state is not reached, the left intersection is selected again using the row decoder 42 and the column decoder 44, a predetermined voltage is applied for a predetermined time, and the data content of the corresponding cell is confirmed again. A series of operations is repeated until a desired state is achieved.

  Alternatively, in order to save the number of switching between selection and non-selection by the decoders 42 and 44, the left intersection of the corresponding cell is selected by using the row decoder 42 and the column decoder 44, and a predetermined voltage is applied for a predetermined time, The right intersection is additionally selected to detect the current at both intersections, and the contents of the corresponding cell are read. If the read result is not in the desired state, the selection of the right intersection is turned off while the selection of the left intersection is turned on, and the selection of the right intersection is turned on after one clock cycle or more has passed. A series of operations of confirming the contents of cell data is repeated until a desired state is achieved.

  Unlike the previous example, one of the features of this method is that random access is possible for writing. In the illustrated example, one particle is exchanged between the left and right in one cell, but two or more particles are held in one cell, and at least one of them is held. Writing is also possible by exchanging the above. This is due to the fact that the bit value is inverted if the magnitude relationship between the number of fine particles at the left and right intersections is switched on the principle of reading. As an example, if there are three fine particles in a cell, it is possible to form a one-to-two state by the exchange of one fine particle when the number of fine particles at the left and right intersections is two to one. It can be seen that the bit values correspond to “0” and “1”, respectively.

  FIG. 5C shows a method of assigning 1-bit information to a cell composed of four intersections. The four intersections are two intersections (B, C) of a diagonal line that rises to the right, and a diagonal line that descends to the right. Whether the corresponding bit is “0” or “1” according to which group has a lot of fine particles in two groups of two intersections (A, D) Remember. There is an arbitrary choice as to which group has a large number of fine particles to correspond to the bit value “1”. In the example shown in the figure, when the number of particles present in the right-upward diagonal line pair is larger than that in the right-down diagonal line group, the bit value “1” is made to correspond, A bit value “0” is associated when the number is less than the pair of diagonal lines that descend to the right.

  The bit information is read by selecting the corresponding four intersections by the row decoder 42 and the column decoder 44, and subtracting the sum of the current flowing through the right-down diagonal pair from the sum of the current flowing through the right-up diagonal pair. The bit value “1” or “0” is made to correspond according to the sign of the value.

  Specifically, the current flowing through the intersection B is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. After the current flowing through the intersection A is converted into a voltage using the reference resistor, the differential amplifier Input to the negative input terminal. Then, by detecting the output of the differential amplifier, a value obtained by subtracting the number of particles present at the intersection A from the number of particles present at the intersection B is obtained, and this value (intersection B−intersection A) is temporarily stored in the driver. Keep in. Next, the current flowing through the intersection D is converted into a voltage using a reference resistor and then input to the positive input terminal of the differential amplifier. The current flowing through the intersection C is converted into a voltage using the reference resistor and then the negative input of the differential amplifier. Enter at the end. Then, by detecting the output of the differential amplifier, a value obtained by subtracting the number of particles present at the intersection C from the number of particles present at the intersection D (intersection D−intersection C) is obtained.

  Thereafter, the value of (intersection B + intersection C−intersection A−intersection D) is obtained by subtracting the value of (intersection D−intersection C) from the value of (intersection B−intersection A) temporarily stored in the driver. obtain. The bit value “1” or “0” is made to correspond to the sign of this value.

  In this reading method, the bit value is determined by using the difference between the currents flowing through the common row and column address lines. Therefore, even when there is a variation in resistance between the row and column address lines, it can be detected with high accuracy. Yes, it is possible to increase the margin. Conventionally, in a memory device in which a driving MOSFET is provided for each cell, it is necessary to control the threshold value of the MOSFET. Therefore, it is necessary to suppress the line width variation to 10% or less, preferably 5% or less of the line width. On the other hand, by using the present embodiment, it is possible to easily configure a cell without requiring such strict line width control.

  When writing “1”, the intersection B and intersection C of the corresponding cell are sequentially selected using the row decoder 42 and the column decoder 44 and a predetermined voltage is applied. Unlike the previous example, the write operation is completed by one voltage application to the intersection B and one voltage application to the intersection C. This is because the fine particles on the row address line move in the direction along the row address line, and the fine particles on the column address line move in the direction along the column address line, as described above. For example, the fine particles present at the intersection A move by pulling the fine particles from the two directions of the intersection B and the intersection C, regardless of whether they are present on the row address line or on the column address line. Because it is possible.

  In order to increase the reliability of storage, a read operation may be performed immediately after writing to confirm that the written information is stored correctly. Similarly, when “0” is written, the intersection A and intersection D of the corresponding cell may be sequentially selected using the row decoder 42 and the column decoder 44, and a predetermined voltage may be applied. The writing operation is completed by the application and the voltage application to the intersection D once.

  As described above, this method has an advantage that the write operation can be easily performed in a short time. In addition, one of the features of this system is that random access is possible for both reading and writing. In the illustrated example, a shape in which two fine particles are exchanged with different diagonal pairs in one cell is drawn, but one or more than three fine particles are held in one cell, Writing is also possible by exchanging at least one of them. As in the previous example, this is due to the bit value being inverted when the magnitude relationship between the numbers of particles present at different pairs of intersections on different diagonals is switched on the principle of reading.

As described so far, in this embodiment, charges are used for reading and writing information, but the stored contents are not the accumulated charges but the positions of the fine particles. There are characteristics that are not easily affected. Furthermore, since the size of the fine particles is on the order of 10 nm as in the above example, the gravitational force acting on the fine particles is only about 10 ^-18 N, and the movement of the fine particles due to the gravitational force acting on the fine particles and external impact should be ignored. As a matter of course, since magnetism is not used, the memory device is not affected by a magnetic field and is hardly affected by a disturbance.

(Second Embodiment)
FIG. 7 is a perspective view showing the overall configuration of the storage device according to the second embodiment of the present invention.

  A CMOS circuit 52 including a wiring layer is formed on a normal Si substrate 51 by a commonly used process, and a layer 53 including a plurality of memory cell portions 54 is formed thereon. 7 corresponds to the memory cell array 41 of FIG. 6, and a portion called a peripheral circuit in a normal memory including the driver / decoder and the upper block of FIG. 6 is shown. 7 CMOS circuit 52.

  The CMOS circuit 52 was designed and manufactured according to the 90 nm design rule, which is looser than the wiring of the memory cell portion 54 except for the connection portion with the memory cell portion 54. One memory cell portion occupies an area of about 11 μm square and includes 256 × 256 intersections. Each memory cell portion 54 has an electrical connection portion with the CMOS circuit 52 around the memory cell portion 54, and blocks each having the memory cell portion 54 and the peripheral connection portion as a unit are arranged in a matrix. Further, an input / output unit 55 of the device, which includes a through hole formed in the layer 53 including the memory cell unit 54 and is electrically coupled to the input / output unit of the CMOS circuit 52, is shown in FIG. Thus, it is formed at the end of the layer 53 including the memory cell portion 54.

  With such a configuration, a portion corresponding to the protective film of the CMOS circuit 52 can be used as an insulating film formed in the memory cell portion 54, while the memory cell portion 54 and the CMOS circuit 52 are coupled in the vertical direction. Therefore, it is possible to shorten the operation time and increase the number of cells that can be read / written simultaneously without increasing the chip area. The input / output unit 55 of the device is bonded to the lead frame in the packaging process in the same manner as a normal semiconductor device.

  As described above, since there are 256 × 256 intersections in one memory cell unit 54, 128 × 128 = 16384 bits are assigned when 1-bit information is allocated to a cell composed of four intersections. It is possible to assign information. However, in order to improve the reliability of the memory, an error correction code bit may be assigned to a part of the memory and used. For example, if 1 error correction code bit is assigned to 8 bits of external input / output data, net information of about 14336 to 14563 bits is assigned to the same array. As a result, the amount of information that can be stored in the same array is reduced, but the reliability of the memory can be greatly improved.

  The error correction codes may be arranged in the same row in the memory cell unit 54, arranged in the same memory cell unit 54, or distributed in a plurality of memory cell units 54 including data. It is possible, and the CMOS circuit 52 can determine which arrangement is performed. In order to read and write data at high speed, it is desirable to arrange them in the same row in the memory cell unit 54, and in order to increase the redundancy of data, it is desirable that the data is distributed as wide as possible. It is advantageous to disperse the memory cell units 54. When arranged in the same memory cell portion 54, the characteristics are intermediate between the two.

  Further, as in the case of a normal memory, the manufacturing yield can be improved by providing spare row wiring and column wiring in the memory cell portion 54 corresponding to a redundancy circuit that relieves defects during manufacturing. Is possible. In the present embodiment, since the size of one memory cell portion 54 is as small as about 11 μm square, by providing a spare memory cell portion 54, blocks including intersections of 256 × 256 are integrated into a circuit. It is also possible to relieve the defects by replacing them with.

  Separately from the relief circuit, the row wiring or the column wiring that is not used as the storage area, or both the row wiring and the column wiring are arranged in the peripheral portion of the memory cell section 54, so that the inside of the memory cell section 54 is provided. When excess or deficiency of fine particles occurs, it is possible to secure an area for supplying or storing fine particles. In this area, circuits such as a row decoder, a column decoder, and a driver are connected in the same way as a portion used as a storage area, and there is no difference in appearance. The difference in function is given to the upper block of the CMOS circuit 52. Specifically, it is used in the following initialization procedure.

  First, a predetermined voltage is sequentially applied to each intersection in the memory cell portion 54 to measure the flowing current, and the number of fine particles present at each intersection is measured. Next, when there is an excess or deficiency in the number of fine particles in a portion used as a storage area, the deficiency is eliminated by moving the fine particles sequentially to adjacent intersections. At this time, if there is a shortage in the entire storage area, fine particles are supplied from a storage area outside the storage area. On the contrary, when there are excessive particles in the entire storage area, the particles are stored in a storage area outside the storage area. Finally, the number of fine particles present at the intersection of the storage areas is measured again to confirm that the predetermined number of fine particles has been reached.

(Third embodiment)
FIG. 8 is a schematic configuration diagram showing a fine particle distribution apparatus according to the third embodiment of the present invention. This device is used in the method for manufacturing a storage device of the present invention.

  In the figure, reference numeral 81 denotes a hollow needle electrode for discharging a solvent in which fine particles are dispersed, and the base end side is connected to a pipe described later, and the solution is discharged from a supply port on the front end side. Furthermore, an electric field can be applied to the supply port on the distal end side of the needle electrode 81.

  82 is an extraction electrode for forming an electric field at the supply port on the distal end side of the needle electrode 81, 83 is a substrate corresponding to the first substrate 10 described in the first embodiment, and 84 is an extraction electrode with the needle electrode 81. A voltage control unit for applying an electric field between the electrode 82 and the substrate 83, 85 a solution discharge pump, 86 a substrate stage on which the substrate 83 is placed, 87 and 88 are pipes, and 89 is a raw material container. .

  Here, the voltage control unit 84 applies an electric field to the droplets discharged from the supply port on the distal end side of the needle electrode 81 to charge the droplets. The strength of the electric field for charging is adjusted so that the repulsive force due to charging is larger than the surface tension of the droplet before the droplet reaches the substrate.

  The fine particles are dispersed in a solvent and supplied to the hollow needle-like electrode 81 serving as a supply port. The fine particles are discharged as an electric field between the extraction electrode 82 and proceed toward the substrate 83. In the micro droplet, since the ratio of the surface area to the volume is large, the solvent molecules are rapidly evaporated from the surface. Furthermore, as described above, since the micro droplet discharged by the electric field has a large amount of charge on the surface, the repulsive force acting between the charges becomes very large and eventually exceeds the surface tension of the droplet. Then, the droplet breaks up into several droplets, and further evaporation of the solvent molecules proceeds. Then, as a result of repeating this process, the droplets are subdivided at once and the electric charge is transferred to the fine particles. Therefore, before reaching the substrate 83, the fine particles are charged and become individually independent, and fly on the substrate 83 while being dispersed without recombination due to repulsive force between charges.

  On the other hand, when a solvent droplet in which fine particles are simply dispersed is dropped on the substrate 83 without using an electric field, solvent molecules evaporate on the substrate, but the surface tension of the droplet becomes dominant. Therefore, as the size of the droplet is reduced, the interval between the fine particles is also reduced. Then, after the solvent is completely evaporated, the fine particles remain in an agglomerated mass. The agglomerated fine particles can be used as a storage device by forming an electrode, sequentially applying a voltage to the electrode, separating and aligning from the end, and performing initialization. However, according to the method described above, this process can be greatly simplified.

  As shown in FIG. 8, the electric field applied between the hollow needle electrode 81 and the extraction electrode 82 is controlled by the voltage output from the voltage control unit 84. Note that the voltage controller 84 can also control the voltage between the extraction electrode 82 and the substrate 83, and can adjust the kinetic energy of the fine particles flying on the substrate 83. Further, the voltage control unit 84 can be controlled in conjunction with the solution discharge pump 85 and the substrate stage 86, and when the desired position on the substrate 83 becomes a point where fine particles fly by the substrate stage 86, the voltage is controlled. To increase the particle size. Further, the solution discharge pump 85 can adjust the discharge amount in accordance with the spraying amount of the fine particles.

  The pipe 87 connecting the needle electrode 81 and the solution discharge pump 85 is made of a fluorine resin, which is a highly insulating synthetic resin, in order to isolate other portions from the voltage applied to the needle electrode 81. Yes. A fluorine resin that is the same material as the pipe 87 is also used for the pipe 88 that connects the raw material container 89 for storing the solvent in which the fine particles are dispersed and the solution discharge pump 85. This is because the fluorine resin is also excellent in low dust generation, and the manufacturing process suitability of the storage device as in this embodiment is good.

  In order to improve productivity, a plurality of hollow needle-like electrodes 81 and lead-out electrodes 82 are provided and can be configured in a linear or two-dimensional array. In this case, the voltage control unit 85 has a plurality of outputs to control the voltage of each electrode pair, thereby improving the controllability of each electrode pair, and the voltage control unit 85 has only one output. By controlling the voltages of all the electrode pairs at once, both methods for reducing the apparatus cost are possible.

FIG. 9 is an explanatory view schematically showing an enlarged view of the charged fine particles flying on the substrate. In order from the bottom, the substrate is a Si substrate 91 as a base substrate, a SiO ₂ film 93 having a thickness of 100 nm, a Si ₃ N ₄ film 94 having a thickness of 20 nm, a SiO ₂ film 95 having a thickness of 30 nm, and a Si _{3 having} a thickness of 20 nm. An N ₄ film 97 and a 40 nm thick SiO ₂ film 98 are formed. An aluminum wiring pattern 96 is formed on the SiO ₂ film 95.

As shown on the left side of FIG. 9, when negatively charged fine particles 99 approach this substrate, more positive polarization occurs on the aluminum surface as a conductor than the SiO ₂ film or Si ₃ N ₄ film as an insulator. Charge appears. For this reason, the fine particles 99 are attracted onto the wiring pattern 96 and automatically arranged on the wiring at a desired position without aggregation. The application amount of the fine particles 99 is determined by measuring the relationship with the voltage application time in advance and controlling the voltage application time so that the desired application amount is obtained.

  Here, the situation in which the fine particles 99 are excessively dispersed is shown on the right side of FIG. Since the fine particles 99 bring in negative charges, when the fine particles 99 are arranged on the wiring pattern 96, the entire wiring is negatively charged. As the fine particles 99 accumulate, there is a repulsive force of a magnitude that cancels the attractive force from the positive charges due to polarization. To occur. For this reason, the excessively supplied fine particles 99 are disposed at a place other than the wiring, but such fine particles 99 become useless fine particles 99 that cannot be used as a storage device as they are. . In order to prevent this, it is necessary to perform additional spraying after neutralization of the charged state by natural discharge or forced discharge by an ionizer. However, this process can be used to apply the fine particles 99 in another form as follows.

  First, only the solvent that does not contain the fine particles 99 is supplied by inverting the voltage polarity between the hollow needle electrode 81 and the extraction electrode 82 in the mechanism shown in FIG. At this time, positively charged solvent droplets are released and sequentially evaporated from the surface, so that the droplets are divided into several small droplets as in the case of including the fine particles 99, and further evaporation of the solvent molecules proceeds. Therefore, the droplet is subdivided at once. However, since the fine particles 99 are not included, when the last solvent molecule evaporates, charges cannot be delivered, and the solvent molecule itself reaches the substrate 83 in a positively ionized form. At this time, the polarity is reversed from that of FIG. 9, but positive ions are attracted onto the electrode by the polarization charge appearing on the electrode surface, and the electrode is positively charged.

  In this state, when the negatively charged fine particles 99 are dispersed as described above using the mechanism shown in FIG. 8, the electrode is positively charged in addition to the polarization charge, so that the fine particles 99 and the electrode surface are applied. As the attractive force is further increased, even if a small amount of fine particles 99 fly and bring in a negative charge, it is consumed for neutralization of the charge, so that more fine particles 99 are placed on the electrode before the electrode is negatively charged. It becomes possible to spray.

  Note that this step is not only performed by switching the chemical solution supplied to one hollow needle electrode 81 and extraction electrode 82 and the applied voltage, but also a plurality of hollow needle electrodes 81 and extraction electrode 82 sets and voltage control. It is also possible to divide into a group that includes the unit 85 and sprays only the solvent by positive ionization, and a group that sprays the fine particles 99 by negatively charging, and continuously sprays while moving in parallel on the substrate. .

(Fourth embodiment)
10 to 14 are cross-sectional views showing the manufacturing process of the memory device according to the fourth embodiment of the present invention. This describes a manufacturing process in the case where the storage device described in the first embodiment is manufactured using the fine particle distribution device described in the third embodiment.

First, as shown in FIG. 10A, a desired CMOS circuit 102 is formed on one main surface of a Si substrate (first substrate) 101 having a thickness of 625 μm using a normal CMOS process. A 30 nm-thickness SiO ₂ film 103 is formed thereon as an insulating film by a CVD method using TEOS as a main material. The CMOS circuit 102 includes a connection line to the memory cell array in addition to a normal MOSFET and multilayer wiring.

Subsequently, as shown in FIG. 10B, a Si ₃ N ₄ film 104 having a thickness of 20 nm is formed by LPCVD using dichlorosilane and ammonia as main materials. Subsequently, as shown in FIG. 10C, a 30 nm-thickness SiO ₂ film 105 is formed again by the CVD method using TEOS as a main material.

Next, as shown in FIG. 10 (d), a resist pattern (not shown) having a pitch of 40 nm is formed by using the imprint lithography technique, and CHF ₃ and CO gas are added using the obtained resist pattern as a mask. Then, the SiO ₂ film 105 is patterned by reactive ion etching. Subsequently, as shown in FIG. 10E, after forming an Al film by a sputtering method, a so-called reflow process is performed, the Al film 106 is agglomerated and embedded in the pattern groove, and then the excess Al film 106 is formed by the CMP method. Remove.

On the other hand, as shown in FIG. 11A, another Si substrate (second substrate) 201 cleaned with dilute hydrofluoric acid having a thickness of 625 μm is prepared, and a film is formed on the entire surface of the substrate 201 at a temperature of 950 ° C. A thermal oxide film (SiO ₂ film) 203 having a thickness of 100 nm is formed. Subsequently, as shown in FIG. 11 (b), after an Si ₃ N ₄ film 204 having a thickness of 20nm by an LPCVD method using dichlorosilane and ammonia as main materials, the back side the Si ₃ N ₄ film 204 and The SiO ₂ film 203 is peeled off. Thereafter, as shown in FIG. 11C, an SiO ₂ film 205 having a thickness of 30 nm is formed as an insulating film on the Si ₃ N ₄ film 204 on the substrate surface side by a CVD method using TEOS as a main material.

Next, as shown in FIG. 11 (d), a resist pattern (not shown) with a pitch of 40 nm is formed by using the imprint lithography technique, and CHF ₃ and CO gas are used using the obtained resist pattern as a mask. The SiO ₂ film 205 is patterned by the reactive ion etching. Subsequently, as shown in FIG. 11E, after forming an Al film by a sputtering method, a so-called reflow process is performed, the Al film 206 is agglomerated and embedded in the pattern groove, and then the excess Al film 206 is formed by the CMP method. Remove.

Next, as shown in FIG. 11F, a Si ₃ N ₄ film 207 having a film thickness of 20 nm is formed by plasma nitriding, LPCVD using dichlorosilane and ammonia as main materials. Subsequently, as shown in FIG. 12G, a SiO ₂ film 208 having a film thickness of 40 nm is formed as an insulating film by a CVD method using TEOS as a main material.

Next, as shown in FIG. 12 (h), the connection portion with the CMOS circuit is patterned by a photolithography process, and reactive ion etching is performed using CHF ₃ and CO gas using a resist pattern (not shown) as a mask. Thus, the SiO ₂ film 208 is patterned. Subsequently, as shown in FIG. 12 (i), the Si ₃ N ₄ film 207 is patterned by reactive ion etching using CHF ₃ , CF ₄ and O ₂ gas.

  Next, as shown in FIG. 12 (j), after an Al film 209 is formed again by sputtering, so-called reflow treatment is performed, and Al is coagulated and embedded in the obtained opening. Subsequently, as shown in FIG. 12K, the excess Al film 209 is removed by the CMP method.

Next, as shown in FIG. 13L, the memory cell array portion is patterned by a photolithography process, and the SiO ₂ film 208 is formed by reactive ion etching using CHF ₃ and CO gas using the resist pattern as a mask. Pattern. Subsequently, as shown in FIG. 13 (m), the Si ₃ N ₄ film 207 is patterned by reactive ion etching using CHF ₃ , CF ₄ and O ₂ gas.

  Next, as shown in FIG. 13 (n), a solution in which colloidal silica particles having a particle diameter of 14 nm formed by the reverse micelle method are dispersed in isopropyl alcohol is dispersed using the apparatus having the structure shown in FIG. An amount of fine particles 210 are arranged on the wiring of the memory cell array portion. Subsequently, as shown in FIG. 13 (o), the obtained substrate is turned upside down. Subsequently, as shown in FIG. 13 (p), the substrate is rotated so that the wiring is in a predetermined direction.

  Next, as shown in FIG. 14, the substrate obtained in FIG. 10 (e) and the substrate obtained in FIG. 13 (p) are aligned and directly bonded in a dry nitrogen atmosphere at 1 atm. Bond two substrates together. Subsequently, in order to ensure the strength of direct bonding, heat treatment was performed for 1 hour in a nitrogen atmosphere at 200 ° C. after bonding. Finally, the Si portion of the upper substrate 201 is removed by polishing to form a wiring connection portion serving as an input / output portion, and then a so-called post-process such as inspection or dicing is performed to complete the storage device.

  As described above, according to the present embodiment, when the fine particles are arranged on the substrate, a device in which colloidal silica particles are dispersed in isopropyl alcohol is used as a needle-like hollow to which an electric field is applied. It is made to discharge as a droplet from the supply port of the electrode 81. Thereby, the fine particles are charged, and the droplets are subdivided and dispersed as the solvent evaporates, and the fine particles are arranged on the substrate without recombination due to repulsive force between the charges. For this reason, aggregation of fine particles can be prevented, and the production efficiency can be improved.

(Fifth embodiment)
15A to 15C are cross-sectional views showing the manufacturing process of the memory device according to the fifth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 11-13 same part, and the detailed description is abbreviate | omitted.

  Unlike the manufacturing method described in the fourth embodiment, this embodiment is a method for manufacturing a storage device without using a special fine particle distribution device.

  According to the method for manufacturing a storage device described in the fourth embodiment, it is possible to suppress excessive consumption of fine particles for realizing the function of the storage device and wasteful consumption such as discharge of fine particles to the outside of the substrate at the time of spraying. However, a new apparatus as shown in FIG. 8 is required. However, since the introduction of a new device requires a large amount of cost, such as the cost of installing in a clean room, in addition to the cost of the main body of the device, manufacturing can be performed using existing equipment if possible. desirable. Therefore, in the present embodiment, a technique is provided in which fine particles are dispersed on a substrate using a spin coater and a CMP apparatus.

  Since a solution in which fine particles are simply dispersed in a solvent such as an organic solvent or water has low viscosity, it is difficult to form a uniform film even if normal spin coating is attempted. Therefore, polyvinyl alcohol, which is a high viscosity resin, is added as means for adjusting the viscosity. Due to the increase in viscosity, even if the fine particles try to agglomerate, the viscous resistance prevents the fine particles from aggregating. Polyvinyl alcohol is not only capable of adjusting the viscosity in a wide range, but also easily dissolves in high-temperature water, but has a feature that the dissolution rate is not so high in water near room temperature. In addition to being able to use high-temperature water, a very inexpensive and easy-to-handle solvent, if a re-application is necessary for any reason, this is possible because of the formation of embedded shapes by CMP using water as a solvent near room temperature. Is an advantage that is possible.

  The solubility in water is further reduced by heat treatment, and swelling can be suppressed by heat treatment at about 100 to 180 ° C. Furthermore, since polyvinyl alcohol has a very low environmental load, it can be easily treated after use. Then, it is possible to remove only polyvinyl alcohol from the mixture of polyvinyl alcohol and fine particles, leaving only fine particles on the substrate by plasma ashing treatment using oxygen gas, which is generally used.

  Specifically, a solution in which colloidal silica particles having a particle size of 14 nm formed by the reverse micelle method are dispersed in pure water is prepared, and a solution containing 3% by weight of polyvinyl alcohol having an average degree of polymerization of 1800 is prepared. To do. This solution is spin-coated on a substrate at a rotation speed of 2000 rpm using a normal spin coating apparatus. After coating, heat treatment is performed at 180 ° C. for 15 minutes to form a mixed film in which colloidal silica fine particles are dispersed in a polyvinyl alcohol resin film. At this time, since the solution as a raw material has high viscosity, the uniformity of coating is very good. On the substrate, patterning is performed in advance so that the portion where the fine particles are to be arranged becomes a recess.

  Next, the mixed film of the polyvinyl alcohol film and the fine particles is polished from the surface by CMP using water kept near room temperature. When the polyvinyl alcohol is polished and dissolved, the fine particles contained in the portion are also discharged, so that at the end point of CMP, the mixed film remains only in the previously formed recess. Then, by removing only the polyvinyl alcohol by plasma ashing using oxygen gas, it is possible to dispose the fine particles only in the previously formed recesses without agglomeration.

In the entire manufacturing process, the CMOS circuit 102 is formed on one main surface of the Si substrate 101 in the same manner as in FIGS. 10A to 10E, and the SiO ₂ film 103 and the Si ₃ N ₄ film 104 are formed thereon. , And the SiO ₂ film 105 are formed. Subsequently, after the SiO ₂ film 105 is patterned, an Al film 106 is embedded in the pattern groove.

11A to 13M, a thermal oxide film 203, a Si ₃ N ₄ film 204, and a SiO ₂ film 205 are formed on another substrate 201, and then SiO _2. The film 205 is patterned, and an Al film 206 is embedded in the pattern groove. Subsequently, after forming the Si ₃ N ₄ film 207 and the SiO ₂ film 208, the SiO ₂ film 208 is patterned for patterning the connection portion with the CMOS circuit, and the Si ₃ N ₄ film 207 is further patterned. Thereafter, after the Al film 209 is buried and formed, the SiO ₂ film 208 is patterned and the Si ₃ N ₄ film 207 is patterned in order to pattern the memory cell array portion.

  Next, as shown in FIG. 15A, a solution containing fine particles 210 is formed by coating on the substrate having the structure shown in FIG. That is, an ordinary spin coater is prepared by mixing a coating solution in which 3% by weight of polyvinyl alcohol having an average degree of polymerization of 1800 is mixed with a solution in which colloidal silica particles having a particle size of 14 nm formed by the reverse micelle method are dispersed in pure water. Is applied at a rotational speed of 2000 rpm. After coating, heat treatment is performed at 180 ° C. for 15 minutes to form a mixed film 220 of polyvinyl alcohol and fine particles 210.

  Next, as shown in FIG. 15B, the excess mixed film 220 is removed by a CMP method using pure water maintained at room temperature. Subsequently, as shown in FIG. 15C, the polyvinyl alcohol is removed by plasma ashing using oxygen gas, leaving only the fine particles 210 on the substrate.

  Next, the obtained substrate is turned upside down in the same manner as in FIG. Subsequently, the substrate is rotated so that the wiring is in a predetermined direction in the same manner as 13 (p).

  Then, in the same manner as in FIG. 14, the alignment of the substrate obtained in FIG. 10 (e) and the substrate obtained in FIG. 15 (c) is performed, and direct bonding is performed under a dry nitrogen atmosphere of 1 atm. Bond two substrates together. Subsequently, in order to ensure the strength of direct bonding, heat treatment was performed for 1 hour in a nitrogen atmosphere at 200 ° C. after bonding. Finally, the Si portion of the upper substrate is removed by polishing to form a wiring connection portion serving as an input / output portion, and then a so-called post-process such as inspection or dicing is performed to complete the storage device.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, colloidal silica, which is an insulator made of silicon oxide, is used as the particles used for the memory operation. However, other inorganic oxides such as aluminum oxide and titanium oxide can also be used, and organic substances such as polystyrene can be used. It is also possible to use. Furthermore, since it is not necessary in principle to be an insulator, for example, a metal particle such as a conductor such as chromium, nickel, copper, gold, titanium, and aluminum, a particle made of an alloy containing them, or a carbon particle or a semiconductor. Some silicon particles may be used. The shape of the particles need not be spherical, and may be a polyhedral shape, an ellipsoid, or a column.

  In addition, the row lines and the column lines do not necessarily have to be orthogonally arranged, and may be in a crossed relationship. Furthermore, conditions such as the gap length between the first and second electrodes and the size of the particles can be appropriately changed according to the specifications.

  Further, in the embodiment, the storage device including both the data reading unit and the data writing unit has been described. However, both units are not necessarily provided, and only one of them may be provided. For example, when considering using the storage device of the present invention as a ROM, the storage device main body as shown in FIG. It is only necessary to provide data reading means on the side using the.

  In addition, various modifications can be made without departing from the scope of the present invention.

The perspective view which shows the cell part structure of the memory | storage device concerning 1st Embodiment. The schematic diagram for demonstrating the operation | movement principle of 1st Embodiment. The characteristic view which graphs and shows the force which acts on particle | grains. The perspective view which shows the mode of movement of particle | grains typically. The schematic diagram which shows the relationship between a cross | intersection part and a cell, and the memory state by particle | grains. 1 is a block diagram showing a schematic configuration of a memory device including a peripheral circuit. The perspective view which shows the whole structure of the memory | storage device concerning 2nd Embodiment. The schematic block diagram which shows the fine particle distribution apparatus concerning 3rd Embodiment. The schematic diagram for demonstrating the operation | movement of 3rd Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 4th Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 4th Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 4th Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 4th Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 4th Embodiment. Sectional drawing which shows the manufacturing process of the memory | storage device concerning 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... 1st board | substrate 11 ... Row line 20 ... 2nd board | substrate 21 ... Column line 30 ... Fine particle 31 ... Selected intersection 41 ... Memory cell array 42 ... Row decoder 43 ... Driver 44 ... Column decoder 45 ... Upper block 51 ... Si substrate 52 ... CMOS circuit 53 ... Layer including memory cell 54 ... Memory cell portion 55 ... Input / output portion 81 ... Hollow needle electrode 82 ... Drawer electrode 83 ... Substrate 84 ... Voltage control unit 85 ... Solution discharge pump 86 ... Substrate stage 87,88 ... pipe 89 ... raw material container 91,101,201 ... Si substrate 102 ... CMOS circuit 93,95,98,103,105,203,205,208 ... SiO ₂ film 94,97,104,204,207 ... Si ₃ N ₄ film 96, 106, 206, 209... Al film 99, 210... Fine particle 220.

Claims (5)

A first substrate provided with a plurality of row lines arranged in parallel, and a plurality of column lines arranged in parallel, and the first substrate and a gap so that the column lines intersect the row lines. Is selectively disposed at each intersection between the row line and the column line, and is movable between the opposing row line and the column line and between adjacent intersections. And a method of manufacturing a storage device including various particles,
In order to arrange the particles at the intersection, the first substrate and the second substrate are arranged opposite to each other, and are directed toward the row line forming surface of the first substrate or the column line forming surface of the second substrate. A method for manufacturing a memory device, comprising: discharging a solution in which the particles are dispersed in a solvent as droplets from a supply port to which an electric field is applied.   The droplet discharged from the supply port is charged by the electric field, and the repulsive force due to charging is larger than the surface tension of the droplet before the droplet reaches the substrate. 2. The method of manufacturing a storage device according to claim 1, wherein the strength of the electric field is set.   3. The method of manufacturing a storage device according to claim 1, wherein a plurality of supply ports are provided per substrate. A first substrate provided with a plurality of row lines arranged in parallel, and a plurality of column lines arranged in parallel, and the first substrate and a gap so that the column lines intersect the row lines. Is selectively disposed at each intersection between the row line and the column line, and is movable between the opposing row line and the column line and between adjacent intersections. And a method of manufacturing a storage device including various particles,
In order to dispose the particles at the intersection, the row line forming surface of the first substrate or the column line forming surface of the second substrate is disposed on the row line forming surface of the first substrate before the first and second substrates are opposed to each other. A solution in which particles are dispersed in a solvent and a high-viscosity resin that is soluble in the solvent is further mixed by spin coating , followed by ashing to remove components other than the particles in the solution. A method for manufacturing a storage device. 5. The method of manufacturing a storage device according to claim 4 , wherein a CMP process is performed on the surface on which the solution is spin-coated before the ashing treatment .

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