JP4323873B2 - I / O interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides jitter tolerance when performing data transmission / reception between LSIs (Large-Scale Integrated Circuits), data transmission / reception between a plurality of elements and circuit blocks in an LSI chip, and data transmission / reception between boards and enclosures. Can be tested Nairi The present invention relates to an output interface circuit.
[0002]
[Prior art]
In general, transmission / reception data in data transmission / reception between circuit blocks, between chips, or in a housing includes jitter (phase fluctuation) corresponding to the usage environment such as transmission line characteristics. The data receiving circuit has a clock recovery circuit so that data including jitter can be correctly determined. Many standards relating to data transmission and reception define jitter tolerance (jitter tolerance) as the minimum amount of jitter that a data receiving circuit must correctly determine data. Satisfying jitter tolerance is essential in data transmission and reception design. It is also possible to evaluate the performance of the data receiving circuit by measuring the jitter tolerance.
[0003]
Specifically, as a test of a network termination device used in an integrated service digital network, a signal with a prescribed jitter superimposed is received without error by superimposing the required jitter on the signal input to the network termination device. A jitter superimposing method capable of testing the performance to be disclosed is disclosed (for example, refer to Patent Document 1). Also disclosed is a delay jitter inserter for a packet test apparatus that can add delay jitter close to the actual state of the network by adding both delay jitter and advance jitter to the transmitted packet in the packet test apparatus. (For example, refer to Patent Document 2 and Patent Document 3.)
[0004]
However, the jitter tolerance in the mass production test cannot be evaluated for the above-described data transmission / reception circuit. This is because an expensive system cannot be used in the mass production test due to cost, and it is impractical to construct another system that generates transmission / reception data including jitter intended by the measurer. For example, in a conventional mass production test, a data reception circuit is tested by a loop configuration in which transmission data from a data transmission circuit is directly input to the data reception circuit. FIG. 11 is a diagram showing a loop configuration for testing the data transmission / reception circuit (input / output interface circuit).
[0005]
In FIG. 11, 1 is a data transmission / reception circuit, which is based on a data transmission circuit 2 that outputs serial data TXRX_DT, a data reception circuit 3 that receives serial data TXRX_DT output by the data transmission circuit 2, and a basic clock signal REF_CK. The clock generation circuit 4 outputs the clock signal TX_CK and the clock signal RX_CK to the data transmission circuit 2 and the data reception circuit 3, respectively.
[0006]
Specifically, the clock generation circuit 4 illustrated in FIG. 11 generates a clock signal TX_CK having a frequency of 5 G (giga) Hz based on the basic clock signal REF_CK having a frequency of 625 M (mega) Hz as the data transmission circuit 2. And a clock signal RX_CK having the same frequency of 5 GHz is output to the data receiving circuit 3. The transmission speed of serial data TXRX_DT transmitted / received between the data transmission circuit 2 and the data reception circuit 3 is 10 Gbps (bits / second).
[0007]
Next, the internal configuration of the data transmission circuit 2 will be described. As shown in FIG. 11, the data transmission circuit 2 includes a clock control circuit 21, a PRBS (pseudo random bit sequence) pattern generation circuit 22, selectors 23 and 24, a 32: 4 conversion circuit 25, and a driver circuit. 26. The clock control circuit 21 receives a clock signal TX_CK having a frequency of 5 GHz from the clock generation circuit 4 and shifts the phase by 90 degrees at a frequency of 2.5 GHz, so that a 4-bit clock signal TX_DCK having four types of phases is obtained. Is output to the 32: 4 conversion circuit 25 and the driver circuit 26.
[0008]
Each of the 4-bit clock signals TX_DCK is assumed to be TX_DCK_A, TX_DCK_B, TX_DCK_C, and TX_DCK_D. The clock control circuit 21 divides the clock signal TX_CK by 1/16 and outputs a 312.5 MHz clock signal CLK to the PRBS pattern generation circuit 22.
[0009]
The PRBS pattern generation circuit 22 generates 32-bit data PRBS_DT [31: 0], which is a pseudo random pattern for testing the data transmission / reception circuit 1, in synchronization with the clock signal CLK output from the clock control circuit 21. And output. The PRBS pattern generation circuit 22 is activated when the enable signal PRBS_EN is at an H (high) level. The enable signal PRBS_EN is a signal that is at the L (low) level during the normal operation of the data transmitting / receiving circuit 1 and is at the H level during the test. Details of the PRBS pattern generation circuit 22 will be described later.
[0010]
The selectors 23 and 24 switch signals input to the 32: 4 conversion circuit 25 between the test of the data transmission circuit and the normal operation. Specifically, the selector 23 normally selects a clock signal USER_CK having an arbitrary frequency from the outside and outputs it as a clock signal TX_ICK to the 32: 4 conversion circuit 25 during normal times, and a PRBS pattern generation circuit during testing. The clock signal PRBS_CK output from the signal 22 is selected and output to the 32: 4 conversion circuit 25 as the clock signal TX_ICK. Further, the selector 24 normally selects any 32-bit data USER_DT [31: 0] from the outside and outputs it to the 32: 4 conversion circuit 25 as data TX_IDT [31: 0]. The 32-bit data PRBS_DT [31: 0] output from the PRBS pattern generation circuit 22 is selected and output to the 32: 4 conversion circuit 25 as data TX_IDT [31: 0].
[0011]
Further, the 32: 4 conversion circuit 25 converts the input 32-bit data TX_IDT [31: 0] into 4-bit data TX_DT [3: 0] and outputs the converted data to the driver circuit 26. Specifically, the 32: 4 conversion circuit 25 takes in the 32-bit data TX_IDT [31: 0] in synchronization with the 312.5 MHz clock signal TX_ICK and performs a data width conversion process from 32 bits to 4 bits. Then, 4-bit data TX_DT [3: 0] synchronized with the 4-bit 2.5 GHz clock signal TX_DCK is output. Here, 4-bit data TX_DT [3: 0] is assumed to be TX_DT_A, TX_DT_B, TX_DT_C, and TX_DT_D.
[0012]
Next, the driver circuit 26 converts the 4-bit data TX_DT [3: 0] into 1-bit serial data TXRX_DT and outputs it. Specifically, the driver circuit 26 converts 4-bit data TX_DT [3: 0] into 1-bit serial data TXRX_DT using a 4-bit clock signal TX_DCK having different phases, and outputs it at a transmission rate of 10 Gbps. To do.
With the configuration described above, the data transmission circuit 2 converts the test 32-bit 312.5 Mbps data PRBS_DT generated by the PRBS pattern generation circuit 22 into 1-bit 10 Gbps serial data TXRX_DT during the test. Output.
[0013]
Next, the internal configuration of the data receiving circuit 3 will be described. As shown in FIG. 11, the data receiving circuit 3 includes a clock control circuit 31, a receiver circuit 32, a 4:32 conversion circuit 33, and a pattern comparison circuit 34. The clock control circuit 31 receives the clock signal RX_CK having a frequency of 5 GHz from the clock generation circuit 4 and shifts the phase by 90 degrees at a frequency of 2.5 GHz, so that the 4-bit clock signal RX_DCK has four types of phases. Is output to the 4:32 conversion circuit 33 and the receiver circuit 32. Each of the 4-bit clock signals RX_DCK is assumed to be RX_DCK_A, RX_DCK_B, RX_DCK_C, and RX_DCK_D.
[0014]
The receiver circuit 32 receives the serial data TXRX_DT transmitted from the data transmission circuit 2 and outputs 4-bit received data RX_DT [3: 0] and received data RX_BDT [3: 0]. Specifically, the receiver circuit 32 receives serial data TXRX_DT of 10 Gbps with 1 bit according to the timing of the 4-bit clock signal RX_DCK having different phases, and received data RX_DT [3: 0 with 4 bits of 2.5 Gbps. ] And received data RX_BDT [3: 0]. The reception data RX_DT [3: 0] is reception data obtained by taking each data of the serial data TXRX_DT at a timing at which it can be reliably received and converting it into 4 bits. Also, the reception data DX_BDT [3: 0] is reception data that is captured at the change point timing in each data of the serial data TXRX_DT and converted into 4 bits.
[0015]
The 4:32 conversion circuit 33 receives 4-bit reception data DX_DT [3: 0] and reception data DX_BDT [3: 0] input from the receiver circuit 32, and receives 32-bit reception data RX_ODT [31: 0]. Data RX_OBDT [31: 0] is converted and output. Specifically, the 4:32 conversion circuit 33 uses the 4-bit 2.5 Gbps reception data DX_DT [3: 0] and the reception data DX_BDT [3: 0] input from the receiver circuit 32 as the clock control circuit 31. In response to the input 4-bit clock signal RX_DCK, it is converted into reception data RX_ODT [31: 0] and reception data RX_OBDT [31: 0] of 312.5 Mbps in 32 bits and output. The reception data RX_ODT [31: 0] is input to the pattern comparison circuit 34 and the filter circuit 35. The reception data RX_OBDT [31: 0] is input to the filter circuit 35. The 4:32 conversion circuit 33 divides the 2.5 GHz clock signal DX_DCK by 1/8 and outputs a 312.5 MHz clock signal RX_OCK to the pattern comparison circuit 34 and the filter circuit 35.
[0016]
The pattern comparison circuit 34 compares the reception data RX_ODT [31: 0] output from the 4:32 conversion circuit 33 with an expected value, and outputs an error flag ERROR that is a signal for detecting an error during reception. Specifically, the pattern comparison circuit 34 takes in the 32-bit reception data RX_ODT [31: 0] output from the 4:32 conversion circuit 33 in synchronization with the clock signal RX_OCK output from the 4:32 conversion circuit 33. Then, processing to compare with the expected value is performed. The pattern comparison circuit 34 is activated when the enable signal COMP_EN is at the H (high) level. The enable signal COMP_EN is a signal that is at the L (low) level during the normal operation of the data transmitting / receiving circuit 1 and is at the H level during the test. Details of the pattern comparison circuit 34 will be described later.
[0017]
Based on the reception data RX_ODT [31: 0] and reception data RX_OBDT [31: 0] output from the 4:32 conversion circuit 33, the filter circuit 35 detects the phase shift of the clock signal RX_DCK output from the clock control circuit 31. A signal PI_CODE for adjustment is output. Thus, for example, when the serial data signal TXRX_DT is captured at the rising edge of the clock signal RX_DCK, the rising edge of the clock signal RX_DCK is in the middle of the change point in each data of the serial data signal TXRX_DT (at a timing at which data can be reliably captured). As described above, the operation of the clock control circuit 31 can be controlled.
[0018]
Next, a conventional circuit configuration example in the clock generation circuit 4 shown in FIG. 11 will be described.
FIG. 12 is a diagram showing a conventional circuit configuration example in the clock generation circuit 4 shown in FIG. As shown in FIG. 12, the clock generation circuit 4 includes a phase comparator 41, a filter 42, a VCO (Voltage Controlled Oscillator) 43, a frequency divider 44, and buffers 45 and 46. Here, it is clear that the phase comparator 41, the filter 42, the VCO 43, and the frequency divider 44 form a PLL (Phase Locked Loop), and thus the frequency is determined based on the 625 MHz reference clock signal REF_CK. The clock signal TX_CK and the clock signal RX_CK of 5 GHz multiplied by 8 can be output with a stable phase.
[0019]
Next, a conventional circuit configuration example in the PRBS pattern generation circuit 22 shown in FIG. 11 will be described.
FIG. 13 is a diagram showing a conventional circuit configuration example in the PRBS pattern generation circuit 22 shown in FIG. As shown in FIG. 13, the conventional PRBS pattern generation circuit 22 includes flip-flops 221, 222, a logic element 223, a flip-flop 224 with an enable function, an XOR (exclusive OR) group 225, a buffer 226, 227.
[0020]
The flip-flop 221 latches the enable signal PRBS_EN from the outside in response to the rising edge of the clock signal CLK, and outputs the latched signal to the input terminal of the flip-flop 222 and the first input terminal of the logic element 223 as the signal START. The flip-flop 222 latches the signal START output from the flip-flop 221 at the rising edge of the clock signal CLK, and outputs the latched signal to the second input terminal of the logic element 223. The logic element 223 outputs a signal START_DET that is a logical product of the signal START input to the first input terminal and a signal obtained by inverting the signal input to the second input terminal.
[0021]
A signal START_DET output from the logic element 223 is input to an enable terminal en of a flip-flop with an enable function (hereinafter referred to as an enable FF) 224. The enable FF 224 is activated when the signal START_DET changes from H level to L level. Further, data DT_NEXT [31: 0] output from the XOR group 225 is input to the input terminal of the enable FF 224. The enable FF 224 outputs data DT_NOW [31: 0] to the input terminal of the XOR group 225. Also, DT_NOW [31: 0] output from the enable FF 224 is output to the outside as data (PRBS pattern) PRBS_DT [31: 0] via the buffer 226.
[0022]
The clock signal CLK is input to the clock terminals of the flip-flops 221 and 222 and the enable FF 224. The clock signal CLK is output as the clock signal PRBS_CK via the buffer 227. Further, the flip-flops 221 and 222 and the logic element 223 constitute a rise detection circuit. The rise detection circuit generates a signal START_DET that is a pulse signal that rises in response to the rise of the enable signal PRBS_EN.
With the above configuration, the PRBS pattern generation circuit 22 outputs the PRBS pattern generated by the XOR group 225 in response to the rise of the enable signal PRBS_EN.
[0023]
Further, a detailed circuit configuration example of the XOR group 225 shown in FIG. 13 will be described. FIG. 14 is a diagram showing a detailed circuit configuration example of the XOR group 225 shown in FIG. As shown in FIG. 14, the XOR group 225 includes XOR (exclusive OR) 252 to 261 and has a 32-bit input terminal 251 and an output terminal 262. When the current output data DT_NOW [31: 0] of the flip-flop 24 shown in FIG. 13 is input to the input terminal 251, the XOR group 225 generates the output data DT_NEXT [31: 0] of the next cycle. Output from the output terminal 262. Note that the connection configuration of the XORs 252 to 261 that connect the input terminal 251 and the output terminal 262 is a connection configuration that can generate a PRBS pattern. The PRBS pattern described above is a pattern that can generate an expected value of a subsequent received signal by receiving a part of the PRBS pattern on the receiving side.
[0024]
Next, the operation of the PRBS pattern generation circuit 22 shown in FIG. 13 will be briefly described. FIG. 15 is a waveform diagram for explaining the operation of the PRBS pattern generation circuit 22 shown in FIG. As shown in FIG. 15, the clock signal CLK is supplied to the PRBS pattern generation circuit 22. First, at time t41, the enable signal PRBS_EN rises. Next, at time t42, the flip-flop 221 latches the enable signal PRBS_EN in synchronization with the rising edge of the clock signal CLK, so that the signal START rises to the H level. As a result, the signal START_DET output from the logic element 223 also rises to the H level, and the enable FF 224 is deactivated.
[0025]
Next, when the clock signal CLK rises at time t43, the output of the flip-flop 222 changes to H level, and the signal START_DET that is the output of the logic element 223 falls to L level. As a result, the enable FF 224 is activated, and in synchronization with the rise of the clock signal CLK, a process of taking DT_NEXT [31: 0] and outputting it as DT_NOW [31: 0] is performed. Thereby, the buffer 226 outputs DT_NOW [31: 0] as the PRBS pattern PRBS_DT [31: 0]. As described above, the PRBS pattern generation circuit 22 generates and outputs the PRBS pattern PRBS_DT [31: 0] in synchronization with the clock signal CLK.
[0026]
Next, a conventional circuit configuration example in the pattern comparison circuit 34 shown in FIG. 11 will be described.
FIG. 16 is a diagram showing a conventional circuit configuration example in the pattern comparison circuit 34 shown in FIG. As shown in FIG. 16, the conventional pattern comparison circuit 34 includes flip-flops 341, 343, 347 to 349, a selector 342, an XOR (exclusive OR) group 344, a comparison circuit 345, and a demultiplexer 346. , A logic element 350 and a sequencer 351.
[0027]
The flip-flop 341 receives the data RX_ODT [31: 0] input from the 4:32 conversion circuit 33 at the rising edge of the clock signal RX_OCK and outputs the data as data DT [31: 0]. The selector 342 selects either the data DT [31: 0] output from the flip-flop 341 or the data DT_NEXT2 [31: 0] output from the XOR group 344 and outputs the selected data to the flip-flop 343. At this time, the selector 342 performs the above selection according to the control signal STATE_SEL from the sequencer 351.
[0028]
The flip-flop 343 outputs the data input from the selector 342 to the XOR group 344 as data DT_NOW2 [31: 0] in response to the rising edge of the clock signal RX_OCK. The XOR group 344 outputs data DT_NEXT2 [31: 0] based on DT_NOW2 [31: 0] input from the flip-flop 343. Further, data DT_NEXT2 [31; 0] output from the XOR group 344 is input to the first input terminal of the comparison circuit 345 as expected value data. Further, data DT [31: 0] output from the flip-flop 341 is input to the second input terminal of the comparison circuit 345 as reception data.
[0029]
The comparison circuit 345 compares the expected value data (data DT_NEXT2 [31: 0]) with the received data (data DT [31: 0]) and outputs a comparison result. Note that the comparison circuit 345 outputs an L level signal if they match as a comparison result, and outputs an H level signal if they do not match. The demultiplexer 346 outputs the signal input from the comparison circuit 345 to the output destination selected according to the control signal STATE_SEL output from the sequencer 351. Specifically, when the control signal STATE_SEL = L level, the flip-flop 347 is selected as the output destination, and when the control signal STATE_SEL = H level, the sequencer 351 is selected as the output destination. The flip-flop 347 receives the signal input from the comparison circuit 345 via the demultiplexer 346 at the rising edge of the clock signal RX_OCK, and outputs an error flag ERROR that is an error detection signal.
[0030]
The flip-flop 348 latches the enable signal COMP_EN input from the outside in response to the rise of the clock signal RX_OCK, and outputs the latched signal to the input terminal of the flip-flop 349 and the first input terminal of the logic element 350 as the signal START. . The flip-flop 349 latches the signal START2 output from the flip-flop 348 at the rising edge of the clock signal RX_OCK, and outputs the latched signal to the second input terminal of the logic element 350. The logic element 350 outputs a signal START_DET2 that is a logical product of the signal START2 input to the first input terminal and a signal obtained by inverting the signal input to the second input terminal.
[0031]
A signal START_DET2 output from the logic element 350 is input to the enable terminal en of the sequencer 351. The signal CMP_FLAG output from the demultiplexer 346 is input to the input terminal of the sequencer 351. In addition, the sequencer 351 outputs a control signal STATE_SEL that remains at the H level for a certain period based on the signal START_DET2.
[0032]
Note that the clock signal RX_OCK is input to the clock terminals of the flip-flops 341, 343, 347 to 349 and the sequencer 351. The circuit configuration of the XOR group 344 is the same as the detailed circuit configuration example of the XOR group 225 shown in FIG. Further, the flip-flops 348 and 349 and the logic element 350 constitute a rise detection circuit. That is, the rising edge detection circuit detects the rising edge of the enable signal COMP_EN and outputs a signal START_DET2 that is a pulse signal that rises.
With the above configuration, the pattern comparison circuit 34 compares the received data with the expected value data and outputs an error flag ERROR according to the rise of the enable signal COMP_EN.
[0033]
Next, the operation of the pattern comparison circuit 34 shown in FIG. 16 will be briefly described. FIG. 17 is a waveform diagram for explaining the operation of the pattern comparison circuit 34 shown in FIG. As shown in FIG. 17, the clock signal RX_OCK is supplied to the pattern comparison circuit 34. First, at time t51, the enable signal COMP_EN rises. Next, at time t52, the flip-flop 348 latches the enable signal COMP_EN in response to the rise of the clock signal RX_OCK, so that the signal START2 rises to the H level. As a result, the signal START_DET2 output from the logic element 350 becomes H level for one clock.
[0034]
Next, at time t53, when the H level period of the signal START_DET2 ends and falls to the L level, the sequencer 351 raises the control signal STATE_SEL to the H level. As a result, the selector 342 outputs the data DT [31: 0] output from the flip-flop 341 to the flip-flop 343. Further, the demultiplexer 346 outputs the output signal of the comparison circuit 345 to the sequencer 351 as the signal CMP_FLAG. As described above, the pattern comparison circuit 34 enters a LOCK detection state in which a proper expected value is output in the XOR group 344 based on the reception data RX_ODT [31: 0].
[0035]
Here, the LOCK detection state will be described. Generally, when pattern comparison is performed on the receiving side, it is divided into a reception data head detection (LOCK detection) state and an error detection state. The control signal STATE_SEL shown in FIG. 16 is a signal for controlling to any one of the states. Specifically, STATE_SEL = H level corresponds to the LOCK detection state, and STATE_SEL = L level corresponds to the error detection state. During the LOCK detection state, the error flag ERROR maintains the L level.
[0036]
In the LOCK detection state, the reception data DT [31: 0] is fetched into the flip-flop 343 every clock cycle, and the initial value data DT_NOW2 [31: 0] is used as the XOR group 344 so that the expected value data DT_NEXT2 [31: 0]. Is generated. The comparison circuit 345 compares the expected value data DT_NEXT2 [31: 0] generated in this way with the reception data DT [31: 0]. In the comparison circuit 345, when the comparison results coincide with each other for several cycles, it is regarded as being LOCKed (appropriate expected value has been generated), and the state shifts to an error detection state. The above-mentioned several cycles are determined by the processing of the sequencer 351. Specifically, the sequencer 351 has a function of generating an internal signal HEAD_END that is a pulse signal that rises after counting a predetermined number of cycles from the fall of the signal START_DET2. Hereinafter, the transition to the error detection state will be described with reference to FIG.
[0037]
At time t54, the sequencer 351 counts a predetermined number of cycles and raises the internal signal HEAD_END. Next, at time t55, the sequencer 351 causes the internal signal HEAD_END to fall, and the control signal STATE_SEL to fall accordingly. As described above, the pattern comparison circuit 34 enters an error detection state, and the flip-flop 347 outputs an error flag ERROR in synchronization with the clock signal from time t56.
As described above, in the mass production test, the transmission / reception function of the data transmission / reception circuit 1 is evaluated by the loop configuration in which the transmission data from the data transmission circuit 2 is directly input to the data reception circuit 3.
[0038]
As described above, in the data reception circuit 3, the clock control circuit 31 adjusts the phase of the internal clock signal RX_DCK in accordance with the difference between the phase of the reception data TXRX_DT and the phase of the internal clock signal RX_DCK. However, if there is no change such as 0 → 1 or 1 → 0 in the reception data TXRX_DT, the phase difference between the reception data TXRX_DT and the internal clock signal RX_DCK cannot be detected. Therefore, in general communication standards, the length of data that does not change is defined as 0 run length or 1 run length. That is, the length of continuous 0 (L level) data is 0 run length, and the length of continuous 1 (H level) data is 1 run length. For example, the SONET standard defines a maximum length of 72 bits as 0 run length or 1 run length. Satisfying jitter tolerance using data including 0 run length or 1 run length is essential in data transmission / reception design.
[0039]
[Patent Document 1]
JP-A-4-220045
[Patent Document 2]
JP-A-1-241945
[Patent Document 3]
JP-A-1-235437
[0040]
[Problems to be solved by the invention]
However, in the mass production test described above, the transmission / reception data TXRX_DT includes jitter corresponding to the environment in which the data transmission / reception circuit 1 will be used, and jitter corresponding to the jitter tolerance specified for the data transmission / reception circuit 1 in the design specifications. Is not included. That is, there is a problem that the jitter tolerance test is not completed.
Further, when measuring the above-described jitter tolerance characteristics, it is necessary to change the modulation frequency and modulation depth (modulation amount) of jitter applied to the clock signal in various combinations, and the measurement is performed. There was a growing demand for automation.
Further, in the above-described mass production test, there is a problem that jitter tolerance using transmission data including 0 run length or 1 run length cannot be evaluated.
[0041]
The present invention has been made in consideration of the above-described circumstances, and can test for jitter tolerance in data transmission and reception during a mass production test, and can improve the failure detection rate. Enter An object of the present invention is to provide an output interface circuit.
In addition, the present invention can automatically measure jitter tolerance characteristics in data transmission / reception. Enter An object of the present invention is to provide an output interface circuit.
In addition, the present invention can test the jitter tolerance of data transmission / reception during a mass production test even when the transmission / reception data includes 0 run length or 1 run length, and can improve the failure detection rate. Enter An object of the present invention is to provide an output interface circuit.
[0042]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems. In the input / output interface circuit according to the present invention, a clock generation means for generating a first clock signal and the first generation generated by the clock generation means Jitter supply means for including jitter in a clock signal, a data transmission circuit for transmitting data in synchronization with the first clock signal including the jitter, and a data reception circuit for receiving data, the clock generation The means further supplies a second clock signal to the data receiving circuit, and the data transmitting circuit generates a data pattern for a jitter tolerance test, and the data pattern generated by the pattern generating means. Including the jitter Transmitting means for transmitting in synchronization with the first clock signal, the data receiving circuit receiving the data pattern received from the transmitting means in synchronization with the second clock signal; Pattern comparing means for comparing the data pattern received by the receiving means with an expected value and outputting a comparison result; The pattern generation unit of the data transmission circuit further includes a function of including data in which 0 or 1 continues in the data pattern, and the pattern comparison unit in the data reception circuit has data in which the 0 or 1 continues. And a function for forcibly passing the comparison result when it is detected that the data having the continuous 0 or 1 is received by the function. It is characterized by.
[0043]
Thus, according to the present invention, Enter In the output interface circuit, jitter can be included in the clock signal supplied to the data transmission circuit, so that transmission data output from the data transmission circuit can also include jitter. Thus, it is possible to perform a jitter tolerance test by checking whether or not the data receiving circuit can properly receive the transmission data including the jitter.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the invention will be described below.
First, the overall configuration of a data transmitting / receiving circuit (input / output interface circuit) including a jitter test circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to a first embodiment of the present invention. In FIG. 1, circuits given the same reference numerals as those in FIG. 11 are circuits having the same functions and configurations, and description thereof is omitted. The data transmission / reception circuit 1a shown in FIG. 1 is different from the conventional data transmission / reception circuit 1 shown in FIG. Unlike the clock generation circuit 4 of FIG. 11, the clock generation circuit 5 can output a clock TX_CK including jitter. The data transmission circuit 2 and the clock generation circuit 5 constitute a data transmission device capable of transmitting data including jitter.
[0045]
Further, although not shown in FIG. 11, the clock control circuit 21 has a frequency divider 21a that divides the frequency into 1/2 frequency, for example, as shown in FIG. Is composed of a phase shift circuit 21b for shifting the frequency and a frequency divider 21c for dividing the frequency to 1/8. As a result, the clock signal TX_DCK of 5 GHz including the jitter input from the clock generation circuit 5 is output by the frequency divider 21a to ½ frequency (2.5 GHz). Next, the phase shift circuit 21b outputs clock signals TXDCK_A to D having four types of phases obtained by shifting the phase of the divided clock signal in units of 90 degrees. Further, the frequency divider 21c outputs a clock signal CLK having a frequency (312.5 MHz) of 1/8 of the clock signal TX_DCK.
[0046]
The clock generation circuit 5 receives various setting signals that determine the type and size of jitter included in the clock signal TX_CK and a signal TEST that is a signal for controlling whether or not to perform a jitter test. Specifically, the clock generation circuit 5 performs an operation of performing a jitter test if the signal TEST = H (high) level, and outputs the clock signal TX_CK including jitter generated according to various setting signals. If the signal TEST = L (low) level, the clock generation circuit 5 performs a normal operation and outputs a generated clock signal TX_CK that does not include jitter.
[0047]
Next, two examples of the internal configuration of the clock generation circuit 5 shown in FIG. 1 will be described below. First, an internal configuration example 1 of the clock generation circuit 5 shown in FIG. 1 will be described.
FIG. 2 is a diagram illustrating an internal configuration example 1 of the clock generation circuit 5 illustrated in FIG. 1. In the internal configuration example 1 of the clock generation circuit 5 shown in FIG. 2, those given the same reference numerals as the internal configuration of the clock generation circuit 4 shown in FIG. As shown in FIG. 2, the clock generation circuit 5 includes a phase comparator 41, a filter 42, a first VCO 43, a frequency divider 44, and buffers 45 and 46 that have the same configuration as the conventional clock generation circuit 4. In order to include jitter in the clock signal TX_CK, a jitter generation circuit 51, a voltage adder 52, a second VCO 53, and a selector 54 are further provided. The first VCO 43 in FIG. 2 has the same name as the VCO 43 in FIG. 12 but is different from the second VCO 53 in name.
[0048]
The various setting signals described above are input to the input terminal of the jitter generation circuit 51 described above. The output terminal of the jitter generation circuit 51 is connected to the first input terminal of the voltage adder 52. The second input terminal of the voltage adder 52 is connected to an interconnection point between the output terminal of the filter 42 and the input terminal of the first VCO 43. The output terminal of the voltage adder 52 is connected to the input terminal of the second VCO 53. The output terminal of the second VCO 53 is connected to the first input terminal of the selector 54, and the output terminal of the first VCO 43 is connected to the second input terminal of the selector 54. A signal TEST is input to the control terminal of the selector 54. The output terminal of the selector 54 is connected to the input terminal of the buffer 45.
[0049]
Next, a clock generation process including jitter in the clock generation circuit 5 shown in FIG. 2 will be described.
The jitter generation circuit 51 in FIG. 2 outputs, for example, a control voltage that becomes a jitter of a sine wave pattern or a random pattern according to various setting signals. Specifically, this control voltage changes according to the period and amplitude of the sine wave pattern given by various setting signals and the maximum amplitude of the random pattern. The voltage adder 52 outputs a voltage obtained by adding the output voltage of the filter 42 and the control voltage (jitter component) output from the jitter generation circuit 51. The second VCO 53 outputs a clock signal CK1 having a frequency (5 GHz ± jitter) corresponding to the voltage including the jitter component output from the voltage adder 52. That is, the second VCO 53 changes the frequency of the output clock signal in accordance with the sum of the control voltage output from the jitter generation circuit 51 and the output voltage of the filter 42 in the loop including the first VCO 43.
[0050]
The selector 54 selects and outputs the clock signal CK1 including jitter when the signal TEST = H level, and selects and outputs the clock signal CK not including jitter when the signal TEST = L level. . As described above, when the signal TEST = H level, the clock generation circuit 5 outputs the clock signal CK1 including the jitter output from the second VCO 53 as the clock signal TX_CK. Thereby, the clock control circuit 21 shown in FIG. 1 outputs a clock signal obtained by dividing the clock signal TX_CK including jitter. That is, the PRBS pattern generation circuit 22 in the data transmission / reception circuit 1a operates in synchronization with the clock signal including jitter. The 32: 4 conversion circuit 25 and the driver circuit 26 convert the parallel data PRBS_DT [31: 0] output from the PRBS pattern generation circuit 22 into serial data using a clock signal including jitter.
[0051]
As described above, the data transmission circuit 2 can output transmission data TXRX_DT including jitter. Thereby, the data receiving circuit 3 receives the transmission data TXRX_DT including this jitter. Here, it is possible to perform a jitter tolerance test by detecting whether the data reception circuit 3 has properly received the transmission data TXRX_DT including jitter.
[0052]
Next, an internal configuration example 2 of the clock generation circuit 5 shown in FIG. 1 will be described.
FIG. 3 is a diagram illustrating an internal configuration example 2 of the clock generation circuit 5 illustrated in FIG. 1. In the internal configuration example 2 of the clock generation circuit 5 shown in FIG. 3, those given the same reference numerals as the internal configuration of the clock generation circuit 4 shown in FIG. As shown in FIG. 3, the clock generation circuit 5 includes a clock signal in addition to a phase comparator 41, a filter 42, a VCO 43, a frequency divider 44, and buffers 45 and 46 that have the same configuration as the conventional clock generation circuit 4. In order to include jitter in TX_CK, a jitter generation circuit 51, a selector 54, and a DLL (Delay Locked Loop) 55 are further provided. The jitter generation circuit 51 and the selector 54 have the same functions as those shown in FIG.
[0053]
The various setting signals described above are input to the input terminal of the jitter generation circuit 51 described above. The output terminal of the jitter generation circuit 51 is connected to the control voltage input terminal of the DLL 55. The clock signal input terminal of the DLL 55 is connected to the output terminal of the VCO 43. The output terminal of the DLL 55 is connected to the first input terminal of the selector 54, and the output terminal of the VCO 43 is connected to the second input terminal of the selector 54. A signal TEST is input to the control terminal of the selector 54. The output terminal of the selector 54 is connected to the input terminal of the buffer 45.
[0054]
Next, a clock generation process including jitter in the clock generation circuit 5 shown in FIG. 3 will be described.
The jitter generation circuit 51 in FIG. 3 outputs, for example, a control voltage that becomes a jitter of a sine wave pattern or a random pattern according to various setting signals. The DLL 55 changes the frequency of the clock signal input from the VCO 43 by changing the internal delay amount according to the control voltage output from the jitter generation circuit 51, and outputs the clock signal CK2. That is, the DLL 55 outputs a clock signal CK2 having a frequency (5 GHz ± jitter) including a jitter component corresponding to the control voltage output from the jitter generation circuit 51.
[0055]
The selector 54 selects and outputs the clock signal CK2 including jitter when the signal TEST = H level, and selects and outputs the clock signal CK not including jitter when the signal TEST = L level. . As described above, when the signal TEST = H level, the clock generation circuit 5 outputs the clock signal CK2 including the jitter output from the DLL 55 as the clock signal TX_CK. As described above, as described in the case of FIG. 2, the data transmission circuit 2 in the data transmission / reception circuit 1a illustrated in FIG. 1 can output transmission data TXRX_DT including jitter. Thereby, it is possible to test the jitter tolerance in the data transmission / reception circuit 1a by detecting whether the data reception circuit 3 has properly received the transmission data TXRX_DT including jitter.
[0056]
Next, as a second embodiment of the present invention, the clock generation circuit 5 described above is provided, and the measurement time of the transmission / reception test including jitter, the modulation depth (modulation amount) and frequency of jitter are automatically changed. A data transmission / reception circuit that can measure multiple times will be described. A graph showing the characteristics of jitter tolerance can be generated from the measurement data obtained by the plurality of measurements. However, the measurement to such an extent that a graph showing the characteristics of jitter tolerance can be generated not at the time of mass production testing but at the prototype stage or the characteristic evaluation stage of the data transmission / reception circuit. Based on this jitter tolerance characteristic, the modulation frequency and modulation depth of the jitter to be given to the clock signal during the mass production test are determined. In addition, due to time constraints during mass production testing, it is rare to change the jitter modulation frequency and modulation depth for testing, and usually the jitter tolerance characteristic is the most marginal with respect to the jitter tolerance standard. Measure only the part with no mark.
[0057]
Here, the modulation frequency of the jitter and the modulation depth will be further described.
When the frequency of the clock signal TX_CK not including jitter is fc, the frequency fc ′ of the clock signal TX_CK including jitter is expressed by the following equation.
fc ′ = fc {1 + δ × cos (2π × fm × t)}
Where δ: modulation depth, fm: modulation frequency, t: time variable
[0058]
FIG. 4 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to the second embodiment of the present invention. In FIG. 4, circuits given the same reference numerals as those in FIG. 11 are circuits having similar functions and configurations, and description thereof is omitted. 4 is different from the data transmission / reception circuit 1 shown in FIG. 11 in that the data transmission / reception circuit 1b includes a data reception circuit 3a, a clock generation circuit 5, and a clock generation circuit control circuit 6.
[0059]
Here, the data receiving circuit 3a is different from the data receiving circuit 3 shown in FIG. 11 in that it has a measurement time counting circuit 36, and the other configurations are the same. 4 has the same configuration as that of the clock generation circuit 5 shown in FIG. That is, the internal configuration of the clock generation circuit 5 of FIG. 4 may be the configuration shown in FIG. 2 or the configuration shown in FIG. Further, the clock generation circuit control circuit 6 receives the clock signal RX_OCK, the signal OK_FLAG and the signal NG_FLAG that are signals indicating the test results from the data reception circuit 3a. The clock generation circuit control circuit 6 receives various setting data from the outside. The clock generation circuit control circuit 6 outputs various setting signals controlled based on the received plurality of signals and data to the clock generation circuit 5.
[0060]
Next, the measurement time counting circuit 36 of the data receiving circuit 3a will be described. The measurement time count circuit 36 includes an input terminal to which the clock signal RX_OCK output from the 4:32 conversion circuit 33 is input. The measurement time count circuit 36 includes an input terminal to which an error flag ERROR output from the pattern comparison circuit 34 is input. The measurement time count circuit 36 includes an input terminal to which an enable signal COMP_EN that is a signal input from the outside and a measurement time setting signal MEAS_TIME are input. The measurement time count circuit 36 outputs a reset signal COMP_RST to the pattern comparison circuit 34 and outputs a signal OK_FLAG and a signal NG_FLAG to the clock generation circuit control circuit 6.
[0061]
The measurement time counting circuit 36 described above is a circuit for defining the jitter tolerance evaluation time, and the time can be changed from the outside by a measurement time setting signal MEAS_TIME. The reason for providing the measurement time counting circuit 36 is that, in order to evaluate the jitter tolerance, the data TXRX_DT including the sine wave jitter having a certain modulation frequency and a certain modulation depth is received only for a time corresponding to the specified time. This is because a mechanism is necessary. The reset signal COMP_RST output from the measurement time counting circuit 36 is not shown in FIG. 16, but is input to the sequencer 351 in FIG. 16, for example, to reset the sequencer 351 to the initial state (STATE_SEL = H state). To do.
[0062]
In addition, the measurement time count circuit 36 detects whether or not the error flag ERROR = H level output from the pattern comparison circuit 34 during the time set by the measurement time setting signal MEAS_TIME (hereinafter referred to as setting time). To do. Specifically, if the measurement time count circuit 36 does not detect the error flag ERROR = H level within the set time, the data reception circuit 3a has correctly received the data TXRX_DT including sine wave jitter. Determination is made and the signal OK_FLAG = H level is output. On the other hand, when the error flag ERROR = H level is detected within the set time, the measurement time count circuit 36 outputs a signal NG_FLAG = H level.
[0063]
As a result, when the signal OK_FLAG = H level, the clock generation circuit control circuit 6 outputs various setting signals for instructing the clock generation circuit 5 to change the depth of jitter modulation. Further, when the signal NG_FLAG = H level, the clock generation circuit control circuit 6 outputs various setting signals for instructing the clock generation circuit 5 to change the modulation frequency of jitter. That is, the clock generation circuit control circuit 6 outputs various setting signals according to various setting data from the outside, the signal OK_FLAG, and the signal NG_FLAG.
[0064]
Specifically, the clock generation circuit control circuit 6 receives data MF_INIT, data MF_STEP, data MD_INIT, data MD_STEP, data MEAS_STOP_MF, and data JT_START as various setting data. Data MF_INIT is an initial value of the modulation frequency of jitter in jitter tolerance measurement. Data MF_STEP is a value indicating a modulation frequency change step to be changed when signal NG_FLAG = H level. Data MD_INIT is an initial value of the modulation depth in jitter. The data MD_STEP is a value indicating a modulation depth changing step to be changed when the signal OK_FLAG = H level. Data MEAS_STOP_MF sets a modulation frequency at which measurement ends (measurement end modulation frequency). Data JT_START instructs the start of measurement. Each setting data described above can be changed.
[0065]
As described above, the clock generation circuit control circuit 6 outputs various setting signals in accordance with the above-described settings, thereby changing the circuit parameters of the jitter generation circuit 51 in the clock generation circuit 5, and the jitter included in the transmission / reception data TXRX_DT. Change the amount. Further, when the measurement is completed, the clock generation circuit control circuit 6 outputs a signal MEAS_END indicating the end of the measurement to the outside of the data transmission / reception circuit 1b.
[0066]
Further, when detecting the signal NG_FLAG = H level, the clock generation circuit control circuit 6 stores, for example, an internal code indicating a modulation frequency and a modulation depth of jitter. As a result, the data transmitting / receiving circuit 1b can automatically generate a graph showing the jitter tolerance characteristics. That is, the jitter tolerance of the data transmission / reception circuit 1b can be evaluated.
[0067]
Next, an operation in which the data transmitting / receiving circuit 1b shown in FIG. 4 measures the jitter tolerance characteristics will be described.
FIG. 5 is a diagram illustrating an operation in which the data transmitting / receiving circuit 1b illustrated in FIG. 4 measures the jitter tolerance characteristics. As shown in FIG. 5, first, in step S1, the clock generation circuit 5 of the data transmission / reception circuit 1b is activated by the instruction of the data JT_START to set the signal TEST = H level. Thereby, the clock generation circuit 5 starts outputting the clock signal TX_CK including jitter. Then, after a sufficient time has elapsed to stabilize the operation of the PLL in the clock generation circuit 5, the process proceeds to the next step S2.
[0068]
Next, in step S2, the data transmission circuit 2 and the data reception circuit 3a are activated to start operations synchronized with the clock signals TX_CK and RX_CK, respectively. Also, PRBS_EN = H level. Next, in step S3, the data transmission circuit 2 processes the PRBS pattern data PRBS_DT [31: 0] generated by the PRBS pattern generation circuit 22 with a clock signal including jitter, thereby transmitting / receiving transmission / reception data TXRX_DT including jitter. Generate and output. At this time, the clock generation circuit 5 that receives various setting signals according to the settings of various setting data from the clock generation circuit control circuit 6 has a jitter that becomes a modulation frequency and a modulation depth according to the received various setting signals. It is included in the clock signal TX_CK.
[0069]
Next, in step S4, the data reception circuit 3a receives the transmission / reception data TXRX_DT including the jitter, and compares the expected value with the pattern comparison circuit 34 to start measurement of the reception state. At this time, the enable signal COMP_EN = H level, and the measurement time is determined by setting the measurement time setting signal MEAS_TIME. Further, as described with reference to FIG. 17, the pattern comparison circuit 34 enters the error detection state (measurement start) after the LOCK detection state.
[0070]
Next, in step S5, the clock generation circuit control circuit 6 detects whether or not the signal NG_FLAG = H level. If the signal NG_FLAG = H level is not detected (No in step S5), the process proceeds to step S6, where the clock generation circuit control circuit 6 ends the measurement time and the signal OK_FLAG = H level. Whether or not is detected. When the signal NG_FLAG = H level is detected (Yes in step S5), the clock generation circuit control circuit 6 proceeds to step S9. Step S9 will be described later.
[0071]
In step S6, when the measurement time is over and it is not detected that the signal OK_FLAG = H level (No in step S6), the process returns to step S5, and the data reception circuit 3a performs the measurement process of the reception state. Continuously, the clock generation circuit control circuit 6 detects whether or not the signal NG_FLAG = H level. If it is detected in step S6 that the measurement time has ended and the signal OK_FLAG = H level (Yes in step S6), the process proceeds to step S7, where the clock generation circuit control circuit 6 provides the jitter. Change the modulation depth. Next, proceeding to step S8, the data receiving circuit 3a initializes the measurement time counting circuit 36 and the pattern comparison circuit 34, and returns to step S5.
[0072]
The change of the modulation depth in step S7 described above (in this embodiment, the modulation depth is changed so as to increase gradually) is performed until the signal NG_FLAG = H level is detected in step S5. Thereby, the maximum modulation depth at a certain modulation frequency can be obtained.
[0073]
Next, when the signal NG_FLAG = H level is detected in step S5 (Yes in step S5), the clock generation circuit control circuit 6 proceeds to step S9, and the clock generation circuit control circuit 6 provides the jitter at that time. The modulation frequency and modulation depth values thus encoded are internally encoded and stored. Next, proceeding to step S10, the clock generation circuit control circuit 6 detects whether or not the modulation frequency stored in step S9 is the same as the measurement end modulation frequency set in the data MEAS_STOP_MF.
[0074]
If the modulation frequency stored in step S9 is the same as the measurement end modulation frequency (No in step S10), the data transmission / reception circuit 1b ends the jitter tolerance characteristic measurement process. When the modulation frequency stored in step S9 is different from the measurement end modulation frequency (Yes in step S10), the process proceeds to step S11, and the clock generation circuit control circuit 6 changes the modulation frequency and proceeds to step S8. Note that the change of the modulation frequency in step S11 starts from an initial value determined by the data MF_INIT and is changed by a step width corresponding to the data MF_STEP. Further, the jitter tolerance at each modulation frequency is measured by changing the modulation frequency in step S11.
[0075]
Through the above processing, the data transmitting / receiving circuit 1b can output the stored modulation frequency and modulation depth. As a result, a graph plotting changes in each modulation frequency and modulation depth can be generated, and the characteristics of jitter tolerance can be shown. Further, if the data transmission / reception circuit 1b according to the present embodiment is used, it is possible to evaluate the jitter tolerance characteristics while using a conventional mass production test system.
[0076]
Next, a data transmission / reception circuit capable of performing a transmission / reception test using transmission / reception data including 0 run length or 1 run length will be described as a third embodiment of the present invention. FIG. 6 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to the third embodiment of the present invention. In FIG. 6, circuits given the same reference numerals as those in FIG. 11 are circuits having the same functions and configurations, and the description thereof is omitted. 6 differs from the data transmission / reception circuit 1 shown in FIG. 11 in that the data transmission / reception circuit 1c includes a data transmission circuit 2c, a data reception circuit 3c, and a clock generation circuit 5.
[0077]
Here, the data transmission circuit 2c in FIG. 6 is different from the data transmission circuit 2 shown in FIG. 11 in that it has a PRBS pattern generation circuit 22a, and the other configurations are the same. Further, the data receiving circuit 3c of FIG. 6 is different from the data receiving circuit 3 shown in FIG. 11 in that it has a pattern comparison circuit 34a, and the other configurations are the same. Further, the clock generation circuit 5 in FIG. 6 has the same configuration as the clock generation circuit 5 shown in FIG. That is, the internal configuration of the clock generation circuit 5 of FIG. 6 may be the configuration shown in FIG. 2 or the configuration shown in FIG.
[0078]
The PRBS pattern generation circuit 22a described above generates a PRBS pattern including 0 run length or 1 run length. Thereby, the data transmission circuit 2c can output the transmission / reception data TXRX_DT including 0 run length or 1 run length. Further, the PRBS pattern generation circuit 22a sets a period for replacing a part of transmission / reception data with 0 run length or 1 run length according to external data CYCLE [15: 0]. Further, the PRBS pattern generation circuit 22a sets the length of 0 run length or 1 run length according to the external data LENGTH [3: 0].
[0079]
As a method for the PRBS pattern generation circuit 22a to generate a PRBS pattern including 0 run length or 1 run length, a method in which 0 run length or 1 run length is replaced with a part of the PRBS pattern, 0 run length or 1 run It is preferable to use a method of inserting a length in the middle of a PRBS pattern.
[0080]
The pattern comparison circuit 34a described above has a function of detecting 0 run length or 1 run length included in the received data. Specifically, the pattern comparison circuit 34a detects that all received data (RXO_DT [31: 0]) is at the L level or the H level. The pattern comparison circuit 34a has a function of forcibly setting the error flag ERROR to the L level when 0 run length or 1 run length is detected. As a result, the data reception circuit 3c can output an appropriate error flag ERROR even when the transmission / reception data TXRX_DT including 0 run length or 1 run length is received.
[0081]
With the above configuration, the data transmission / reception circuit 1c can perform a transmission / reception test of transmission / reception data TXRX_DT including 0 run length or 1 run length and jitter.
[0082]
Next, an internal configuration example of the PRBS pattern generation circuit 22a shown in FIG. 6 will be described.
FIG. 7 is a diagram illustrating an internal configuration example of the PRBS pattern generation circuit 22a illustrated in FIG. In the PRBS pattern generation circuit 22a of FIG. 7, those given the same reference numerals as the internal configuration example of the conventional PRBS pattern generation circuit 22 shown in FIG. In the PRBS pattern generation circuit 22a of FIG. 7, the clock signal line for transmitting the clock signal CLK is omitted, but in the circuit of FIG. 7, the clock signal CLK has a clock terminal as in FIG. It is supplied to each circuit element.
[0083]
In FIG. 7, as a configuration different from that in FIG. 13, the PRBS pattern generation circuit 22 a is configured to set a period for replacing part of transmission / reception data with 0 run length or 1 run length according to external data CYCLE [15: 0]. Includes logic elements 61, 62, 66 and 67, a counter A63, a comparison circuit 64, a flip-flop 65, an input inversion flip-flop with enable (hereinafter simply referred to as enable inversion FF) 73, and a selector 74. It comprises. Further, in order to set the length of 0 run length or 1 run length in accordance with the external data LENGTH [3: 0], the PRBS pattern generation circuit 22a includes a counter B · 68, a comparison circuit 69, and a flip-flop. 70 and logic elements 71 and 72.
[0084]
As shown in FIG. 7, the logic element 61 outputs the logical sum of the signal START_DET output from the logic element 223 and the signal LENGTH_CNT_LOAD output from the logic element 66 to the load terminal load of the counter A · 63. Further, the logic element 62 outputs a logical product of the output signal of the comparison circuit 64 and a signal obtained by inverting the output signal of the logic element 72 as a signal CYCLE_CNT_EN.
[0085]
Further, the counter A · 63 has an input terminal for loading (loading a value) data CYCLE [15: 0] from the outside, and a load terminal load to which a signal instructing the timing for loading data is input from the logic element 61. And an enable terminal en that is activated when the signal CYCLE_CNT_EN = H level input from the logic element 62 and deactivated when the signal CYCLE_CNT_EN = L level, and a clock terminal that receives a clock signal. Further, the counter A · 63 outputs the data CYCLE_CNT [15: 0] counted down in synchronization with the rising edge of the clock signal CLK with the loaded data CYCLE [15: 0] as an initial value.
[0086]
The comparison circuit 64 compares the data CYCLE_CNT [15: 0] output from the counter A • 63 with all L data [15: 0], which is all 16 bits L level, and if they are different, sets the H level. If the same, output L level. The output signal of the comparison circuit 64 is input to the input terminals of the logic element 62 and the flip-flop 65 and the inverting input terminal of the logic element 66. The flip-flop 65 outputs the output signal of the comparison circuit 64 to the input terminal of the logic element 66 in synchronization with the rising edge of the clock signal CLK.
[0087]
The logic element 66 outputs a logical product of a signal obtained by inverting the signal input from the comparison circuit 64 to the inverting input terminal and a signal input from the flip-flop 65 to the input terminal as a signal LENGTH_CNT_LOAD. The signal LENGTH_CNT_LOAD output from the logic element 66 is input to the input terminals of the logic elements 61 and 67 and the load terminal load of the counter B · 68. The flip-flop 65 and the logic element 66 constitute a falling detection circuit.
[0088]
The logic element 67 outputs a logical sum of the signal LENGTH_CNT_LOAD output from the logic element 66 and the signal CYCLE_CNT_EN output from the logic element 62 as the signal DT_SEL. A signal DT_SEL output from the logic element 67 is input to the control terminal of the selector 74 and controls the selector 74.
[0089]
The counter B · 68 has an input terminal for loading (loading a value) data LENGTH [3: 0] from the outside, and a load terminal load to which a signal LENGTH_CNT_LOAD instructing the data loading timing is input from the logic element 66. , An enable terminal en that is activated when the signal input from the comparison circuit 60 = H level and deactivated when the signal = L level, and a clock terminal that receives a clock signal. The counter B · 68 outputs the data LENGTH_CNT [3: 0] counted down in synchronization with the rising edge of the clock signal CLK, with the loaded data LENGTH [3: 0] as an initial value.
[0090]
Further, the comparison circuit 69 compares the data LENGTH_CNT [3: 0] output from the counter B · 68 with the all L data [3: 0] in which all 4 bits are at the L level, and if different, the signal LENGTH_CNT_EN = The H level is output, and if the same, the signal LENGTH_CNT_EN = L level is output. The signal LENGTH_CNT_EN output from the comparison circuit 69 is input to the input terminals of the logic element 72 and the flip-flop 70, the inverting input terminal of the logic element 71, and the enable terminal en of the counter B · 68. The flip-flop 70 outputs the signal LENGTH_CNT_EN output from the comparison circuit 69 to the input terminal of the logic element 71 in synchronization with the rising edge of the clock signal CLK.
[0091]
Further, the logic element 71 receives the logical product of the signal obtained by inverting the signal LENGTH_CNT_EN input to the inverting input terminal from the comparison circuit 69 and the signal input to the input terminal from the flip-flop 70 as the signal LENGTH_CNT_END, and is input to the logic element 72. Output to the terminal. The logic element 72 outputs the logical sum of the signal LENGTH_CNT_END and the signal LENGTH_CNT_EN to the inverting input terminal of the logic element 62 and the enable terminal en of the enable inverting FF 73. The flip-flop 70 and the logic element 71 constitute a falling detection circuit.
[0092]
The enable inversion FF 73 has an inverting input terminal to which a signal output from its own output terminal is input, an enable terminal en to which a signal output from the logic element 72 is input, and a clock to which a clock signal CLK is input. Terminal. The enable inversion FF 73 inverts the signal input to the inversion input terminal in synchronization with the rising edge of the clock signal CLK and outputs the inverted signal to the second input terminal of the selector 74. The input signal and output signal of the enable inversion FF 73 have a bit width of 32 bits. That is, when the output of the enable inversion FF 73 is converted to serial data, 0 run or 1 run that is 32 bits continuous can be alternately output.
[0093]
The selector 74 has a first input terminal to which data DT_NOW [31: 0] output from the enable flip-flop 224 is input, a second input terminal to which the output of the enable inversion FF · 73 is input, And a control terminal to which a signal DT_SEL output from the logic element 67 is input. The selector 74 outputs a signal selected from the output terminal according to the signal DT_SEL to the input terminal of the flip-flop 75. As a result, the flip-flop 75 outputs the signal output from the selector 74 as data PRBS_DT [31: 0] in synchronization with the rising edge of the clock signal CLK. The selector 74 selects and outputs the data DT_NOW [31: 0] output from the enable flip-flop 224 when the signal DT_SEL = H level. When the signal DT_SEL = L level, the selector 74 selects the enable inversion FF · The output 73 is selected and output.
[0094]
Next, the operation of the PRBS pattern generation circuit 22a shown in FIG. 7 will be described. FIG. 8 is a waveform diagram showing the operation of the PRBS pattern generation circuit 22a shown in FIG. As shown in FIG. 8, the enable signal PRBS_EN from the outside rises at time t1. Next, when the clock signal CLK rises at time t2, the flip-flop 221 latches the enable signal PRBS_EN in response to the rise of the clock signal CLK, so that the signal START = H level. As a result, the signal START_DET output from the logic element 223 rises to the H level, and the output signal of the logic element 61 also rises to the H level.
[0095]
Next, when the clock signal CLK rises at time 3, the signal START_DET output from the logic element 223 falls to the L level, and the output signal of the logic element 61 also falls to the L level. As a result, the data CYCLE [15: 0] input to the counter A · 63 is fetched as the initial value of the countdown, and the value is output as data CYCLE_CNT [15: 0]. In this embodiment, the initial value is 127 as shown in FIG.
[0096]
As a result, the output of the comparison circuit 64 rises to the H level, and the signal CYCLE_CNT_EN output from the logic element 62 also rises to the H level. As a result, the signal DT_SEL output from the logic element 67 also rises to the H level. As described above, the selector 74 selects and outputs the data DT_NOW [31: 0], which is a PRBS pattern generated by the configuration of the flip-flop 224 with enable and the XOR group 225. That is, at time t4, the PRBS pattern generation circuit 22a outputs the generated data DT_NOW [31: 0] as data PRBS_DT [31: 0]. Thereafter, during a period until the data CYCLE_CNT [15: 0] = 0 by the countdown of the counter A · 63, the PRBS pattern generation circuit 22a sets the generated data DT_NOW [31: 0] as data PRBS_DT [31: 0]. Output.
[0097]
Next, when the data CYCLE_CNT [15: 0] = 0 output from the counter A • 63 at time 5, the signal output from the comparison circuit 64 falls to the L level, and the signal output from the logic element 62 CYCLE_CNT_EN also falls to the L level. As a result, the signal LENGTH_CNT_LOAD output from the logic element 66 rises to the H level.
[0098]
Next, when the clock signal CLK rises at time t6, the signal LENGTH_CNT_LOAD output from the logic element 66 falls to the L level. As a result, the output signal DT_SEL of the logic element 67 also falls to the L level, and the selector 74 selects and outputs the output data [31: 0] of the enable inversion FF · 73. Further, the output signal of the logic element 62 also falls to the L level, and the data CYCLE [15: 0] input to the counter A · 63 is fetched as the initial value of the countdown, and the value is the data CYCLE_CNT [15: 0]. Is output as
[0099]
Further, the data LENGTH [3: 0] input to the counter B · 68 is taken in as an initial countdown value, and the value is output as data LENGTH_CNT [3: 0]. As a result, the signal LENGTH_CNT_EN output from the comparison circuit 69 rises to H level, and the output signal of the logic element 72 also rises to H level. As a result, the enable inversion FF 73 is activated and outputs 0-run length or 1-run length output data [31: 0]. Note that the initial value specified by the data LENGTH [3: 0] in this embodiment is LENGTH [3: 0] = 2 as shown in FIG.
[0100]
As described above, at time t7, the PRBS pattern generation circuit 22a outputs the output data [31: 0], which is 0 run length or 1 run length, generated by the enable inversion FF 73 as data PRBS_DT [31: 0]. . Thereafter, during a period until the data LENGTH_CNT [3: 0] = 0 due to the countdown of the counter B • 68, the PRBS pattern generation circuit 22a converts the data [31: 0] generated by the enable inversion FF • 73 into the data PRBS_DT [ 31: 0]. Thereby, as indicated by the symbol RUN in FIG. 8, a part of the PRBS pattern can be replaced with 0 run length or 1 run length.
[0101]
Further, when the data LENGTH_CNT [3: 0] = 0 at time t8, the signal LENGTH_CNT_EN output from the comparison circuit 69 falls to the L level. As a result, the signal LENGTH_CNT_END output from the logic element 71 rises to the H level.
[0102]
Next, at time t9, the signal LENGTH_CNT_END output from the logic element 71 falls to the L level, and the output of the logic element 72 also falls to the L level. As a result, the signal CYCLE_CNT_EN output from the logic element 62 rises to H level, and the signal DT_SEL output from the logic element 67 also rises to H level. As described above, the selector 74 selects and outputs the data DT_NOW [31: 0] which is a PRBS pattern again. In the counters A and 63, the signal CYCLE_CNT_EN input to the enable terminal en rises to the H level, so that the countdown process is started. Next, at time t10, the flip-flop 75 starts outputting data PRBS_DT [31: 0], which is a PRBS pattern, in response to the rising edge of the clock signal CLK. Further, the counter A · 63 performs a count-down process for the data CYCLE_CNT [15: 0].
[0103]
As described above, the PRBS pattern generation circuit 22a applies the PRBS pattern to the PRBS pattern according to the combination of the output CYCLE_CNT [15: 0] of the counter A · 63 and the output LENGTH_CNT [3: 0] of the counter B · 68. A signal DT_SEL that defines the timing for replacing the 0 run length or the 1 run length is generated. Further, the PRBS pattern generation circuit 22a may set LENGTH [3: 0] = 0 when it is not desired to include 0 run length or 1 run length in transmission data that is a PRBS pattern.
[0104]
Next, an internal configuration example of the pattern comparison circuit 34a shown in FIG. 6 will be described. FIG. 9 is a diagram showing an internal configuration example of the pattern comparison circuit 34a shown in FIG. In the pattern comparison circuit 34a of FIG. 9, those having the same reference numerals as the internal configuration example of the conventional pattern comparison circuit 34 shown in FIG. In the pattern comparison circuit 34a shown in FIG. 9, the clock signal line for transmitting the clock signal RX_OCK is omitted. However, like the pattern comparison circuit 34 shown in FIG. 16, the clock signal RX_OCK has a clock terminal (FIG. 9). Is supplied to each circuit element having a middle triangle).
[0105]
Further, as a function different from the pattern comparison circuit 34 shown in FIG. 16, the pattern comparison circuit 34a shown in FIG. 9 detects 0 run length or 1 run length from received data, and sets an error flag ERROR corresponding to the received data. It has a function of masking (hiding). That is, the pattern comparison circuit 34a shown in FIG. 9 detects that all received data (data DT [31: 0] in FIG. 9) is 0 or 1 as a configuration different from the pattern comparison circuit 34 shown in FIG. The configuration includes a 0/1 detection circuit 81, flip-flops 82 and 84, and logic elements 83 and 85. The pattern comparison circuit 34a further includes a selector 86 and a flip-flop 87 in order to mask the error flag ERROR (forcibly setting the error flag to a low level) when receiving 0 run length and 1 run length. .
[0106]
In FIG. 9, a 0/1 detection circuit 81 detects that all received data (data DT [31: 0] in FIG. 9) is 0 or 1, and outputs a detection signal RUN_DET (H level when detected). To do. The flip-flop 82 outputs the detection signal RUN_DET input from the 0/1 detection circuit 81 in response to the rising edge of the clock signal RX_OCK. The logic element 83 outputs, as an output signal RUN_END, a logical product of the output signal of the flip-flop 82 inputted to the input terminal and the signal obtained by inverting the detection signal RUN_DET inputted from the 0/1 detection circuit 81 to the inverting input terminal. To do.
[0107]
The flip-flop 84 outputs a signal RUN_END_DLY obtained by delaying the signal RUN_END input from the logic element 83 by one clock in response to the rising edge of the clock signal RX_OCK. The logic element 85 outputs a signal ERROR_SEL that is a logical sum of the detection signal RUN_DET input from the 0/1 detection circuit 81, the signal RUN_END input from the logic element 83, and the signal RUN_END_DLY input from the flip-flop 84. To do. With the above configuration, the pattern comparison circuit 34a detects 0 run length or 1 run length from the received data, and outputs a signal ERROR_SEL that is widened by 1 clock before and after the detected period.
[0108]
Next, the selector 86 selects the signal IN_ERROR_DLY output from the flip-flop 347 and outputs it to the flip-flop 87 if the signal ERROR_SEL = L level (0 or 1 run is not detected) output from the logic element 85. The selector 86 selects a signal fixed at 0 (fixed at L level) and outputs it to the flip-flop 87 if the signal ERROR_SEL = H level (detection of 0 or 1 run) output from the logic element 85. The flip-flop 87 outputs the signal input from the selector 86 as an error flag ERROR in synchronization with the clock signal RX_OCK.
[0109]
With the configuration described above, in addition to the function of generating the expected value of the conventional PRBS pattern and comparing it with the received data, the pattern comparison circuit 34a has the function of detecting 0 run length and 1 run length, And a function of forcibly fixing the error flag ERROR to the L level when one run length is detected.
[0110]
Next, the operation of the pattern comparison circuit 34a shown in FIG. 9 will be described. FIG. 10 is a waveform diagram showing an operation of the pattern comparison circuit 34a shown in FIG. As shown in FIG. 10, when reception data DT [31: 0] including 0 run length or 1 run length is received at time t21, the comparison circuit 345 outputs the data because it differs from the expected value data corresponding to the PRBS pattern. Raise signal to H level. As a result, the signal IN_ERROR output from the demultiplexer 346 rises to the H level.
[0111]
Next, at time t22, the flip-flop 347 takes in the signal IN_ERROR output from the demultiplexer 346 in synchronization with the rise of the clock signal RX_OCK, and raises the signal IN_ERROR_DLY to the H level. Further, the 0/1 detection circuit 81 detects 0 run length or 1 run length for the received data DT [31: 0], and raises the detection signal RUN_DET to the H level. As a result, the signal ERROR_SEL output from the logic element 85 rises to the H level.
[0112]
Next, at time t23, the 0/1 detection circuit 81 detects the end of 0 run length or 1 run length in the received data DT [31: 0], and lowers the detection signal RUN_DET to the L level. Further, the logic element 83 raises the signal RUN_END obtained by delaying the signal RUN_DET by one clock in the flip-flop 82 to the H level. Thereby, the signal ERROR_SEL output from the logic element 85 is maintained at the H level. Note that the flip-flop 82 and the logic element 83 detect the falling edge of the signal RUN_DET.
[0113]
Next, at time 24, the logic element 83 causes the flip-flop 82 to delay the signal RUN_DET obtained by delaying the signal RUN_DET by one clock to the L level. Further, the flip-flop 84 raises the signal RUN_END_DLY obtained by delaying the signal RUN_END by one clock to the H level. Thereby, the signal ERROR_SEL output from the logic element 85 is maintained at the H level. Also, the reception data DT [31: 0] corresponding to the PRBS pattern not including 0 run length or 1 run length is received, and the comparison circuit 345 compares the output signal with the expected value data corresponding to the PRBS pattern. Fall to the level. As a result, the signal IN_ERROR output from the demultiplexer 346 falls to the L level.
[0114]
Next, at time t25, the flip-flop 84 causes the signal RUN_END_DLY obtained by delaying the signal RUN_END by one clock to fall to the L level. As a result, the signal ERROR_SEL output from the logic element 85 falls to the L level. Further, the signal IN_ERROR_DLY obtained by delaying the signal IN_ERROR output from the flip-flop 347 by one clock falls.
[0115]
As described above, during the period of the signal IN_ERROR_DLY = H level (ERROR output mask period) in which 0 run length or 1 run length is detected as an error, the error flag ERROR is forced by setting the signal ERROR_SEL to the H level. Can be set to L level.
[0116]
Here, the features of the present embodiment will be further described. Generally, as described above, the pattern comparison sequence is divided into a data head detection (Lock detection) state and an error detection state. The signal STATE_SEL in FIGS. 9 and 16 is a signal indicating these states. Here, STATE_SEL = H level corresponds to the Lock detection state, and L level corresponds to the error detection state. The pattern comparison circuit 34a includes a circuit that generates the same PRBS pattern as the pattern generation circuit 22a. In the Lock detection state, the received data is taken into the pattern generation circuit 34a for each cycle, and expected value data is generated using the received data as an initial value.
[0117]
For example, when 0 run length or 1 run length data is received in the Lock detection state, Lock detection is impossible in the pattern generation circuit 34a, and the Lock detection operation is performed again. In the error detection state, the expected value data captured at the end of the Lock detection state is set as an initial value, and the expected value data is continuously generated. If the received data does not match the expected value data even with 1 bit, it is regarded as an error. The conventional pattern comparison circuit 34 outputs this error flag as it is. On the other hand, the pattern comparison circuit 34a in the present embodiment masks the error flag when it receives data of 0 run length or 1 run length.
[0118]
However, in this case, the length of data of 0 run length or 1 run length must be 64 bits or more. For example, as described above, the SONET standard defines a maximum length of 72 bits as 0 run length or 1 run length data. For this reason, when this embodiment is used, the length of data of 0 run length or 1 run length is set to LENGTH [2: 0] = 2 to be set in the PRBS pattern generation circuit of the data transmission circuit. The data length of 0 run length or 1 run length is 96 bits. Thereby, a test stricter than the SONET standard described above can be performed. In this embodiment, the period for masking the error flag ERROR is defined by the signal ERROR_SEL as described above, and the error is detected by comparing the expected value data and the received data in the same manner as in the conventional example except for this mask period. Each time an error is detected, the error flag ERROR is output at H level.
[0119]
With the above configuration, the data transmission / reception circuit 1c according to the present embodiment generates a PRBS pattern including 0 run length or 1 run length data in the transmission / reception data while using a conventional mass production test system, and further generates jitter. It can be included and sent and received. That is, when evaluating the jitter tolerance, a test of 0 run length or 1 run length can be performed together, and the failure detection rate can be improved.
[0120]
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.
The embodiment of the present invention can be applied variously as shown below, for example.
[0121]
(Supplementary Note 1) Clock generation means for generating a clock signal;
Jitter supply means for including jitter in the clock signal generated by the clock generation means;
A data transmission circuit for transmitting data in synchronization with the clock signal including the jitter;
A data transmission device comprising:
[0122]
(Supplementary note 2) The data transmitting apparatus according to supplementary note 1, wherein the jitter supply means can adjust a modulation amount and / or a frequency of the jitter included in the clock signal.
[0123]
(Supplementary note 3) The data transmission apparatus according to supplementary note 1, wherein the jitter supply unit can supply at least one of a sine wave jitter and a random jitter as the jitter.
[0124]
(Supplementary Note 4) Clock generation means for generating a first clock signal;
Jitter supply means for including jitter in the first clock signal generated by the clock generation means;
A data transmission circuit for transmitting data in synchronization with the first clock signal including the jitter;
An input / output interface circuit comprising:
[0125]
(Supplementary Note 5) The input / output interface circuit according to Supplementary Note 4, wherein the jitter supply means can adjust a modulation amount and / or a frequency of the jitter included in the first clock signal.
[0126]
(Supplementary note 6) The input / output interface circuit according to supplementary note 4, wherein the jitter supply means can supply at least one of sine wave jitter and random jitter as the jitter.
[0127]
(Additional remark 7) The data receiving circuit which receives data is further provided,
The clock generation means further supplies a second clock signal to the data receiving circuit,
The data transmission circuit includes:
Pattern generation means for generating a data pattern for jitter tolerance test;
Transmitting means for transmitting the data pattern generated by the pattern generating means in synchronization with the first clock signal;
With
The data receiving circuit includes:
Receiving means for receiving the data pattern received from the transmitting means in synchronization with the second clock signal;
Pattern comparing means for comparing the data pattern received by the receiving means with an expected value and outputting a comparison result;
Having
The input / output interface circuit according to appendix 4, wherein:
[0128]
(Additional remark 8) It further has the measurement result storage means which links | relates and stores the said comparison result which the said pattern comparison means outputs, and the information regarding the modulation amount and / or frequency of the said jitter which the said jitter supply means supplies. The input / output interface circuit according to appendix 7, which is characterized.
[0129]
(Supplementary Note 9) Jitter supply means control means for controlling the jitter supply means to change the modulation amount and / or frequency of the jitter according to the comparison result output from the pattern comparison means and the jitter tolerance measurement procedure. The input / output interface circuit according to appendix 7, further comprising:
[0130]
(Supplementary Note 10) When the comparison result output from the pattern comparison unit is acceptable, the jitter supply control unit changes the modulation amount of the jitter, and the comparison result output from the pattern comparison unit is invalid. 8. The input / output interface circuit according to appendix 7, wherein if the result is acceptable, the jitter supply means is controlled to change the frequency of the jitter.
[0131]
(Additional remark 11) The said pattern generation means of the said data transmission circuit is further provided with the function to include the data which 0 or 1 continues in the said data pattern,
When the pattern comparison means of the data receiving circuit detects that the 0 or 1 has received continuous data and the function has detected that the 0 or 1 has been received continuously, And a function for forcibly passing the comparison result.
The input / output interface circuit according to appendix 7, wherein:
[0132]
(Additional remark 12) The said pattern generation means of the said data transmission circuit replaces a part of the said data pattern with the data which 0 or 1 continues, and makes the said data pattern include the data which 0 or 1 continues. The input / output interface circuit according to Supplementary Note 11, wherein the input / output interface circuit is characterized.
[0133]
(Additional remark 13) The said pattern generation means of the said data transmission circuit inserts the data which 0 or 1 continues in the middle of the said data pattern, and makes the data pattern include the data which 0 or 1 continues. The input / output interface circuit according to Supplementary Note 11, wherein the input / output interface circuit is characterized.
[0134]
(Additional remark 14) The said pattern generation means of the said data transmission circuit is further provided with the function to adjust the said period, when the data pattern contains the data which 0 or 1 continues periodically. The input / output interface circuit according to appendix 11.
[0135]
【The invention's effect】
As explained above, according to the present invention, Enter In the output interface circuit, jitter can be included in the clock signal supplied to the data transmission circuit, so that transmission data output from the data transmission circuit can also include jitter. Accordingly, it is possible to test the jitter tolerance (jitter tolerance) by checking whether or not the data receiving circuit can properly receive the transmission data. Thereby, the failure detection rate at the time of mass production test can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an internal configuration example 1 of the clock generation circuit 5 shown in FIG. 1;
FIG. 3 is a diagram illustrating an internal configuration example 2 of the clock generation circuit 5 illustrated in FIG. 1;
FIG. 4 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram illustrating an operation in which the data transmission / reception circuit 1b illustrated in FIG. 4 measures jitter tolerance characteristics.
FIG. 6 is a diagram showing an overall configuration of a data transmission / reception circuit including a jitter test circuit according to a third embodiment of the present invention.
7 is a diagram illustrating an internal configuration example of a PRBS pattern generation circuit 22a illustrated in FIG. 6;
8 is a waveform diagram showing an operation of the PRBS pattern generation circuit 22a shown in FIG.
9 is a diagram showing an internal configuration example of a pattern comparison circuit 34a shown in FIG. 6;
10 is a waveform diagram showing an operation of the pattern comparison circuit 34a shown in FIG.
FIG. 11 is a diagram showing a loop configuration for testing a data transmission / reception circuit.
12 is a diagram showing a conventional circuit configuration example in the clock generation circuit 4 shown in FIG. 11;
13 is a diagram showing a conventional circuit configuration example in the PRBS pattern generation circuit 22 shown in FIG.
14 is a diagram showing a detailed circuit configuration example of an XOR group 225 shown in FIG.
15 is a waveform diagram for explaining the operation of the PRBS pattern generation circuit 22 shown in FIG.
16 is a diagram showing a conventional circuit configuration example in the pattern comparison circuit shown in FIG.
17 is a waveform chart for explaining the operation of the pattern comparison circuit shown in FIG.
[Explanation of symbols]
1, 1a, 1b, 1c Data transmission / reception circuit
2, 2c data transmission circuit
3, 3a, 3c data receiving circuit
4, 5 Clock generation circuit
6 Clock generation circuit control circuit
21 Clock control circuit
21a Frequency divider (× 1/2)
21b Phase shift circuit
21c Frequency divider (× 1/8)
22, 22a PRBS pattern generation circuit
23, 24 selector
25 32: 4 conversion circuit
26 Driver circuit
27 buffers
31 Clock control circuit
32 Receiver circuit
33 4:32 conversion circuit
34, 34a Pattern comparison circuit
35 Filter circuit
36 Measurement time counting circuit
51 Jitter generation circuit
52 Voltage adder
53 Second VCO
54 selector
55 DLL
63 Counter A
64 comparison circuit
68 Counter B
69 Comparison circuit
73 Inverting flip-flop with enable
74 Selector
81 0/1 detection circuit
86 Selector
224 Flip-flop with enable
225, 344 XOR group
345 comparison circuit
346 Demultiplexer
351 sequencer

Claims (7)

Clock generating means for generating a first clock signal;
Jitter supply means for including jitter in the first clock signal generated by the clock generation means;
A data transmission circuit for transmitting data in synchronization with the first clock signal including the jitter;
A data receiving circuit for receiving data,
The clock generation means further supplies a second clock signal to the data receiving circuit,
The data transmission circuit includes:
Pattern generation means for generating a data pattern for jitter tolerance test;
Transmitting means for transmitting the data pattern generated by the pattern generating means in synchronization with the first clock signal including the jitter , and
The data receiving circuit includes:
Receiving means for receiving the data pattern received from the transmitting means in synchronization with the second clock signal;
Pattern comparing means for comparing the data pattern received by the receiving means with an expected value and outputting a comparison result ; and
The pattern generation means of the data transmission circuit further comprises a function of including data in which 0 or 1 continues in the data pattern,
When the pattern comparison means of the data receiving circuit detects that the 0 or 1 has received continuous data, and the function has detected that the 0 or 1 has received continuous data, And an input / output interface circuit further comprising a function for forcibly passing the comparison result .   2. The input / output interface circuit according to claim 1, wherein the jitter supply unit is capable of adjusting a modulation amount and / or a frequency of the jitter included in the first clock signal.   The input / output interface circuit according to claim 1, wherein the jitter supply unit can supply at least one of sine wave jitter and random jitter as the jitter.   The measurement result storing means for storing the comparison result output from the pattern comparing means and information relating to the modulation amount and / or frequency of the jitter supplied from the jitter supplying means in association with each other. The input / output interface circuit according to any one of claims 1 to 3.   Jitter supply means control means for controlling the jitter supply means to change the modulation amount and / or frequency of the jitter according to the comparison result output from the pattern comparison means and the measurement procedure of the jitter tolerance. The input / output interface circuit according to any one of claims 1 to 4, wherein the input / output interface circuit is provided.   When the comparison result output from the pattern comparison unit is acceptable, the jitter supply control unit changes the modulation amount of the jitter, and the comparison result output from the pattern comparison unit is unacceptable. 6. The input / output interface circuit according to claim 1, wherein the jitter supply unit is controlled to change a frequency of the jitter. The input / output interface according to any one of claims 1 to 6 , wherein the first clock signal is obtained by adding jitter by the jitter supply means to the second clock signal. circuit.

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