JP3436498B2 - Clock generation circuit with frequency correction function - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDC (Personal
The present invention relates to a clock generation circuit for a system such as a digital cellular, and particularly to a function of holding a system clock frequency during standby. 2. Description of the Related Art In a portable telephone such as a PDC, a receiving operation for monitoring a base station radio wave is intermittently performed in order to suppress a current consumption in a standby state. During standby, a period during which the receiving operation is performed (hereinafter, “non-sleep”) and a period during which reception is not performed (hereinafter, “sleep”)
Divided into In order to accurately execute the reception demodulation operation immediately after the transition from the sleep mode to the non-sleep mode, the frequency of the system clock, which is the clock that provides the basic timing in the processing such as demodulation, is accurately held even during the sleep time of 680 ms at most. , It must maintain synchronization with the received wave. Conventionally, the system clock during sleep is generated by a method of dividing the master clock generated by the crystal oscillator, and as means for accurately maintaining the frequency of this system clock,
For example, a GT cut crystal having a high accuracy of 8 ppm has been used as an oscillator. FIG. 1 shows an example of the prior art. In the figure, 1
Reference numeral 0 denotes a PLL (Phase Locked Loop), which is provided from a phase comparator 12 and a phase comparator 12 which compare the phase of the received wave reproduction clock with the system master clock during operation and generate an error signal indicating the lead / lag of the phase. It comprises an integrator 14 for integrating the error signal and a variable frequency divider 16 whose frequency division ratio changes according to the output of the integrator 14.
The received wave recovered clock input to the phase comparator 12 is a clock recovered from the received wave.
Hz. The operating system master clock is the frequency divided output of the variable frequency divider 16 and is 42 kHz for PDC.
It is. Further, what is divided by the variable frequency divider 16 is
Master clock oscillated by a high-precision crystal oscillator 18 such as GT cut (in the case of PDC, for example, 2.4 MHz)
Is multiplied by the multiplier 20 to, for example, 14.4 MHz. Therefore, during the signal reception period including the non-sleep state during standby, the phase lock is applied so that the operating system master clock is synchronized with the received wave reproduction clock. During operation, the system master clock is supplied as a system clock to a not-shown baseband circuit via a selector 22. In the sleep mode, no signal can be received and, therefore, a received-wave recovered clock cannot be obtained. Therefore, an operating system master clock cannot be obtained. Therefore, the master clock oscillated by the crystal oscillator 18 is divided by the frequency divider 2
The frequency is divided by 4 and 26, and the resulting sleep-time system master clock is supplied as a system clock to a subsequent baseband circuit (not shown) via the selector 22. In the case of PDC, the sleep time system master clock is set to 42 kHz, and the frequency division ratios of the frequency dividers 24 and 26 are, for example, 1/6 or 21/200, respectively. The clock switching timing control circuit 28 switches the output of the selector 22 from the operating system master clock to the sleep system master clock or vice versa by monitoring the system clock output from the selector 22. The principle and method are well-known in the art, and a description thereof will be omitted. [0005] However, in order to accurately maintain the frequency of the system clock by the circuit shown in FIG. 1, a high-precision oscillator must be used as the crystal oscillator 18. However, in general, high-precision oscillators such as GT-cut quartz are expensive. For this reason, it has been conventionally required in terms of cost to use a lower-cost (but less accurate) oscillator in place of the crystal oscillator 18 in FIG. Furthermore,
TCXO (Temperature Compensated X'tal Oscillator)
However, there is also a problem that the high-precision oscillator such as that described above consumes a large amount of current and is not suitable for intermittent operation. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is intended to generate a system master clock at the time of sleep using a less accurate but less expensive oscillator while receiving a received signal. The purpose of the present invention is to make it possible to maintain the synchronization with respect to the clock accurately during sleep, and to realize a cheaper circuit. In order to achieve the above object, according to the present invention, necessary information is received from a PLL circuit while a master clock is obtained during operation, and the received information is added to the received information. The function of adjusting and controlling the frequency division ratio of the master clock based on this is added to the circuit for generating the system master clock during sleep. That is, the present invention provides (1) an oscillator which oscillates at a predetermined frequency, and (2) a first frequency divider which variably divides a master clock output from the oscillator and outputs an operating system master clock. And (3) a PLL including the first frequency divider and controlling the frequency division ratio of the first frequency divider so that the operating system master clock is phase-locked to the received wave recovered clock during operation. A) a second frequency divider for generating a system master clock during sleep by dividing the master clock; and (5) a system clock for operation when the system clock for operation is obtained when the recovered clock for the received wave is obtained. Otherwise, a means for selecting each of the system master clocks at the time of sleep and supplying the system master clocks to the subsequent stage is provided. , (6) a second divider, and its frequency division ratio adjustable control from the outside of the variable frequency divider, (7)
Furthermore, the second frequency division during the period during which the received wave recovered clock cannot be obtained from the control signal of the frequency division ratio given to the first frequency divider by the PLL during the period during which the received wave recovered clock can be obtained. Means for determining the frequency division ratio of the frequency divider and controlling the frequency division ratio of the second frequency divider based on the result. As described above, in the present invention, the circuit for generating the master clock during sleep is not free-running, but the frequency is corrected using the variable frequency divider. Further, at the time of this frequency correction, a signal obtained from the PLL is input during a period in which the clock can be reproduced from the received wave, and based on this, the frequency division ratio of the second frequency divider as the variable frequency divider is set and changed. I have to. Therefore,
An oscillator for generating a master clock can be reduced in accuracy and cost without a large-scale circuit modification / addition. Preferred embodiments of the present invention will be described below with reference to the drawings. The present invention can be implemented by partially modifying the conventional technique shown in FIG. for that reason,
The embodiment of the present invention described below has components common to FIG. Therefore, for simplification of description, FIG.
The redundant description of the components shown in FIG.
However, the present invention can be applied not only to the modification of the circuit shown in FIG. 1 but also to other types of configurations without departing from the gist thereof. FIG. 2 shows a circuit configuration according to an embodiment of the present invention. In the circuit shown in this figure, a correction amount integration control amount calculation conversion unit 30, a frame-by-frame control unit 32
And a circuit composed of the variable frequency divider 34 generates the system master clock during sleep. In this figure, a tuning fork type 100 kHz oscillator is used as a crystal oscillator for generating a master clock.
Therefore, the reference numeral 18A, which is different from the crystal oscillator 18 in FIG. The correction amount integration control amount calculation conversion section 30 has a PL
During the period in which the operating system master clock is generated by L10, that is, during a call or during a non-sleep state during standby, the frequency divider ratio control signal from the integrator 14 to the variable frequency divider 16 (“correction amount” in the figure). Enter The correction amount integration control amount calculation conversion unit 30 calculates the control amount of the frequency division ratio in the variable frequency divider 34 from the input correction amount. For example, the control amount is obtained by integrating the input correction amounts over a predetermined period and calculating the average. However, the simple frequency averaging is not sufficient for the basic frequency division ratio of the variable frequency divider 16 (for example, 1/3).
The control amount is based on 6). Further, since the variable frequency divider 34 divides the decimal point as described later, an adjustment process for adapting to the decimal point is required. Therefore, the correction amount integration control amount calculation conversion unit 30 converts the control amount obtained by the averaging from the amount for the variable frequency divider 16 into the variable frequency divider 34.
After being converted to a desired amount and adjusted in consideration of the decimal point frequency division, it is supplied to the frame-by-frame control unit 32.
The frame-by-frame control unit 32 detects the frequency of the sleep-time system master clock every predetermined period (frame), and outputs the result and the correction amount integration control amount calculation conversion unit 3
The frequency division ratio in the variable frequency divider 34 is variably controlled according to the control amount given from 0. In the case of PDC, for example, 2
1/48, 21/49, 21/50, 21/51, 21
/ 52. As described above, according to the present embodiment, information indicating a frequency error of the master clock is input from the PLL 10 during a call or during a non-sleep state while waiting, and a sleep-time system master clock is obtained based on the information. The frequency division ratio of the variable frequency divider 34 is adjusted and controlled, so that the crystal oscillator 18A has an error of 200p
A relatively large but inexpensive tuning-fork-shaped crystal oscillator of the order of pm can be used, and as a result, an inexpensive circuit with performance equal to or better than the conventional one can be obtained. There is no need to provide a temperature compensation circuit or the like for the crystal oscillator 18A. Except for the crystal oscillator (18 or 18A), the circuit according to the present embodiment is a digital ASIC (App).
Since the circuit shown in FIG. 1 can be configured from the circuit shown in FIG. 1 (excluding the oscillator part), no extra cost is involved.
In other words, the deformed portion according to the features of the present embodiment can be easily incorporated into the integrated circuit except for the oscillator portion.
It is easy to realize and suitable for miniaturization.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a circuit according to one related art. FIG. 2 is a block diagram illustrating a configuration of a circuit according to an embodiment of the present invention. [Description of Signs] 10 PLL, 12 phase comparator, 14 integrator, 1
6, 34 Variable frequency divider, 18A crystal oscillator, 20 multiplier, 22 selector, 28 clock switching timing control circuit, 30 correction amount integration control amount operation conversion section, 32
Control unit for each frame.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-223236 (JP, A) JP-A-5-276087 (JP, A) JP-A-4-43717 (JP, A) JP-A-9-1997 321694 (JP, A) Japanese Patent Laid-Open No. Hei 10-17342 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/033 H03L 7/00

Claims (1)

(57) Claims 1. An oscillator that oscillates at a predetermined frequency, and a first frequency divider that variably divides a master clock output from the oscillator and outputs a system master clock during operation. And a PLL that includes the first frequency divider and controls the frequency division ratio of the first frequency divider so that the operating system master clock is phase-locked to the received wave recovered clock, and divides the master clock. A second frequency divider for generating a system master clock during sleep, and a system master clock during operation when a received wave recovered clock and, consequently, a system master clock during operation are obtained, and a system master clock during sleep otherwise. Means for selecting and supplying to a subsequent stage, wherein the second frequency divider has A variable frequency divider whose frequency division ratio can be externally adjusted and controlled. Further, during a period in which a received wave recovered clock can be obtained, a PLL controls a frequency division ratio given to the first frequency divider by a control signal. Means for determining the frequency division ratio of the second frequency divider during a period during which a received wave recovered clock cannot be obtained, and controlling the frequency division ratio of the second frequency divider based on the result. Clock generation circuit.