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JP3496639B2 - High frequency semiconductor device - Google Patents

High frequency semiconductor device

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Publication number
JP3496639B2
JP3496639B2 JP2000364220A JP2000364220A JP3496639B2 JP 3496639 B2 JP3496639 B2 JP 3496639B2 JP 2000364220 A JP2000364220 A JP 2000364220A JP 2000364220 A JP2000364220 A JP 2000364220A JP 3496639 B2 JP3496639 B2 JP 3496639B2
Authority
JP
Japan
Prior art keywords
semiconductor device
frequency
frequency semiconductor
terminal
electrostatic breakdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000364220A
Other languages
Japanese (ja)
Other versions
JP2002170931A (en
Inventor
武人 國久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000364220A priority Critical patent/JP3496639B2/en
Publication of JP2002170931A publication Critical patent/JP2002170931A/en
Application granted granted Critical
Publication of JP3496639B2 publication Critical patent/JP3496639B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明はマイクロ波、ミリ波
周波数帯で用いられる高周波半導体チップと該高周波半
導体チップをパッケージに封止した高周波半導体装置及
び前記高周波半導体チップあるいは前記高周波半導体装
置を搭載したマザーボードを有する高周波通信機に関す
るものである。 【0002】 【従来の技術】高周波用の半導体デバイス(例えばHEMT
やMODFETを含む広義のGaAs MESFET、GaAs HBT、SiGe
HBTなど)は、高周波で動作させるため微細加工が必要
となり静電気破壊に弱いという問題があった。従来、静
電気破壊から半導体デバイスを保護する手段としては、
図5に示すような保護ダイオードを保護すべき端子と接
地間に挿入し、静電気電流を接地に逃がすという方法が
多く用いられてきた。例えば特公平6-69101号公報、特
公平7-40571号公報、特公平6-26243号公報、特公平7-19
782号公報などに記載されている通りである。しかし、
マイクロ波、ミリ波などの高周波領域では保護ダイオー
ドの寄生容量、寄生抵抗及び非線形性により信号の損
失、歪みの発生が生じ、高周波特性が劣化するという問
題があった。一方、高周波特性を重視した保護ダイオー
ドを用いない高周波半導体チップでは、静電気破壊を生
じさせないため特殊な組立ラインが必要となり、パッケ
ージ組立やベアチップ実装が困難であるという課題があ
った。 【0003】 【発明が解決しようとする課題】本発明の課題は、ダイ
オードを用いずに半導体チップの静電気破壊耐性を改善
する手段を提案し、半導体デバイスの高周波特性を劣化
させることなく、高周波半導体チップを実現し、特殊な
組立ラインを必要としない高周波性能の良好な高周波半
導体装置及び高周波通信機を実現することである。 【0004】 【課題を解決するための手段】静電気破壊モデルの静電
気波形を検討したところ、キロヘルツ程度までの低周波
成分の瞬間的エネルギーが大きく、ギガヘルツ以上の成
分は小さいことが確認できている。このため、高周波用
の半導体デバイスを静電気破壊から保護する手段として
は低周波をカットする、あるいは低周波成分の通過時定
数を長くすることにより瞬間的発熱量を低減することが
有益であり、高周波用の半導体デバイスの保護すべき端
子に直列に非線形性を持たないMIMキャパシタを挿入
することあるいは高周波用の半導体デバイスの保護すべ
き端子に並列に接地に対してスパイラルインダクタを挿
入することが有用である。なお、MIMキャパシタと
は、容量絶縁膜が2枚の平板電極で挟まれた構成のコン
デンサを指すものとする。 【0005】本発明では、MIMキャパシタを複数個直
列にすることを以下の理由から提案するものである。 1.MIMキャパシタの層間絶縁膜の組成、厚さによっ
てMIMキャパシタ自体が静電気破壊されてしまう場合
があるため、直列に複数個接続することにより、MIM
キャパシタ1個あたりの電圧を分割し、MIMキャパシ
タ自体の破壊を防止する。 2.MIMキャパシタの直列挿入損失はスパイラルイン
ダクタの並列挿入損失及びダイオードの並列挿入損失に
比較して十分小さいため、特性劣化が最小限に抑えられ
る。 3.MIMキャパシタを複数個直列に接続することによ
り、小さな容量値を大きなパターンで実現できるため、
精度の高いキャパシタが実現できる。 【0006】高周波用の半導体デバイスの保護すべき端
子に直列に非線形性を持たないMIMキャパシタを複数
個挿入することにより、特性劣化を生じずにチップの静
電気破壊耐性が改善されるため、特殊な組立ラインを構
築することなくパッケージ組立やベアチップ実装が可能
になり、特性良好な高周波通信機を実現することができ
る。 【0007】 【発明の実施の形態】次に、本発明の実施の形態におけ
る高周波半導体装置について図面を用いて説明する。 【0008】(実施の形態1)まず、図1及び図2を用
いて本発明の実施の形態1における高周波半導体装置に
ついて説明する。 【0009】図1(a)は本発明の実施の形態1におけ
る高周波半導体装置の回路図であり、1はGaAs MODFET
で保護すべき半導体素子であり、2及び3は静電気破壊
保護用に挿入された直列接続されたそれぞれ10pFの
MIMキャパシタ、4は2kΩのゲートバイアス抵抗、
5は信号入力端子であり外部接続端子(パッド)に相当
し、6は1のゲート端子であり保護すべき端子であり、
7は信号出力端子であり1のドレイン端子(他の外部接
続端子)である。実施の形態1における高周波半導体装
置におけるこれらの構成は、全て基板(図示せず)上に
形成されている。 【0010】図1(b)は比較用の高周波半導体装置
(チップ)の回路図であり、図1(a)から2及び3の
キャパシタが除かれたものである。 【0011】図1(b)の静電気破壊耐性を端子6と接
地間について静電気破壊モデル(マシンモデル)を用い
て測定した場合18Vであったが図1(a)の場合の5
と接地間の静電気破壊耐性は40Vであり、本発明によ
り静電気破壊耐性が改善されていることが分かる。 【0012】これは、2及び3のMIMキャパシタの容
量成分により、静電気の低周波成分に大きな時定数が生
じ端子6に印加される時間が長くなるため、結果的に瞬
間的発熱量が低減され静電気破壊耐性が改善されたもの
である。 【0013】図2(a)は図1(a)における直列接続
されたキャパシタ2及び3の平面図であり、図2(b)
は図2(a)のA−A’での断面図である。 【0014】11はMIMキャパシタの下層金属で厚さ
200nmのPt膜で2及び3の接続を兼ねており、1
2及び13はそれぞれMIMキャパシタ2及び3の層間
絶縁膜であり厚さ300nmのSrTiO3膜であり、
14及び15はそれぞれMIMキャパシタ2及び3の上
層金属であり厚さ700nmのAu/Ti膜である。 【0015】12あるいは13は単独の場合30Vの静
電気破壊耐性であるが、直列に接続することにより40
Vまで改善されている事が分かる。 【0016】図1(a)と図1(b)での高周波特性の
違いは、5GHzにおけるNFが図1(a)で0.8d
Bであるのに対し図1(b)では0.9dBでありほと
んど劣化が生じていないことが確認できる。 【0017】なお、本実施の形態では、保護すべき素子
としてGaAs MODFETを使ったが、GaAs HEMTを含む広義の
MESFETであっても、Si MOSFETであっても、同様の効果
が得られる。また、MIMキャパシタの層間絶縁膜をS
rTiO3として説明したが、BaSrTiO3等の強誘
電体材料、一般的な酸化シリコン、窒化シリコンでも同
様の効果を得ることができる。 【0018】また、本実施の形態では、同じ容量値のM
IMキャパシタを2個直列に接続した例について説明し
たが、それぞれ異なる容量値で有っても、また、3つ以
上のMIMキャパシタを直列に接続しても同様の効果を
得ることができる。 【0019】(実施の形態2)次に、本発明の実施の形
態2における高周波半導体装置について図3を用いて説
明する。 【0020】図3は、実施の形態2における高周波半導
体装置の回路図であり、1はGaAs MODFETで保護すべき
素子であり、2及び3は静電気破壊保護用に挿入された
直列接続されたそれぞれ10pFのキャパシタ、5は信
号入力端子であり外部接続パッドに相当し、6は1のゲ
ート端子であり保護すべき端子であり、7は信号出力端
子であり1のドレイン端子で外部接続端子であり、8は
2kΩのゲートバイアス抵抗である。なお、図1(a)
と同じ番号のものは同じ素子、端子を示している。 【0021】実施の形態1では、1のMODFETのゲ
ートバイアス電圧は接地電位に固定されてしまうため、
チップ外部からゲートバイアス電圧を変更することが不
可能であった。 【0022】本実施の形態では、MIMキャパシタ2、
3と並列にゲートバイアス抵抗8を挿入しているため入
力端子5からゲートバイアス電圧を設定することが可能
となる。 【0023】(実施の形態3)次に図4を用いて本発明
の実施の形態3における高周波半導体装置について説明
する。 【0024】図4は本発明の実施の形態3における高周
波半導体装置の回路図であり、21はGaAs HBTで保護す
べき素子であり、22及び23は静電気破壊保護用に挿
入された直列接続されたそれぞれ10pFのキャパシ
タ、24は21のベースにベース電流を供給するベース
バイアス回路、25は信号入力端子であり外部接続パッ
ドに相当し、26は21のベース端子であり保護すべき
端子であり、27は信号出力端子であり21のコレクタ
端子で外部接続端子である。 【0025】本実施の形態においても実施の形態1で述
べたように静電気破壊耐性の改善効果が得られる。 【0026】なお、本実施の形態では、GaAs HBTを用い
たが、SiGe HBTやSi バイポーラトランジスタでも同様
な効果が得られる。 【0027】実施の形態1ないし3による高周波チップ
を用いることにより、例えばマシンモデルにおけるクラ
ス0(25V以下)のラインでしか組み立てられなかっ
たチップがクラス1(25〜100V)のラインで組み
立てられるようになるため、容易に組み立てができるよ
うになり、高周波性能の良好な高周波半導体装置、高周
波通信機を実現することが可能となる。なお、高周波半
導体装置には、高周波半導体チップがプラスチックパッ
ケージやセラミックパッケージに封止され母基板である
プリント基板あるいはセラミック基板上に実装されてい
るもの又はベアチップ状態で母基板に実装されているも
の、及びプリント基板あるいはセラミック基板上に高周
波半導体チップとチップ部品が実装されている、いわゆ
るモジュール型の高周波半導体装置を含む。 【0028】 【発明の効果】本発明によれば、高周波性能を劣化させ
ることなく静電気破壊耐性を改善することができる。ま
た、静電気破壊耐性を改善することによって、パッケー
ジや通信機のマザーボードに容易に組み立てができるよ
うになり高周波性能の良好な半導体装置や高周波通信機
を実現することができる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor chip used in microwave and millimeter-wave frequency bands, a high-frequency semiconductor device in which the high-frequency semiconductor chip is sealed in a package, and the high-frequency semiconductor device. The present invention relates to a high frequency communication device having a semiconductor chip or a mother board on which the high frequency semiconductor device is mounted. A semiconductor device for high frequency (for example, HEMT)
GaAs MESFET, GaAs HBT, SiGe including MODFET
HBT, etc.) has a problem that it is vulnerable to electrostatic breakdown because it requires fine processing to operate at a high frequency. Conventionally, as means for protecting semiconductor devices from electrostatic breakdown,
A method of inserting a protective diode as shown in FIG. 5 between a terminal to be protected and the ground and releasing the electrostatic current to the ground has been often used. For example, Japanese Patent Publication No. 6-69101, Japanese Patent Publication No. 7-40571, Japanese Patent Publication No. 6-24243, Japanese Patent Publication No. 7-19
It is as described in the 782 publication. But,
In high frequency regions such as microwaves and millimeter waves, there is a problem that signal loss and distortion occur due to parasitic capacitance, parasitic resistance, and nonlinearity of the protection diode, and high frequency characteristics deteriorate. On the other hand, a high-frequency semiconductor chip that does not use a protection diode that places importance on high-frequency characteristics has a problem that a special assembly line is required to prevent electrostatic breakdown, and package assembly and bare chip mounting are difficult. SUMMARY OF THE INVENTION An object of the present invention is to propose means for improving the resistance to electrostatic breakdown of a semiconductor chip without using a diode, and to prevent high frequency semiconductors from deteriorating the high frequency characteristics of the semiconductor device. It is to realize a chip and realize a high-frequency semiconductor device and a high-frequency communication device with good high-frequency performance that do not require a special assembly line. As a result of examining the electrostatic waveform of the electrostatic breakdown model, it has been confirmed that the instantaneous energy of the low frequency component up to about kilohertz is large and the component above gigahertz is small. Therefore, as a means to protect high-frequency semiconductor devices from electrostatic breakdown, it is beneficial to reduce the instantaneous heat generation by cutting low frequencies or lengthening the low-frequency component passage time constant. It is useful to insert an MIM capacitor having no nonlinearity in series with a terminal to be protected of a semiconductor device for use or to insert a spiral inductor with respect to ground in parallel with a terminal to be protected of a semiconductor device for high frequency. is there. Note that the MIM capacitor refers to a capacitor having a configuration in which a capacitive insulating film is sandwiched between two plate electrodes. The present invention proposes that a plurality of MIM capacitors be connected in series for the following reason. 1. Depending on the composition and thickness of the interlayer insulating film of the MIM capacitor, the MIM capacitor itself may be electrostatically destroyed.
The voltage per capacitor is divided to prevent destruction of the MIM capacitor itself. 2. Since the series insertion loss of the MIM capacitor is sufficiently smaller than the parallel insertion loss of the spiral inductor and the parallel insertion loss of the diode, the characteristic deterioration can be minimized. 3. By connecting a plurality of MIM capacitors in series, a small capacitance value can be realized in a large pattern.
A highly accurate capacitor can be realized. By inserting a plurality of non-linear non-linear MIM capacitors in series into the terminals to be protected of the high-frequency semiconductor device, the electrostatic breakdown resistance of the chip can be improved without causing characteristic deterioration. Package assembly and bare chip mounting are possible without constructing an assembly line, and a high-frequency communication device with good characteristics can be realized. DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a high frequency semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. (Embodiment 1) First, a high-frequency semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1A is a circuit diagram of a high-frequency semiconductor device according to Embodiment 1 of the present invention, where 1 is a GaAs MODFET.
2 and 3 are 10 pF MIM capacitors connected in series and inserted for protection against electrostatic breakdown, 4 is a gate bias resistor of 2 kΩ,
5 is a signal input terminal corresponding to an external connection terminal (pad), 6 is a gate terminal of 1 and is a terminal to be protected,
A signal output terminal 7 is a drain terminal 1 (another external connection terminal). All of these components of the high-frequency semiconductor device according to the first embodiment are formed on a substrate (not shown). FIG. 1B is a circuit diagram of a high-frequency semiconductor device (chip) for comparison, which is obtained by removing the capacitors 2 and 3 from FIG. 1A. The electrostatic breakdown resistance of FIG. 1B was 18 V when measured between the terminal 6 and the ground using an electrostatic breakdown model (machine model), but it was 5 in the case of FIG. 1A.
The resistance to electrostatic breakdown between the ground and the ground is 40 V, and it can be seen that the electrostatic breakdown resistance is improved by the present invention. This is because, due to the capacitance components of the MIM capacitors 2 and 3, a large time constant is generated in the low frequency component of static electricity and the time applied to the terminal 6 is lengthened. As a result, the instantaneous heat generation amount is reduced. It has improved resistance to electrostatic breakdown. FIG. 2A is a plan view of the capacitors 2 and 3 connected in series in FIG. 1A, and FIG.
FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. Reference numeral 11 denotes a lower layer metal of the MIM capacitor, which is a Pt film having a thickness of 200 nm and also serves as a connection between 2 and 3.
Reference numerals 2 and 13 are interlayer insulating films of the MIM capacitors 2 and 3, respectively, and SrTiO 3 films having a thickness of 300 nm.
Reference numerals 14 and 15 are upper metal layers of the MIM capacitors 2 and 3, respectively, and are Au / Ti films having a thickness of 700 nm. When 12 or 13 is used alone, it has a resistance to electrostatic breakdown of 30 V.
It turns out that it has improved to V. The difference in high frequency characteristics between FIG. 1 (a) and FIG. 1 (b) is that NF at 5 GHz is 0.8d in FIG. 1 (a).
In contrast to B, in FIG. 1B, it is 0.9 dB, and it can be confirmed that almost no deterioration has occurred. In this embodiment, GaAs MODFET is used as an element to be protected. However, in a broad sense including GaAs HEMT.
The same effect can be obtained regardless of whether it is a MESFET or a Si MOSFET. Also, the interlayer insulating film of the MIM capacitor is made of S
Although described as rTiO 3 , the same effect can be obtained with a ferroelectric material such as BaSrTiO 3 , general silicon oxide, and silicon nitride. In the present embodiment, M having the same capacitance value is used.
Although an example in which two IM capacitors are connected in series has been described, the same effect can be obtained even if they have different capacitance values, or if three or more MIM capacitors are connected in series. (Embodiment 2) Next, a high-frequency semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 is a circuit diagram of the high-frequency semiconductor device according to the second embodiment. Reference numeral 1 denotes an element to be protected by a GaAs MODFET. Reference numerals 2 and 3 denote series-connected elements inserted for protection against electrostatic breakdown. 10 pF capacitor, 5 is a signal input terminal and corresponds to an external connection pad, 6 is a gate terminal of 1 and a terminal to be protected, 7 is a signal output terminal, 1 is a drain terminal and an external connection terminal , 8 are 2 kΩ gate bias resistors. FIG. 1 (a)
Those having the same numbers indicate the same elements and terminals. In the first embodiment, the gate bias voltage of one MODFET is fixed to the ground potential.
It was impossible to change the gate bias voltage from outside the chip. In the present embodiment, the MIM capacitor 2,
3, the gate bias resistor 8 is inserted in parallel, so that the gate bias voltage can be set from the input terminal 5. (Embodiment 3) Next, a high-frequency semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 is a circuit diagram of the high-frequency semiconductor device according to the third embodiment of the present invention, 21 is an element to be protected by GaAs HBT, and 22 and 23 are connected in series inserted for protection against electrostatic breakdown. 10 pF capacitors, 24 is a base bias circuit for supplying a base current to 21 bases, 25 is a signal input terminal corresponding to an external connection pad, 26 is a base terminal of 21 and is a terminal to be protected, A signal output terminal 27 is a collector terminal 21 and an external connection terminal. Also in this embodiment, as described in the first embodiment, the effect of improving the resistance to electrostatic breakdown can be obtained. In this embodiment, GaAs HBT is used, but the same effect can be obtained with SiGe HBT or Si bipolar transistor. By using the high-frequency chip according to the first to third embodiments, for example, a chip that can only be assembled on a class 0 (25 V or lower) line in a machine model can be assembled on a class 1 (25 to 100 V) line. Therefore, it becomes possible to easily assemble, and it is possible to realize a high-frequency semiconductor device and a high-frequency communication device with good high-frequency performance. In the high-frequency semiconductor device, a high-frequency semiconductor chip is sealed in a plastic package or a ceramic package and mounted on a printed circuit board or a ceramic substrate that is a mother substrate, or is mounted on a mother substrate in a bare chip state, And a so-called modular high-frequency semiconductor device in which a high-frequency semiconductor chip and a chip component are mounted on a printed circuit board or a ceramic substrate. According to the present invention, the resistance to electrostatic breakdown can be improved without deteriorating the high frequency performance. In addition, by improving the resistance to electrostatic breakdown, it is possible to easily assemble the package and the motherboard of the communication device, thereby realizing a semiconductor device and a high-frequency communication device with good high-frequency performance.

【図面の簡単な説明】 【図1】(a)本発明の実施の形態1における高周波半
導体装置の回路図 (b)比較用の高周波半導体装置の回路図 【図2】(a)本発明の実施の形態1における高周波半
導体装置のキャパシタの平面図 (b)同キャパシタの断面図 【図3】本発明の実施の形態2における高周波半導体装
置の回路図 【図4】本発明の実施の形態3における高周波半導体装
置の回路図 【図5】保護ダイオードを用いた従来の高周波半導体装
置の回路図 【符号の説明】 1 MODFET 2、3 MIMキャパシタ 4 ゲートバイアス抵抗 5 信号入力端子 6 ゲート端子 7 信号出力端子 8 ゲートバイアス抵抗 11 下層金属 12、13 層間絶縁膜 14、15 上層金属 21 HBT 22、23 キャパシタ 24 ベースバイアス回路 25 信号入力端子 26 ベース端子 27 信号出力端子
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a circuit diagram of a high-frequency semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a circuit diagram of a high-frequency semiconductor device for comparison. FIG. 3 is a cross-sectional view of the capacitor of the high-frequency semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram of the high-frequency semiconductor device according to the second embodiment of the present invention. FIG. 5 is a circuit diagram of a conventional high-frequency semiconductor device using a protection diode. DESCRIPTION OF SYMBOLS 1 MODFET 2, 3 MIM capacitor 4 Gate bias resistor 5 Signal input terminal 6 Gate terminal 7 Signal output Terminal 8 Gate bias resistor 11 Lower metal 12, 13 Interlayer insulating film 14, 15 Upper metal 21 HBT 22, 23 Capacitor 24 Base bias circuit 25 Signal input terminal 26 the base terminal 27 signal output terminal

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−48809(JP,A) 特開2000−294566(JP,A) 特開2000−260783(JP,A) 特開 昭63−224358(JP,A) 特開2000−68714(JP,A) 特開 平8−274256(JP,A) 特開 平2−159753(JP,A) 国際公開98/012751(WO,A1) (58)調査した分野(Int.Cl.7,DB名) H01L 27/04 H01L 27/06 H01L 21/822 H03F 3/54 - 3/60 ──────────────────────────────────────────────────── ----- Continuation of the front page (56) References JP 4-48809 (JP, A) JP 2000-294566 (JP, A) JP 2000-260783 (JP, A) JP 63-224358 ( JP, A) JP 2000-68714 (JP, A) JP 8-274256 (JP, A) JP 2-159753 (JP, A) International Publication 98/012751 (WO, A1) (58) Survey Field (Int.Cl. 7 , DB name) H01L 27/04 H01L 27/06 H01L 21/822 H03F 3/54-3/60

Claims (1)

(57)【特許請求の範囲】 【請求項1】 半導体基板と、前記半導体基板上に形成
された外部接続端子と、前記半導体基板上に形成されか
前記外部接続端子に接続された半導体素子と、前記半
導体基板上に形成されかつ前記半導体素子と前記外部接
続端子との間に接続された保護素子とを有し、前記保護
素子は複数のMIMキャパシタの直列接続のみからな
り、前記MIMキャパシタは金属と絶縁膜と金属とを前
記半導体基板上に順次積層してなることを特徴とする高
周波半導体装置。
(57) and [Claims 1. A semiconductor substrate, an external connection terminal formed on the semiconductor substrate, or formed on the semiconductor substrate
A semiconductor element connected to said external connection terminals One, the half
A protective element formed on a conductive substrate and connected between the semiconductor element and the external connection terminal;
The element consists only of a series connection of multiple MIM capacitors.
The MIM capacitor has a metal, an insulating film and a metal in front.
A high-frequency semiconductor device characterized by being sequentially laminated on a semiconductor substrate .
JP2000364220A 2000-11-30 2000-11-30 High frequency semiconductor device Expired - Fee Related JP3496639B2 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260783A (en) 1999-03-11 2000-09-22 Hitachi Ltd Semiconductor device, manufacturing method thereof, high frequency power amplifier, and wireless communication device
JP2000294566A (en) 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device, method of manufacturing the same, and method of manufacturing a substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260783A (en) 1999-03-11 2000-09-22 Hitachi Ltd Semiconductor device, manufacturing method thereof, high frequency power amplifier, and wireless communication device
JP2000294566A (en) 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device, method of manufacturing the same, and method of manufacturing a substrate

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