JP3490502B2 - Memory controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling access to a memory device represented by a buffer memory incorporated in a main memory or a central processing unit (CPU) or a main memory.

In the process of a data processing device, a process of moving data from one area to another area is frequently performed in a memory device. A move instruction for moving data in such a memory device includes a fetch flow for reading corresponding data from the memory for each predetermined transfer unit (for example, 8 bytes) and holding it in a read register, and a hold flow for this read register. The stored flow for transferring the stored data to the write register and writing it to the memory is repeated according to the instructed movement amount, thereby performing processing.

Depending on how the program is made,
Since the frequency of movement instructions appearing in a program is very high when performing complicated calculation processing, the processing speed of movement instructions is a factor that greatly affects the performance of the data processing device.

Therefore, there is a need for a technique for accelerating the data movement process in the memory device.

[0005]

2. Description of the Related Art FIG. 9 shows a configuration example of a conventional central processing unit incorporating a buffer memory. Further, FIG. 10 shows a diagram for explaining a data movement process in a conventional central processing unit.

In FIG. 9, the buffer memory 201 is
2 each with a capacity of 1 transfer unit (eg 8 bytes)
Fetch data registers (FCDR) 202a, 202b
And two buffer store word registers (BSWR) 203a and 203b each having a capacity of 8 bytes, the access unit to the buffer memory 201 is two transfer units (that is, 16 bytes). ing.

In this example, the buffer memory 201
A case where the updated data in step 3 is reflected in the main storage device by the swap method will be described. When processing the move command, the command control unit 204 provided in the central processing unit.
In response to the instruction from, the fetch flow is started as shown in FIG.

In the fetch flow, first, each processing is performed in the priority cycle (P) and the tag read cycle (T), and the buffer access cycle is executed.
In (B), the data of the beginning 8 bytes of the data to be moved is read from the buffer memory 201 and held in the fetch data register 202a. Next, in the read cycle (R), the fetch data register 20
2 sends the held data through the selector 205, writes it in the operand word register (OWR) 206 corresponding to the above-mentioned read register, and ends the fetch flow.

At this time, the arithmetic circuit 207 is in the through state according to the instruction from the instruction control unit 204, and the data held in the operand word register 206 is directly passed through the arithmetic circuit 207 to the result register (RR) 208.
Is output to.

The store flow is started one cycle after the start of the fetch flow described above, and the check processing is performed to determine whether the write address is prepared in the four cycles indicated by the symbols P, T, B, and R in FIG. Is being done.

The data held in the result register 208 shown in FIG. 9 is first written in the store data register (STDR) 209, as shown in FIG. 10, and in the next cycle, the store data buffer register (STDB) 210a. In the next cycle, the buffer store word register 20
3a.

Here, the store data register 209 is
In response to an instruction from the instruction control unit 204, data from a register group (not shown) including general-purpose registers and floating-point registers or data from the result register 208 is held, and processing of a move instruction is performed. When
As described above, the data from the result register 208 is selectively retained.

In parallel with this process, the store flow priority cycle (Ps) and the tag read cycle (Ts) are processed, and the data stored in the buffer store word register 203a in the next buffer access cycle. Is written in the corresponding address of the buffer memory 201.

In this way, the process of moving the 8-byte data is completed. If the amount of data to be moved exceeds 8 bytes, the fetch flow for the next 8 bytes of data will be started with a delay of one cycle from the start of the write address check process in the above-described store flow. The movement command is processed by repeating the same processing.

Therefore, for example, a 16-byte data movement instruction is processed by two fetch flows and two store flows, as shown in FIG. Was there.

However, the fetch data register 202b, the store data buffer register 210b, and the buffer store word register 203b, which are not used in the first 8-byte move process, are used in the subsequent 8-byte move process.

The present applicant has already applied for Japanese Patent Application Laid-Open No. 61-206061 as a technique for reducing the processing time of a move command. As shown in FIG. 11, this technique adds a moving data holding register (STDBB) 301 and a selector 302 corresponding to a store data buffer register 210a to the conventional central processing unit shown in FIG.
The first 8 bytes of data are temporarily held in the move data holding register 301, and then written to the store data buffer registers 209a and 209b simultaneously with the next 8 bytes of data, thereby writing 16 bytes of data in one store flow. It made it possible.

In this case, as shown in FIG. 12, 16 fetches are performed by two fetch flows and one store flow.
It is possible to execute an instruction to move bytes of data in a processing time of 9 cycles.

[0019]

In the above-mentioned conventional technique and the technique disclosed in Japanese Patent Laid-Open No. 61-206061, a path for storing the operation result of the operation circuit 207 in the buffer memory 201 as a data transfer path. Are using. Therefore, the width of the data read in one fetch flow is limited by the widths of the fetch data bus that sends data to the arithmetic circuit 207 and the store data bus that sends data from the result register 208 to the store data register 209. .

Therefore, when the amount of data to be moved increases, the number of fetch flows and store flows increases,
The time required for the move process was long. In the technique of Japanese Patent Laid-Open No. 61-206061, since the data read in the two fetch flows is written in the one store flow, the time required for the movement process is short, but the one fetch flow. It is the same that the data width that can be read by means of is dependent on the width of the fetch data bus and the store data bus.

Further, as described above, when the data movement processing is performed via the arithmetic circuit 207, the movement processing and other arithmetic processing cannot be executed in parallel, so the central processing as a whole. In some cases, the performance of the processing device is degraded.

An object of the present invention is to provide a memory control device capable of moving data at high speed in the memory device.

[0023]

FIG. 1 is a principle block diagram of a memory control device according to claims 1 and 2. In FIG. According to a first aspect of the present invention, with respect to the memory 101 in which the storage area is divided into blocks each including a plurality of transfer units each including a plurality of bytes, each access unit including the plurality of transfer units is divided into blocks. A memory control device for controlling access processing, which receives data for each transfer unit via the memory control device and writes the result of the instructed arithmetic processing in the memory 101 via the memory control device together with the central processing unit 102 In the memory control device provided in the device 103, a plurality of fetch data holding units 111 that divides the data of the access unit read from the memory 101 into transfer units and holds the data, and the access unit of the write unit to be written in the memory 101. A plurality of store data holding means 112 for holding data by dividing the data into transfer units
And a transfer means 113 for directly transferring data between the plurality of fetch data holding means 111 and the plurality of store data holding means 112, and the address of the movement target data and the movement destination address designated by the movement instruction. Determines whether or not satisfies a predetermined condition, and instructs the transfer operation by the transfer unit 113 in accordance with the result of the determination that the predetermined condition is satisfied. And a movement control means 115 for instructing a transfer operation via the same.

According to a second aspect of the invention, in the memory control device according to the first aspect, the transfer means 113 holds the data of the transfer unit held in the corresponding fetch data holding means 111 in response to the write instruction. A plurality of moving data holding means 121 and a transfer bus 122 for transferring the data of the transfer unit held in each of the plurality of moving data holding means 121 to the corresponding store data holding means 112 according to the transfer instruction are provided. And the determination means 114
Is a first address judgment that outputs a judgment result that a predetermined condition is satisfied, when both the address of the data to be moved and the address of the movement destination are boundary addresses of transfer units forming a block. Means 123, second address determining means 124 for determining whether or not the data to be moved is stored in one block of the memory based on the address of the data to be moved, and based on the address of the moving destination. And a third address determining means 125 for determining whether or not the moved data is stored in one block, and the movement control means 115 stores the data to be moved in one block. According to the determination result indicating that the data corresponding to the access unit is output to the memory, the determination result indicating that the data to be moved spans two blocks. According to the above, the access control means 126 for instructing to output the data of the access unit corresponding to the memory for each block divided into two times, and the determination that the data to be moved are stored in one block According to the result, a write instruction is sent to all of the plurality of moving data holding units 121 at the same time, and according to the result of the determination that the data to be moved spans two blocks,
Based on the distribution of the movement target data in the two blocks, the plurality of movement data holding means 121 are divided into two groups, the fetch operation control means 127 for sending a write instruction for each group, and the data after movement is one block. In response to the determination result that the transfer unit 122 stores the data for the access unit held in the plurality of moving data holding units to the transfer bus 122, a transfer instruction for collectively transferring the data is sent. In accordance with the result of the determination that the blocks are to be straddled, the plurality of moving data holding units 121 are divided into two groups based on the distribution of the moved data in the two blocks, and the transfer bus 122 is divided into access unit units. And a transfer instructing means 128 for sending out a transfer instruction to transfer the data for each group twice. To.

FIG. 2 is a principle block diagram of the memory control device according to the third aspect. According to a third aspect of the present invention , in the memory control device according to the first aspect, the memory 101 is a buffer memory provided in the central processing unit 103, and a part of the data in the main storage device 104 is stored in the storage location. Corresponding to the main memory device 104 to the memory 101.
Move-in data holding means 131 that mediates writing of data to and from the move-in data holding means 131
Input the input data into the fetch data holding means 111
Bypass path 135 for
Data to be moved based on the address of the data to be moved.
Data is stored in the memory 101,
If the data to be moved is not stored in the memory 101,
In this case, the second condition regarding the address of the data to be moved
A fourth address determination hand that outputs a determination result that satisfies
And a stage 132, the movement control unit 115, in response to a predetermined condition is satisfied indicating that the determination result, according to the move-in data holding means to the effect that satisfies the second condition corresponding to 131 the determination result, a move Data is stored in the data storage means 131 .
Second access control means 133 for instructing to output the held data to the bypass path 135, and a second condition
Depending on that determination result satisfying, Fe in the transfer means 113
Switch data holding means 111 to store data holding means 1
Second transfer instruction means 13 for instructing data transfer to 12
4 is provided.

[0026]

According to the invention of claim 1, the movement control means 1 is operated in accordance with the result of the judgment by the judgment means 114 that the predetermined condition is satisfied.
By activating the transfer operation by the transfer unit 113, the transfer target data can be transferred from the fetch data holding unit 111 to the store data holding unit 112 via the transfer unit 113.

As a result, it becomes possible to release the arithmetic means from the processing of the movement instruction and execute the processing of the movement instruction and the arithmetic processing in parallel. On the other hand, when the predetermined condition is not satisfied, the movement processing of data is performed for each transfer unit via the calculation means in accordance with the instruction from the movement control means 115 as in the conventional case.

According to the second aspect of the present invention, when the first address determining means 123 determines that the predetermined condition is satisfied, the determination results by the second address determining means 124 and the third address determining means 125 are Accordingly, the first access control means 126, the fetch operation control means 127, and the first transfer instruction means 128 operate, respectively, and the operation of the moving data holding means 121 and the transfer bus 122 that configure the memory 101 and the transfer means 113. Is to control.

As a result, the data read from the memory 101 is transferred from the fetch data holding means 111 to the store data holding means 1 according to the relationship between the position of the data to be moved before and after the movement and the block in the memory 101.
It is possible to transfer to 12 via the transfer means 113 with the minimum number of flows.

In particular, when the data to be moved which is stored in one block is moved so as to be stored in one block even after the movement, the first address is determined according to the determination result of the second address determination means 124. The access control means 126 and the fetch operation control means 127 collectively read the data for each access unit, and the move data holding means 121
Will be written at the same time. Further, in this case, the first transfer instructing means 128 causes the plurality of movement data holding means 121 in accordance with the determination result of the third address determining means 125.
The data for the access unit held in is collectively transferred to the store data holding unit 112. That is, in this case, the data for one access unit can be collectively moved by one fetch flow and one store flow.

On the other hand, when the data to be moved contained in one block is moved so as to extend over two blocks, or the data to be moved distributed over two blocks is set to 1 When moving so as to fit in one block, the store flow or the fetch flow is divided into two and executed, and the fetch data control unit 127 and the first transfer instruction unit 128 respond accordingly.
By controlling the movement data holding means 121 by grouping, it is possible to move the data for one access unit with the minimum number of flows.

That is, in the case of moving data to be moved which is stored in one block so as to straddle two blocks, the move instruction may be executed by one fetch flow and two store flows. Is possible,
When moving data to be moved that is distributed over two blocks so as to be contained in one block, 2
A move instruction can be executed by one fetch flow and two store flows.

As described above, by reducing the number of flows required for executing the move instruction, it is possible to speed up the data move process in the memory. According to the third aspect of the present invention , for example, from the main storage device 104 to the buffer memory.
When a move-in to the memory 101 which is a memory occurs
To, to be moved by the fourth address determination means 132
The second condition regarding the address of the data is satisfied.
Is, depending on the determination result, the second movement control means 115
Access control means 133 is a move-in data holder.
The data moved into the stage 131 is bypassed to the bypass path 13
5 is instructed to output. This makes the move index
The data that has been moved in is stored in the memory.
101 to bypass the fetch data holding means 111
Retained. Therefore, the second condition described above is satisfied.
In accordance with the determination result to the effect, the second control of the movement control means 115 is performed.
The sending instruction means 134 stores the fetch data in the transfer means 113.
Transfer from holding means 111 to store data holding means 112
Is instructed to move in the memory 101.
To move-in data holding means 131 as data to be stored
1 access unit of data that is held, fetch data
The data can be collectively transferred to the store data holding means 112 via the data holding means 111 .

Thus, it did not exist in the memory
When processing move commands for data, move
Data from the main storage device 104 to the data storage means 131.
Before reflecting the imported data in the memory 101,
Switch data holding means 111 for fetching and transferring means 11
Since the data can be passed to the store data holding means 112 via 3, the data transfer processing in the memory can be speeded up.

[0035]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3 shows a block diagram of an embodiment of a central processing unit to which the memory control device of claim 1 is applied.

In FIG. 3, the central processing unit is the same as the conventional central processing unit shown in FIG.
02a and 202b corresponding to the two move data registers 211a and 211b and the store data buffer registers 210a and 210b corresponding to the two selectors 21
2a and 212b are added, these selectors 212a,
212b is configured to select either the data from the corresponding move data registers 211a and 211b or the data from the store data register 209 in accordance with the instruction from the instruction control unit 204.

In FIG. 3, solid line arrows connecting the respective parts indicate a data bus having a width of 8 bytes, and dotted line arrows indicate control signals. The fetch data registers 202a and 202b correspond to the fetch data holding unit 111, and the store data buffer registers 210a and 210b correspond to the store data holding unit 112.

The above-mentioned move data register 211a,
211b and fetch data register 202 with these
The data bus connecting the a and 202b corresponds to the moving data holding means 121, and the corresponding selector 212 from the move data registers 211a and 211b.
Store data buffer register 2 via a, 212b
The transmission path of the data to 10a and 210b is the transfer bus 1
It corresponds to 22.

That is, each of these units realizes the function of the transfer means 113. Here, as shown in FIG. 4, the buffer memory 201 is divided into a plurality of blocks each made up of N (8 in the figure) transfer units.
The access processing to 01 is configured so that the access unit for each block is the upper limit.

In each block shown in FIG. 4, N transfer units are consecutively stored in the order shown by numbers 1 to 3, and the transfer unit to which consecutive numbers are given is 1.
It can be read as one access unit. That is, the access unit (a) and the access unit (b), which are the transfer units shown by hatching in FIG.
It can be read by one fetch operation.

Further, in FIG. 3, the instruction control unit 204
Includes an address determination unit 214 corresponding to the determination unit 114, and the enable signal transmission unit 215 and the operation control unit 2 according to the determination result by the address determination unit 214.
16, the selector control unit 217 and the read control unit 218 perform their respective operations, whereby the movement control unit 1
It is configured to realize 15 functions.

When processing the data move command, the address determining unit 214 first operates as the first address determining means 123 described in claim 2, and the start address of the data to be moved and the data It is determined whether or not the start address of the move destination is a boundary address of the transfer unit (8 bytes in this case). If a positive determination is obtained as a result of this determination, the second address determination means 12
It operates as the fourth and third address determination means 125,
It is configured to determine whether or not the data to be moved is stored in one block at the move source or move destination.

Hereinafter, the fact that the data to be moved is stored in one block at the movement source is referred to as a first condition, and that the data to be moved is stored in one block at the movement destination is referred to as a second condition.

Further, in the instruction control unit 204, the enable signal transmission unit 215 and the selector control unit 217 operate according to the determination result by the first address determination unit 123, and the enable signal transmission unit 215 causes the write enable. The signal is sent to the move data registers 211a and 211b or the operand word register 206, and the selector control unit 217 is configured to control the selection operation by the selectors 212a and 212b.

On the other hand, the arithmetic control unit 216 sends an instruction to the arithmetic circuit 207 to perform the transfer process in accordance with the result of the determination that the source and destination addresses are not the boundary address of the transfer unit. Has become.

The read control unit 218 corresponds to the first access control means 126 and is the above-mentioned first access control unit 126.
Depending on the judgment result of the condition of
The data reading operation from 01 is controlled.

The read control unit 218 instructs, in accordance with the result of the determination that the first condition is satisfied, to read the data to be moved from the corresponding block in batches of the access unit at a time. In accordance with the result of the determination that the condition (3) is not satisfied, it may be instructed that the data to be moved is read out for each block divided into two fetch flows.

Further, the timing control section 219 fulfills the function of the fetch operation control means 127 by controlling the write timing to the move data registers 211a and 211b in accordance with the result of the decision on the first condition. The function of the first transfer instructing means 128 is achieved by controlling the write timing to the store data buffer registers 210a and 210b according to the result of the determination on the second condition.

The timing control unit 219 simultaneously instructs the write data registers 211a and 211b to perform the write operation according to the determination result that the first condition is satisfied, and the first condition is not satisfied. Depending on the judgment result,
The write operation to the move data registers 211a and 211b may be indicated in two steps.

Further, in accordance with the result of the determination that the second condition is satisfied, the timing control unit 219 simultaneously instructs the store data buffer registers 210a and 210b to perform the write operation, and the second condition is not satisfied. Depending on the determination result, the store data buffer registers 210a, 210b
It is sufficient to indicate the write operation to the two times.

Here, the timing control unit 219 may instruct the above-mentioned write operation to each register in accordance with the timing of each cycle for pipeline controlling the fetch flow and the store flow, as will be described later.

In the following, when the address of the data to be moved and the address of the transfer destination are both boundary addresses of the transfer unit and the data transfer process of one access unit, that is, 16 bytes, is performed, the first condition and the first condition are satisfied. The data movement operation for each case will be described by classifying the cases according to whether or not the two conditions are satisfied.

FIG. 5 is an explanatory view of the data moving operation by the memory control device of the present invention. First, if the source and destination addresses are both transfer unit boundary addresses, the enable signal transmission unit 215 determines whether the move data register 211a,
The write enable signal is sent to 211b, and the selector control unit 217 instructs the above selectors 212a and 212b to select the data from the move data registers 211a and 211b.

As a result, the fetch data register 20
2a and 202b to move data registers 211a and 2b
A path is formed to the store data buffer registers 210a and 210b via 11b and the selectors 212a and 212b.

That is, the enable signal transmitting section 215 and the selector control section 217 are respectively arranged in the move data registers 211a, 211b and the selectors 212a, 21.
By controlling 2b, the fetch data register 2
A transfer bus 122 from 01a, 201b to the buffer store word registers 203a, 203b via the store data buffer registers 210a, 210b described above is formed, and data can be moved via this transfer bus 122.

When both the first condition and the second condition are satisfied, the read control unit 218 causes the buffer memory 2 to operate according to the determination result of the address determination unit 214.
01 is instructed to collectively output the data for the corresponding access unit as the data to be moved.

In response to this, the fetch flow indicated by the code in FIG. 5A is started, and data of one access unit (16 bytes) is collectively written in the fetch data registers 202a and 202b in the buffer access cycle. Be done.

At this time, the timing control unit 219 operates as the fetch operation control unit 127, holds the received data in the fetch data registers 202a and 202b until the end of the read cycle, and then the next cycle. Move data registers 211a, 211
It suffices to indicate to b that the data is to be collectively transmitted.

Further, one cycle after the start of the fetch flow described above, the store flow indicated by the symbol in FIG. 5A is started, and the same write address check processing as in the conventional case is performed, and then the buffer memory 201 Write process.

At this time, the timing control unit 219 determines that the first
For instructing the write operation to the store data buffer registers 210a and 210b at the same time in the priority cycle (Ps) of the store flow, and further for the buffer store word register 203a in the next tag read cycle (Ts). , 203b may be simultaneously instructed to write.

As a result, the buffer memories 201 to 1
The data for one access unit is collectively read and sent to the store data buffer registers 210a, 210b via the move data registers 211a, 211b, and the data for one access unit is collectively read for the buffer memory 201.
Can be written on.

That is, the data movement processing for one access unit (16 bytes) can be completed by one fetch flow and one store flow.
As can be seen from (a), the number of cycles required as a whole can be reduced to 8 cycles to shorten the time required to process the move instruction.

Since the data movement path used at this time does not pass through the arithmetic circuit 207, it is not necessary to stop the operation of the arithmetic circuit 207 for the data movement processing.
That is, it is possible to release the arithmetic circuit 207 from the moving process and execute the data moving process and other arithmetic processes in parallel, so that the performance of the data processing device can be improved.

In FIG. 5, the figure showing the period in which the move data registers 211a and 211b hold data is the move data registers 211a and 211b.
Indicates that the retained data is retained until it is overwritten with new data.

On the other hand, when the data to be moved is distributed over two blocks at the move source or move destination, the fetch process or store process for one access unit of data is collectively executed in one flow. It is not possible.

First, when only the second condition is satisfied, the read control unit 218 divides the buffer memory 201 into two fetch flows indicated by the symbols in FIG. It suffices to instruct the read processing of the data for the access unit and collectively store the read data in one store flow (indicated by a symbol in FIG. 5B).

In this case, the timing controller 219
At the timing of the read cycle of each of the two fetch flows described above, the corresponding move data register 21
A writing instruction is sent to each of 1a and 211b.

That is, in the read cycle of the fetch flow indicated by the code, the move data register 211
The write instruction may be sent to a, the write instruction may be sent to the move data register 211b after shifting by one cycle.

In this way, when the data to be moved spans two blocks, the move data registers 211a and 211b are divided into two groups according to the distribution, and the write operation to each group is performed. Can be controlled.

As a result, the fetch data register 20
Since the read data is sequentially written to the move data registers 211a and 211b via the 2a and 202b, the move data registers 211a and 211b are read in the read cycle of the fetch flow indicated by the symbol.
Therefore, data for one access unit will be prepared.

Therefore, in the next cycle, the timing control unit 219 sends a write instruction to the store data buffer registers 210a and 210b at the same time to collectively store the data for one access unit to the store data registers 210a and 210b. It is possible to write and write to the buffer memory 201 via the buffer store word registers 203a and 203b.

In this case, since the move process is performed by the two fetch flows and the one store flow, the time required to process the move instruction is set to JP-A-61-26066.
This is the same as the case of the technique of Publication No. 1 and is 9 as a whole.
Cycle time is required.

However, since the data movement process is performed via an independent path that does not pass through the arithmetic circuit 207, it is possible to perform the data movement process in parallel with other arithmetic processes. The performance of the processing device can be improved.

When only the first condition is satisfied, as shown in FIG. 6 (a), one access unit of data is fetched by one fetch flow (indicated by a symbol in FIG. 6 (a)). Read in batch with two store flows (Fig. 6
It should be written separately in (a).

In this case, in the fetch operation of the data to be moved, the read control unit 218 and the timing control unit 219 operate in the same manner as when the above-mentioned first and second conditions are satisfied, and the read from the buffer memory 201 is started. It is sufficient to control the read processing of 1 and the write operation of data to the move data registers 211a and 211b.

In addition, in the store operation of the data to be moved, the timing control section 219 writes into the store data buffer registers 210a and 210b separately twice in the priority cycle (Ps) of the two store flows. In the tag read cycle (Ts) following this, the write instruction may be sent to each of the buffer store word registers 203a and 203b twice.

In this way, the timing controller 219
By controlling the store data buffer register 210 and the buffer store word register 203 by dividing them into two groups, the data for one access unit collectively read by one fetch flow from one block is divided into two groups. It can be divided and stored across two blocks.

In this case, since the move process is performed by one fetch flow and two store flows, the time required to process the move instruction is set to JP-A-61-26066.
This is the same as the case of the technique of Publication No. 1 and is 9 as a whole.
Cycle time is required.

However, since the data movement processing is performed via an independent path that does not pass through the arithmetic circuit 207, it is possible to perform the data movement processing in parallel with other arithmetic processing. The performance of the processing device can be improved.

On the other hand, when both the first condition and the second condition are not satisfied, as shown in FIG. 6B, the two fetch flows indicated by the symbols and in FIG. The data for the access unit is divided into two groups to perform the fetch operation, and the move data registers 211a and 211a
When data for one access unit is prepared in b, the data in FIG.
The store operation may be performed for each group according to the two store flows indicated by the symbols and in (b).

In this case, since the move processing is performed by the two fetch flows and the two store flows, the time required to process the move instruction is the same as that in the conventional example, and the total time is 10 cycles. Requires.

However, since the data movement processing is performed via an independent path that does not pass through the arithmetic circuit 207, it is possible to perform the data movement processing in parallel with other arithmetic processing. The performance of the processing device can be improved.

As described above, the read control unit 218 and the timing control unit 219 operate according to the determination results for the first condition and the second condition, so that the first access control unit 126 and the fetch operation are performed. By implementing the functions of the control unit 127 and the first transfer instruction unit 128, it becomes possible to execute the move command with the minimum number of flows according to the distribution of the data of the move target at the move source and the move destination.

On the other hand, when the data move destination address is not the boundary address of the transfer unit, the enable signal sending unit 215 sends a write enable signal to the operand word register 206, and the operation control unit 216 operates as in the conventional case. , Instructs the arithmetic circuit 207 to stop the operation,
The arithmetic circuit 207 is put in the through state. In addition, the selector control unit 217 instructs the selectors 212a and 212b to select the data from the store data register 209.

In this case, the fetch data register 20
Store data buffer registers 210a and 210b from 2a and 202b via the arithmetic circuit 207 as in the conventional case.
A path is formed, and data transfer processing is performed for each transfer unit (that is, 8 bytes) as in the conventional case. By the way, in the above-mentioned embodiment, the access unit of the buffer memory 201 is 8 bytes × for simplicity of explanation.
Although the case of being formed with 2 (that is, 16 bytes) has been described, the present invention is not limited to this, and is also applied to the case where the access unit is formed with three times or more of the transfer unit (for example, 8 bytes) by the internal bus. be able to.

For example, when the transfer unit is n bytes and the access unit is formed by n bytes × m (m> 2),
m fetch data registers 202 ₁ , ..., 202 _m
And m buffer store word registers 203 ₁ ,
, 203 _m corresponding to m move data registers 211 ₁ , ..., 211 _m and store data buffer registers 210 ₁ , ..., 211 _m , a data bus connecting them, and each move data register 211. The memory control device may be configured by including the corresponding selectors 212 ₁ , ..., 212 _m .

In this case, the address determination unit 214
Is how, when a determination result that the first condition or the second condition is not satisfied is obtained, the data of the corresponding access unit is distributed to the two blocks at the source or destination. The timing control unit 219 may control the move data register 211 or the store data buffer register 210 by grouping based on this information.

Further, according to the memory control device of the present invention,
It is also possible to process data movement instructions within the main memory. By the way, the buffer memory 20 in the central processing unit
If the data to be moved does not exist in 1, the move-in process of reading the corresponding data from the main storage device is performed and the corresponding data is written in the corresponding area of the buffer memory 201, and then the corresponding data is moved. The process of moving to the previous address was being performed. Data read from the main storage device by this move-in processing (hereinafter referred to as move-in data) is temporarily held in a move-in data register provided in the central processing unit, and is stored in the buffer store word register 203a for each transfer unit. , 203b
Was written in the buffer memory 201 via the.

A method of accelerating the processing of a move instruction for move-in data (hereinafter referred to as move-in data) by applying the memory storage device of the present invention will be described below.

FIG. 7 is a block diagram of an embodiment of a central processing unit to which the memory control device of claim 3 is applied. 7, the memory control device is different from the memory control device shown in FIG. 3 in that a move-in data register (MIDR) 221 and a data bus 222 connecting the move-in data register 221 and the two fetch data registers 202a and 202b.
It has a configuration with and added. In addition, this data bus
222 corresponds to the bypass path 135 shown in FIG.
It is a thing.

This move-in data register 221 is
It corresponds to the move-in data holding unit 131 and has a capacity of at least one access unit (for example, one block = n × N bytes), and the main storage device 1
04 and the move-in data register 221 are connected via a bus for receiving the data and temporarily holding the data.

The above-mentioned data bus 222 has a width of one access unit, and the move-in data register 22
Of the access unit data output from 1, the first 8 bytes are sent to the fetch data register 202a and the second 8 bytes are sent to the fetch data register 202b.

Further, in the instruction control unit 204, the address determination unit 214 operates as the fourth address determination unit 132 described in claim 3, and the corresponding data is stored in the buffer memory based on the address of the data to be moved. 20
It is determined whether it is held at 1.

When the address determination unit 214 obtains a determination result indicating that the corresponding data is not held, the read control unit 218 requests the main storage device 104 to perform move-in processing of the corresponding data. In addition, the enable signal transmission unit 215 and the selector control unit 217 are configured to set the transmission path via the move data registers 211a and 211b.

In response to the request from the read control unit 218 described above, the main storage device 104 outputs the data of the block including the corresponding access unit and sets it in the move-in data register 221.

In this case, as shown in FIG. 8, the read control unit 218 starts the fetch flow at the timing when the buffer access cycle starts when the data of the access unit corresponding to the move-in data register 221 is prepared. In addition, in this buffer access cycle, the output of the block corresponding to the move-in data register 221 may be indicated.

As a result, in the buffer access cycle of the fetch flow shown in FIG. 8, the data from the move-in data register 221 is written into the fetch data registers 202a and 202b instead of the data from the buffer memory 201. .

In this way, the fetch data register 2
One block of data written in 02a, 202b is held until the end of the read cycle, and is written in the move data registers 211a, 211b in the next cycle, as in the above-described movement processing in the buffer memory 201.

In addition, the store flow is started one cycle after the start of the fetch cycle described above, and in the priority cycle (Ps) of this store flow, the data to be moved for one block is batch-stored in the store data buffer registers 210a and 210b. Then, in the tag read cycle (Ts), the buffer store word registers 203a and 203b may be similarly written.

In this way, the data to be moved in the move-in data register 221 can be moved directly to the destination address of the buffer memory 201. As a result, the processing of the move instruction can be executed before the entire move-in data is reflected in the buffer memory 201, and the processing of the move instruction accompanied by the move-in from the main storage device 223 can be speeded up. .

[0101]

As described above, according to the present invention, the movement of the transfer means is controlled by controlling the operation of the transfer means based on whether the address of the data to be moved and the address of the movement destination satisfy a predetermined condition. Since the target data can be moved from the movement source to the movement destination with the minimum number of flows, it is possible to speed up the processing of the movement instruction in the memory and improve the performance of the data processing device. .

When the transfer instruction is processed by the transfer means, the arithmetic means can be released from the movement processing, so that the movement processing and other arithmetic processing can be executed in parallel, The performance of the data processing device can be improved.

Further, in the invention of claim 3, the transfer means can directly transfer the necessary data from the move-in data holding means to the store data holding means.
Without waiting for the move-in data to be reflected in the memory,
It is possible to process a move command targeting data that does not exist in the memory.

[Brief description of drawings]

1 is a principle block diagram of a memory control device according to claim 1 and claim 2;

FIG. 2 is a block diagram of the principle of the memory control device of claim 3;

FIG. 3 is a configuration diagram of an embodiment of a central processing unit to which the memory control device of claims 1 and 2 is applied.

FIG. 4 is a configuration diagram of a buffer memory.

FIG. 5 is an explanatory diagram of a data movement operation.

FIG. 6 is an explanatory diagram of a data movement operation.

FIG. 7 is a configuration diagram of an embodiment of a central processing unit to which the memory control device of claim 3 is applied.

FIG. 8 is an explanatory diagram of a data movement operation.

FIG. 9 is a diagram showing a configuration example of a central processing unit to which a conventional memory control device is applied.

FIG. 10 is an explanatory diagram of a data movement operation.

FIG. 11 is a diagram showing another configuration example of a central processing unit to which a conventional memory control device is applied.

FIG. 12 is an explanatory diagram of a data movement operation.

[Explanation of symbols]

101 memory 102 computing means 103 Central processing unit 104 main memory 111 fetch data holding means 112 Store data holding means 113 transfer means 114 determination means 115 Movement control means 121 Moving data holding means 122 transfer bus 123 First Address Judging Means 124 Second Address Judging Means 125 Third Address Judging Means 126 First Access Control Means 127 Fetch operation control means 128 first transfer instruction means 131 Move-in data holding means 132 Fourth Address Judging Means 133 second access control means 134 Second transfer instruction means 201 buffer memory 202 Fetch data register 203 Store data register 204 Command control unit 205,212,302 selector 206 Operand Word Register (OWR) 207 arithmetic circuit 208 Result register (RR) 209 Store data register (STDR) 210 Store data buffer register (STDB) 211 Move data register (MVCR) 214 address determination unit 215 Enable signal transmitter 216 Operation controller 217 Selector control unit 218 Read Control Unit 219 Timing control unit 221 Move In Data Register 222 data bus 301 Movement data holding register (STDBB)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 61-206061 (JP, A) JP 59-229659 (JP, A) JP 52-155936 (JP, A) JP 51- 101435 (JP, A) JP 5-81124 (JP, A) JP 61-165149 (JP, A) JP 1-111245 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/00-12/08 G06F 13/16-13/18 G06F 9/30

Claims (3)

(57) [Claims] 1. An access process is performed for each access unit composed of a plurality of transfer units with respect to a memory whose storage area is divided into blocks each composed of a plurality of transfer units each composed of a plurality of bytes. A central processing unit, which is a memory control device for controlling, which receives data for each transfer unit via the memory control device and writes the result of the instructed arithmetic processing to the memory via the memory control device. A plurality of fetch data holding means for holding the data for one access unit read from the memory by dividing the data into the transfer unit, and the one access unit for writing in the memory. A plurality of store data holding means for holding the data divided into the transfer units; Between means and said plurality of storage data holding means, a transfer means for transferring the data directly to the transfer address of the data to be moved that is specified by the movement command
Judge whether the destination address and the specified condition meet
And the transfer result according to the determination result that the predetermined condition is satisfied.
Instructs the transfer operation by the sending means, and in the other cases, the above calculation
And a movement control means for instructing a transfer operation via the means.
A memory control device characterized by the above. 2. The memory control device according to claim 1, wherein the transfer means includes a plurality of movement data holding means for holding the data of the transfer unit held in the corresponding fetch data holding means in response to the write instruction. A transfer bus for transferring the data of the transfer unit held in each of the plurality of moving data holding means to the corresponding store data holding means in accordance with a transfer instruction, and the judging means is a moving target. A first address determining unit that outputs a determination result indicating that a predetermined condition is satisfied, when both the address of the data and the address of the transfer destination are boundary addresses of transfer units forming a block; A second address for determining whether the data to be moved is stored in one block of the memory based on the address of the data to be moved. And a third address determining means for determining whether or not the data after the movement can be stored in one block based on the address of the movement destination. According to the determination result that the target data is stored in one block, the memory is instructed to output the data of the corresponding access unit, and the transfer target data is spread over two blocks. 1st access control means for instructing to output the data corresponding to the access unit corresponding to the memory in two times for each block according to the determination result indicating that the data to be moved is 1 In response to the determination result that the data is stored in one block, a write instruction is simultaneously sent to all of the plurality of moving data holding units, and the data to be moved is stored in two blocks. In accordance with the result of the determination that the data is straddling, the plurality of pieces of movement data holding means are divided into two groups based on the distribution of the movement target data in the two blocks, and a write instruction is sent for each group. In accordance with the fetch operation control means and the determination result that the data after the movement is stored in one block, the data for the access unit held in the plurality of movement data holding means is collectively transferred to the transfer bus. A transfer instruction to that effect is sent, and in accordance with the result of the determination that the data after the movement spans two blocks, the
The plurality of moving data holding means are divided into two groups based on the distribution of the moved data in one block, and the access unit data is divided into two groups for the transfer bus. A memory control device comprising: a first transfer instruction means for sending out a transfer instruction to transfer. 3. The memory control device according to claim 1, wherein the memory is a buffer memory provided in the central processing unit, and stores a part of the data in the main storage device corresponding to the storage location. and and a move-in data holding means for mediating writing data in the memory from the main memory, the data output from the move-in data holding means
Bypass for inputting the fetch data holding means 2
Route and address of data to be moved specified by the move command
The data to be moved is stored in the memory according to
It is determined whether or not the data to be moved is
If the data to be moved is not stored in memory,
Outputs the judgment result that the second condition regarding the address is satisfied.
A fourth address determination means for force, movement control means, in response to that the determination result satisfies the second condition, the data held to said beam <br/> Buindeta holding means
Depending on the second access control means for instructing to output to the bypass path and the result of the determination that the second condition is satisfied, the transfer means is instructed from the fetch data holding means to the store data.
A memory control device comprising: second transfer instructing means for instructing data transfer to the data holding means .