JP3324770B2 - Semiconductor wafer for burn-in and test of semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the testing and burn-in of semiconductor devices and, more particularly, to a method of testing and burning-in an entire wafer before dicing.

[0002]

2. Description of the Related Art Most MOS semiconductor products require burn-in and testing during manufacturing to avoid electric field failure due to defective devices. In one procedure, packaging and burn-in are performed after detecting and selecting a bad chip using stress by probing at high voltage.

[0003] High pin count contact assemblies similar to those used in conventional wafer probe systems are difficult to maintain good contact with all 3000-6000 bond pads during burn-in. Not practical. This period is between 20 and 120 hours. Such a high pin count burn-in probe configuration is expensive, if not impossible.

Although reusable flexible contact assemblies manufactured using plating techniques are less expensive than individual pin probes, such contacts are used for bare aluminum bond pads due to the natural oxidation of aluminum bond pads. I can't. The use of this type of contact assembly generally requires bond pad bumping and oxide removal steps. However, this processing method is extremely sensitive to contact pressure and is considered impractical.

According to the present invention, a reliable contact is made to each bond pad of each semiconductor on the wafer. Can be used in a multilayer structure.

In a multi-layer structure, contacts are formed around the edge of the wafer. A first layer of a plurality of conductors is formed on the insulating layer over the wafer surface. There is one conductor for each bond pad on each device under test. A second metal conductor layer is formed on the first conductor layer. A second lead layer interconnects the common bond pads (eg, pin 1 of each device) with each other and connects to contacts on the edge of the wafer. In this way, the semiconductor devices in a row of devices on the wafer are effectively connected in parallel. This burn-in method is extremely useful for a memory device that can simultaneously activate all address lines and input lines. This first layer conductor can be connected to a second layer conductor via a phase link. These links can later be cut by a laser to "disconnect" inactive or shorted devices.

[0007]

[0008] A burn-in voltage can be connected to the device while the device is on the wafer. After performing the burn-in, the burn-in metal interconnect structure is removed. A test for identifying a defective device can be performed to mark the defective device with a scrap mark. Next, the device is separated and mounted, and the final test is performed.

[0009]

FIG. 1 shows a semiconductor wafer 11 on which a plurality of semiconductor devices 12 are formed. The wafer 11 has a margin 13 without devices around its edge. As will be described later, test points for providing test access and performing burn-in by providing contact access with the semiconductor device are formed on the margin 13.

FIG. 2 is a partially enlarged view of the wafer 11 showing three semiconductor devices 12 having the bond pads 14. Bond pads 14 are contacts for device 12.

FIG. 3 shows a first step of providing a connection interface to each semiconductor device 12. Over each individual semiconductor device, a first interconnect layer is formed on the wafer surface. It is performed in the following procedure. An adhesive such as thermoplastic is applied on the wafer, and then an insulating agent such as polyimide is applied on the adhesive. Next, an opening is provided on each pound pad 14 by patterning the insulating material. A first metal layer such as TiW is provided on the insulating material, and then a second metal such as copper is provided. Next, the metal layer is patterned and etched to fuse-link conductor 15, an exposed conductor for later cutting and isolating the shorted device,
To form One end of each conductor 15 is connected to the device bond pad 14. A via pad 16 is formed at the end of each conductor 15 opposite to the side connected to the device bond pad.

FIG. 4 shows a second step of providing a connection interface for each semiconductor device on the wafer 11. Continuing the process, an insulator is provided on the wafer to cover the conductors 15 and the via pads 16. A via pattern is etched on the polyimide. A second metal layer is applied over the insulator, for example, by a copper layer following the TiW layer.
The second metal layer is patterned and etched to form interconnect conductors 17. The polyimide is also etched during this masking step, exposing a portion of the conductor 15 (not shown). Each of these conductors is connected to a via pad of each device in a particular column. For example, the conductor 15 connected to the via pad is connected to each bond pad of each device. For example, conductor 17a is connected to bond pads P ₁ , P ₂ , and P ₃ by conductors 15 and via pads 16. Each conductor 17 is connected to a test point 18 located in an unpatterned area of the wafer 11.

Inactive devices can be located by preliminary testing of the devices on the wafer. The inactive device is connected to the connector 1 of the device by, for example, a laser beam.
5 is cut off electrically. After performing a preliminary test for an open or short circuit, burn-in is performed on the remaining devices to determine if there are any defective devices. After burn-in and preliminary testing, the two conductor layers 15, 17 are removed and the wafer is divided and assembled into individual devices.

[0014]

[0015]

One advantage of the interconnect system of the present invention is that pre-tests are performed in parallel before dividing the wafer into individual devices, and then the interconnects are removed to ultimately assemble and test the individual devices. That is what you can do. Testing devices in wafer form requires contacting the "output" pin of each device. This is accomplished by a probe card or additional metal layer connecting the output pins to a more convenient location on the wafer.

With respect to the above description, the following items are further disclosed. (1) In a semiconductor device burn-in and test interconnection system before separation from a semiconductor wafer,
The system includes a semiconductor wafer having a plurality of semiconductor devices in a matrix configuration each having a plurality of bond pads, and at least one plurality of electrically isolated semiconductor wafers on the wafer isolated from the devices and bond pads. Connected to the plurality of electrically separated conductors, the electrical connection between the plurality of electrically separated conductors and corresponding bond pads on each of the devices in a row, and the plurality of electrically separated conductors. An interconnect system comprising a plurality of test points on the wafer.

(2) The interconnect system of paragraph (1), wherein the connection between each of the plurality of separated conductors and a corresponding bond pad on each of the devices in a row is a fuse link. .

(3) The interconnect system of paragraph (1), further comprising a second layer of a plurality of connectors insulated from the at least one layer of the plurality of electrically isolated conductors; The interconnect system of claim 1, wherein each conductor of the interconnect is connected via a via to one of the plurality of electrically isolated connectors of the first layer.

(4) The interconnect system of paragraph (3), wherein each conductor of the plurality of interconnects of the second layer is connected to a bond pad on the wafer via a fuse link. .

(5) An interconnect system for burn-in and test of semiconductor devices before separation from the semiconductor wafer, the system comprising a plurality of semiconductor devices each having a plurality of bond pads and arranged in a matrix. A first plurality of electrically isolated conductors on the wafer insulated from the device and the bond pads; and a second plurality of electrically isolated conductors on the wafer insulated from the first layer of the plurality of electrically isolated conductors. A plurality of electrically isolated conductors of a layer and an interconnect between each of the first layer electrically isolated conductors and one of the plurality of electrically isolated conductors of the second layer And a plurality of contact test points on the wafer connected to the respective conductors in the second plurality of electrically isolated conductors.

(6) The interconnect system according to paragraph (5), wherein the interconnect between each of the plurality of test points and the bond pad is a fuse link.

(7) In the interconnect system of paragraph (5), the plurality of electrically isolated conductors insulated from the device and connected to bond pads on the device and contact test points on the wafer are connected to the wafer. An interconnect system with only one layer above.

(8) In a method of forming an interconnect system for burn-in and test of a semiconductor device before being separated from a semiconductor wafer, the method includes the following steps, namely, on a semiconductor wafer surface and a semiconductor device formed thereon. Forming a layer of insulating material, each semiconductor device having a plurality of bond pads, the insulating layer having an opening on the bond pad, and extending through the opening in the insulating layer to contact the bond pad on the semiconductor device; Depositing a first metal layer on the insulating layer, etching the first metal layer to form a plurality of conductors, forming test point contacts at locations around the semiconductor wafer that do not include the semiconductor device, Interconnecting a contact with each of a plurality of conductors connected to the bond pad.

(9) The method of (8), further comprising the step of forming a fuse link connecting the bond pad on the semiconductor device to the plurality of conductors.

(10) In the method described in (8), a second insulating layer is formed on the metal layer after the etching, and a second metal layer is deposited on the second insulating layer after forming the via. Forming a second plurality of conductors by etching the second metal layer and connecting the conductor of the first metal layer to the conductor of the second metal layer.

(11) The method according to (10), wherein the conductor formed from the first metal layer is connected to a conductor formed from the second metal layer via a via. Method for forming an interactive system including:

(12) The method of (8), further comprising providing an adhesive layer prior to depositing the insulating material.

(13) The method of paragraph (9), wherein the fuse link is a low-tolerance power conductor that opens in the event of overload during burn-in.

(14) The method according to paragraph (8), wherein the semiconductor devices are arranged on a semiconductor wafer, comprising the step of connecting a plurality of corresponding bond pads on each semiconductor device in a row in parallel, An interconnect system forming method.

(15) In a method of testing and burning in a plurality of semiconductor devices each having a plurality of bond pads before separating the semiconductor devices from the semiconductor wafer, the semiconductors are formed in a plurality of rows on the surface of the semiconductor wafer. The method comprises the following steps: connecting in parallel the corresponding bond pads on the semiconductor device for each column of semiconductor devices, and connecting each set of parallel-connected bond pads of a row of semiconductor devices to test point contacts on the semiconductor wafer. And applying a test and burn-in voltage to each test point contact so as to test and burn-in each semiconductor device.

(16) A test and burn-in method according to the above (15), further comprising a step of disconnecting each semiconductor to be tested as defective from parallel connection.

(17) In the method described in (16), each semiconductor input signal bond pad is connected in parallel by a fuse link, and a fuse device is opened by a laser beam to disconnect a defective device before performing burn-in. A test and burn-in method including steps.

(18) The test and burn-in method according to (15), further comprising the step of removing the interconnect circuit from the wafer before separating the device from the wafer.

(19) The interconnect system of paragraph (2), wherein the fuse link is a low-tolerance power material that opens in the event of overload during burn-in.

(20) An interconnect system and method for testing and burn-in of semiconductor device 12 prior to separation from the semiconductor wafer on which the device is formed, forming an interconnect layer of contacts 16 and conductors 17 on the device; It then involves performing test and burn-in on the device. Prior to further testing and burn-in, the defective device is disconnected from the conductor. Interconnects are removed before the devices on the wafer are separated and before further testing and packaging.

[Brief description of the drawings]

FIG. 1 is a view showing a semiconductor wafer on which a plurality of devices are formed.

FIG. 2 is an enlarged view of three devices on a wafer.

FIG. 3 shows three devices having a first conductor layer.

FIG. 4 shows the three devices of FIG. 3 with a second conductor layer.

[Explanation of symbols]

11 wafer 12 semiconductor devices 13 margin 14 bond pads 15 fuse link conductors 16 via pad 17 interconnect conductors 17a conductors 18 test points P ₁ bond pads P ₂ bond pads P ₃ bond pads

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-169435 (JP, A) JP-A-49-75279 (JP, A) JP-A-2-86142 (JP, A) JP-A 61-16943 87349 (JP, A) Hikaru 1-162260 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66

Claims (4)

(57) [Claims] 1. The method according to claim 1, further comprising the steps of:
A semiconductor wafer for performing burn-in and testing of an overlying semiconductor device, the semiconductor wafer having a plurality of semiconductor devices, wherein each semiconductor device defines a plurality of bond pads and a top surface of the semiconductor device. A plurality of first conductors on a wafer having a plurality of ends and further insulated from the semiconductor device;
A layer, wherein each of the plurality of conductors of the first layer extends over at least one of the semiconductor devices and is entirely within a perimeter of the semiconductor device; And further having a second layer of the plurality of conductors on the wafer, insulated from the first layer of the plurality of conductors,
Further comprising an interconnect between each conductor of the first layer of the plurality of conductors and one conductor of the second layer of the plurality of conductors, further comprising a plurality of test contacts on the wafer, wherein the test contacts Are connected to one of the conductors in the second layer of a plurality of conductors. 2. The semiconductor wafer according to claim 1, wherein said semiconductor devices are arranged in rows and columns on said semiconductor wafer. 3. The semiconductor wafer according to claim 2, wherein the conductors of the first layer of the plurality of conductors extend in the row direction, and the conductors of the second layer of the plurality of conductors extend in the column direction. Wafer. 4. The semiconductor wafer of claim 1, wherein each of the first layer conductors of a plurality of conductors has one bond pad via a low power conductor fuse link opened during overload during burn-in. Semiconductor wafer connected to.