JP3144509B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for simplifying a manufacturing process and improving the reliability of an element.

[0002]

2. Description of the Related Art A conventional method for manufacturing a MOSFET 1 will be described with reference to FIGS. First, an element isolation region and an element formation region are formed in an N-type silicon well 2 provided in a substrate by using a LOCOS method. Thereafter, a first ion implantation is performed to implant boron ions, which are P-type impurities, into the element formation region. Thereby, the characteristics of the channel region 10 are determined (FIG. 5A).

Next, a silicon oxide film 88 is formed by oxidation, and a polycide 55 is deposited thereon by chemical vapor deposition (CVD) (FIG. 5B). afterwards,
By patterning, a gate electrode 5 and a gate oxide film 8 are formed (FIG. 5C). Next, as shown in FIG. 6A, second ion implantation is performed using the gate electrode 5 as a mask, and boron ions, which are P-type impurities, are implanted into the surface of the N-type silicon well 2. Thereby, a P-type source 4 and a drain 3 are both formed.

Next, on the surface of the N-type silicon well 2,
The interlayer insulating film 28 is formed using low pressure chemical vapor deposition (LPCVD) (FIG. 6B). Thereafter, a photoresist is applied and patterned, a contact hole is opened, and contacts of the drain 3, the source 4, and the gate 5 are wired with aluminum in the contact hole, and MOSF is formed.
ET1 is completed (FIG. 6C).

[0005]

However, the above-described method of manufacturing the MOSFET 1 has the following problems. The steps of forming the source 4, the drain 3, and the channel region 10 require a total of two ion implantation steps, which is complicated. Further, when the second ion implantation is performed, the gate oxide film 8 is deteriorated due to the penetration of ions. Therefore, the reliability of the device may be reduced.

An object of the present invention is to provide a semiconductor device which solves the above-mentioned problems, has high reliability and can simplify the steps, and a method of manufacturing the same.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first conductivity type region in a semiconductor substrate is covered with a first insulating film. After a part of the insulating film is removed by etching, the surface of the semiconductor substrate is grown by crystal growth or amorphous growth, and a first mask portion is formed on the removed portion so as to protrude from the semiconductor substrate, and the first insulating film is formed. A second step of forming an efficiency transmitting portion near the boundary between the film and the first mask portion, which allows the efficiency of impurity implantation into the semiconductor substrate to be higher than that of the surroundings; A third step of forming a second conductive type low-concentration region having a small layer thickness and a thick second conductive type high-concentration region sandwiching the low-concentration region on the substrate surface in the mold region; The fourth step of removing the mask, Fifth the stack control electrode on the electrode insulating film provided, formed on the layer thickness of the thin low-density region
And the step of:

In the method of manufacturing a semiconductor device according to the second aspect, isotropic etching is used for etching to remove a part of the first insulating film in the second step, and formation of an efficient transmission portion is performed for the second step. A first mask portion is formed on a portion removed by the etching step so as to slightly overlap or not overlap with the first insulating film.

[0009]

In the method of manufacturing a semiconductor device according to the first aspect, in the third step, a single impurity implantation is performed in the third step to reduce the thickness of the second conductive type low concentration region and the low concentration region. It is possible to form a second-concentration-type high-concentration region with a thicker layer to sandwich. Then, in a fifth step, a stack in which the control electrode is provided on the control electrode insulating film is formed on the low-concentration region having the small thickness. Therefore, the implanted impurities do not penetrate the control electrode insulating film.

In the method of manufacturing a semiconductor device according to a second aspect, isotropic etching is used for etching for removing a part of the first insulating film in the second step, and formation of the efficient transmission portion is performed for the etching. Forming a first mask portion on the portion removed by the etching step so as to slightly overlap or not overlap with the first insulating film;

Therefore, the efficiency transmitting portion can be easily formed.

[0012]

An embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 4A, after an element isolation region and an element formation region are formed by the LOCOS method, a first conductivity type region is formed on the surface of a silicon well 2 (N type).
A first silicon oxide film 26 as an insulating film is formed. In this embodiment, the film is formed by thermal decomposition at 850 ° C. with SiH ₄ and N ₂ O using low pressure chemical vapor deposition (LPCVD). Then, after applying a photoresist 6, patterning is performed (FIG. 4B). Isotropic etching is performed using hydrofluoric acid (FIG. 4C) to form an opening 28 (FIG. 4D).
The photoresist 6 is removed.

Next, as shown in FIG.
First, a mask 23 as a first mask portion is
It is formed so as to protrude from. In this embodiment, SiH ₄
The mask 23 was formed by epitaxial growth (crystal growth) by a low pressure chemical vapor deposition method using H 2 and HCl.

In this embodiment, the mask 23 is formed by the first silicon oxide film 26
However, the mask 23 may be stopped when the mask 23 is grown so as to slightly overlap or not overlap the first silicon oxide film 26.

Next, as shown in FIG.
3 and the entire surface of the first silicon oxide film 26 is implanted with boron ions as impurities. The implanted boron ions are trapped by the first silicon oxide film 26 in the portion T where the first silicon oxide film 26 is thick, and are hardly implanted into the silicon well 2. On the other hand, the thin portion S, which is an efficient transmission portion, is not trapped by the first silicon oxide film 26, so that a large amount of boron ions are implanted. The portion covered with the mask 23 is injected into the silicon well 2 while being trapped by the mask 23. However, compared with the portion S having a small film thickness, the concentration to be implanted is smaller and the depth from the substrate surface is smaller by the amount trapped by the mask 23.

As described above, the channel region 10 which is the second conductive type low-concentration region having a small layer thickness is formed by one ion implantation.
And a drain 3, which is a thick second conductivity type high concentration region formed so as to sandwich the channel region 10;
And the source 4 can be formed.

In the present embodiment, the thin portion S of the first silicon oxide film 26 is formed so as to have a small thickness near the boundary with the mask 23 and to have a large thickness as the distance increases. I have. Therefore, by implanting boron ions, the channel region 10 is a low-concentration second-conductivity-type low-concentration region, and the thick second-conductivity-type high-concentration region is formed to sandwich the channel region 10. The drain 3 and the source 4 are automatically formed.

Then, after the implanted boron is activated by annealing, as shown in FIG. 1C, the mask 23 is removed by a chemical dry etching (CDE) method.

Next, as shown in FIG. 1D, after a silicon oxide film and a polysilicon layer are formed on the entire surface of the silicon well 2, etching is performed using a photoresist to form a gate oxide film 8 and a gate electrode 5. In this manner, a stack in which the gate electrode 5 as the control electrode is provided on the gate oxide film 8 as the control electrode insulating film is formed on the channel region 10 which is the second conductive type low concentration region having a small thickness. Is done.

After the channel region 10, the drain 3 and the source 4 are formed in this manner, the gate oxide film 8 and the gate electrode 5 are formed, whereby the gate oxide film 8 is formed.
Degradation can be prevented.

Next, as shown in FIG. 2, a second silicon oxide film 27 is formed by using a low pressure chemical vapor deposition method. In the present embodiment, it is formed by a CVD method using TEOS (tetraethoxysilane). Then source 4,
After forming contact holes for the drain 3 and the gate electrode 5, the contacts 20a, 20b, and 20c are formed, and the MOSFET 21 is completed.

Although the mask 23 is formed by epitaxial growth in this embodiment, the mask 23 may be formed of polycrystalline silicon. Further, instead of forming the mask 23 from single crystal or polycrystalline silicon, the mask 2 is formed from amorphous amorphous silicon.
3 may be formed.

In this embodiment, the efficient transmission portion is formed by isotropically etching the first silicon oxide film 26. However, the first silicon oxide film 26
Any structure may be used in the vicinity of the boundary between the mask and the mask 23 so long as the efficiency of ion implantation into the semiconductor substrate is higher than that of the surroundings. For example, as shown in FIG. 3A, the first silicon oxide film 26 and the mask 23 may be formed so as not to slightly overlap each other to form the efficient transmission portion. Further, as shown in FIG. 3B, the end of the mask 23 may be formed to be thin, or as shown in FIG. 3C, a part of the first silicon oxide film 26 may be formed to be thin.

In this embodiment, the MOSFET
21 has been described as a depletion type FET,
The OSFET 21 may be an enhancement type FET. In this case, as a manufacturing method, the thickness of the mask 23 may be increased to adjust the ion concentration of the channel region 10.

[0025]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, in the third step, the impurity concentration of the second conductivity type is reduced by performing a single impurity implantation in the third step. The second conductive type high concentration region having a large layer thickness sandwiching the region can be formed. Thereby, the number of masks can be reduced, and the process can be simplified. Then, in a fifth step, a stack in which the control electrode is provided on the control electrode insulating film is formed on the low-concentration region having the small thickness. Therefore, the implanted impurities do not penetrate the control electrode insulating film. Thus, the deterioration of the control electrode insulating film below the control electrode can be prevented.

That is, it is possible to provide a method of manufacturing a semiconductor device which has high reliability and can simplify the steps.

In the method of manufacturing a semiconductor device according to the second aspect, isotropic etching is used for the etching for removing a part of the first insulating film in the second step, and the etching for forming the efficient transmission portion is performed. Forming a first mask portion on the portion removed by the etching step so as to slightly overlap or not overlap with the first insulating film;

Therefore, the efficient transmission portion can be easily formed, and the process can be further simplified.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a MOSFET 21.

FIG. 2 is a diagram showing a MOSFET 21.

FIG. 3 is a diagram illustrating an example of a shape of an efficiency transmitting portion of the MOSFET 21.

FIG. 4 is a view showing a step of forming an opening by isotropic etching in a manufacturing process of the MOSFET 21;

FIG. 5 is a diagram showing a manufacturing process of a conventional MOSFET 1.

FIG. 6 is a diagram showing a manufacturing process of a conventional MOSFET 1.

[Explanation of symbols]

 2 silicon well 3 drain 4 source 5 gate electrode 8 gate oxide film 23 mask 26 first silicon oxide film

Claims (2)

(57) [Claims] A first step of covering a region of the first conductivity type in the semiconductor substrate with a first insulating film; removing a part of the first insulating film by etching;
A first mask portion is formed so as to protrude from the semiconductor substrate in a portion where the semiconductor substrate surface is crystal-grown or non-crystal-grown, and is removed near a boundary between the first insulating film and the first mask portion. A second step of forming an efficient transmission portion that allows the efficiency of impurity implantation into the semiconductor substrate to be higher than that of the surroundings. Impurity implantation is performed from above the semiconductor substrate, and a layer thickness of A third step of forming a thin second conductivity type low concentration region and a thick second conductivity type high concentration region sandwiching the low concentration region; a fourth step of removing the first mask portion; control electrode insulation A fifth step of forming a laminate in which a control electrode is provided on the film on the low-concentration region having the small thickness. 2. The method of manufacturing a semiconductor device according to claim 1, wherein isotropic etching is used for removing a part of the first insulating film in the second step, and formation of an efficient transmission portion is performed. Forming a first mask portion on the portion removed by the etching step so as to slightly overlap or not overlap the first insulating film.