JP3053809B1 - Linear amplifier circuit - Google Patents

Abstract

An object of the present invention is to enable linearization with a wide range of input signal voltages and an arbitrary gain. An N-type field effect transistor for supplying a positive current and an N-type field effect transistor for supplying a negative current are provided.
And a second push-pull circuit composed of an N-type field effect transistor 17 for supplying a positive compensation current and an N-type field effect transistor 18 for supplying a negative compensation current to the load circuit 10. It supplies a load current I _L. The non-linear current supplied by the first push-pull circuit is linearized by the compensation current supplied by the second push-pull circuit. Adjusting the gain by varying the level shift amount of the first level shift circuit 30 and the level shift amount of the second level shift circuit 31 by an amount that has substantially the same absolute value as each other and inverts the positive and negative polarities. Can be.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose amplifier circuit, and more particularly to an amplifier circuit at an output stage in a power amplifier for voice or wireless communication requiring high output and high linear amplification.

[0002]

2. Description of the Related Art A power amplifier for wireless communication is required to have high linearity so as not to disturb adjacent channels. Further, in a commercial wireless system, an amplifier having a large output power is required because the communication area is wide. Against this background, the output stage of a conventional power amplifier has been
No. 28185, Japanese Patent Publication No. Hei 7-101822,
Transistor technology SPECIAL No. 32 eleventh
A push-pull amplifier circuit as disclosed in FIG. 9 and the like has been used. FIG. 5 shows a basic configuration of a conventional push-pull amplifier circuit. In this push-pull amplifier circuit, the drain of a positive current supply N-type field effect transistor 11 is connected to a positive power supply terminal 101, the gate is connected to an input terminal 103, and The source is connected to the drain of the negative current supply N-type field effect transistor 12, the drain of the negative current supply N-type field effect transistor 12 is the source of the positive current supply N-type field effect transistor 11, and the gate is a level shift circuit. 14
And the source is connected to the negative power supply terminal 102. Further, the load circuit 10 is connected between the connection between the source of the N-type field effect transistor 11 for supplying a positive current and the drain of the N-type field effect transistor 12 for supplying a negative current, and the ground terminal 200. Between the input terminals of the shift circuit 14, an inverting amplifier 13 having an amplification degree of 1
Is connected.

The operation of the push-pull amplifier shown in FIG. 5 will be described. A voltage signal inputted from an input terminal 103 is applied to the gate of a positive current supply N-type field effect transistor 11 for supplying a positive current to a load circuit 10. At the same time, the voltage signal is input to the inverting amplifier 13 having an amplification degree of 1 and is converted into a voltage signal having positive and negative polarities inverted. The positive current supply N-type field effect transistor 11 is such that the applied voltage signal becomes active in a positive voltage region, converts the voltage signal into a drain current corresponding to the value, and outputs the positive current supply N-type field effect transistor. 11 to the load circuit 10 connected to the source.

On the other hand, a voltage signal whose positive and negative polarities are inverted by an inverting amplifier 13 having a gain of 1 is level-shifted to the gate of a negative current supplying N-type field effect transistor 12 for supplying a negative current to a load circuit 10. The signal is level-shifted by the circuit 14 and applied. If the level shift amount of the level shift circuit 14 is the level of the source potential of the negative current supply N-type field effect transistor 12, that is, the voltage of the negative power supply terminal 102, the input terminal 103
Becomes active in a negative voltage region of the voltage signal inputted to the load circuit 10, converts the voltage signal into a drain current corresponding to the value, and supplies the drain current to the load circuit 10 connected to the drain. From the above operation, it can be understood that the positive and negative voltage signals input to the input terminal 103 are supplied to the load circuit 10 as currents according to the voltage values. The threshold voltage of the positive current supply N-type field effect transistor 11 and the negative current supply N-type field effect transistor 12 in FIG. 5 is 0 [V].

FIG. 6 shows another basic configuration of a conventional push-pull amplifier circuit. In this push-pull amplifier circuit, the drain of a positive current supply N-type field effect transistor 11 is connected to a positive power supply terminal 101. Gate is input terminal 10
3, the source is connected to the source of the negative current supply P-type field effect transistor 24, the source of the negative current supply P-type field effect transistor 24 is the source of the positive current supply N-type field effect transistor 11, and the gate is The output terminal of the level shift circuit 14 has a drain connected to the negative power supply terminal 102. The load circuit 10 is connected between a connection between the source of the N-type field effect transistor 11 for supplying a positive current and the source of the P-type field effect transistor 24 for supplying a negative current, and the ground terminal 200. It is connected to the input terminal of the level shift circuit 14.

In the push-pull amplifier circuit shown in FIG. 6, the N-type field effect transistor 12 for supplying a negative current in the push-pull amplifier circuit shown in FIG.
It has a simple configuration in which the transistor is replaced with a field effect transistor 24 and the inverting amplifier 13 having a gain of 1 is omitted. In this circuit, by connecting the source of the P-type field effect transistor 24 for supplying a negative current to the load circuit 10, a load current corresponding to the voltage value of the voltage signal in the negative region of the input signal is taken out.

The above operation in FIGS. 5 and 6 is a class B operation in which the load current becomes 0 [A] when the input voltage is 0 [V].
Operations such as class and class A are also possible. In this case, as one method, a level shift circuit is newly inserted between the gate of the N-type field effect transistor 11 for supplying a positive current and the input terminal 103, and the N-type field effect transistor 11 for supplying a positive current is supplied.
Of the negative current supply N-type field effect transistor 12 or the negative current supply P-type field effect transistor 24, the gate voltage is adjusted by changing the level shift amount of the existing level shift circuit 14. And
What is necessary is just to make it flow a desired bias current.

[0008]

The operation of the conventional circuit shown in FIGS. 5 and 6 will be described in detail from the viewpoint of linearity. The operation of the push-pull amplifier shown in FIG. 6 is equivalent to the operation of the push-pull amplifier shown in FIG. 5 and will be described with reference to FIG. The mutual conductance coefficient of the N-type field effect transistor 11 for supplying a positive current and the N-type field effect transistor 12 for supplying a negative current is K, the threshold voltage (threshold voltage) is Vth, and the N-type field effect transistor for supplying a positive current. 11 and the gate-source voltage of the N-type field effect transistor 12
Let sa and Vgsb be the drain current Ia flowing through the N-type field effect transistor 11 for supplying a positive current and the drain current flowing through the N-type field effect transistor 12 for supplying a negative current.
Ib is represented by the following equation. Ia = K (Vgsa-Vth) ² where Vgsa> Vth (1) Ia = 0 but Vgsa ≤ Vth (2) Ib = -K (Vgsb-Vth) ² where Vgsb> Vth (3) Ib = 0 but Vgsb ≤ Vth (4)

Here, the drain current Ia and the drain current Ib
, The direction of the drain current Ib flows in the opposite direction to the direction of the drain current Ia, so that the sign of the minus is added. Assuming that the input signal voltage input to the input terminal 103 is Vin and the resistance value of the load circuit 10 is _RL , the gate-source voltage Vgsa of the positive current supply N-type field effect transistor 11 is Vgsa = Vin− _RL・ Ia is given by (5). The input signal voltage input to the input terminal 103 is Vin, the level shift amount of the level shift circuit 14 is Vd, and the negative power supply voltage of the negative power supply terminal 102 is Vs.
s, N-type field effect transistor 1 for supplying a negative current
The gate-source voltage Vgsb of No. 2 is given by: Vgsb = −Vin + Vd−Vss (6)

By substituting equation (5) into equations (1) and (2) and substituting equation (6) into equations (3) and (4), the drain current Ia and the drain current Ib become , Ia = K (Vin− _RL · Ia−Vth) ² where Vin> Vth + _RL · Ia (7) Ia = 0, but Vin ≦ Vth + _RL · Ia (8) Ib = −K (−Vin + Vd−Vss−Vth) ² (9) where Vin <(− Vth + Vd−Vss) Ib = 0 However, Vin ≧ (−Vth + Vd−Vss) (10) Here, if the voltage drop _RL · Ia in the load circuit 10 is small in the equations (7) and (8), the drain current Ia is Ia = K (Vin−Vth) ² where Vin> Vth (7-2) Ia = 0 However, Vin ≦ Vth (8-2).

Further, equations (7-2), (8-2),
In the equations (9) and (10), for example, K = 1 [A / V
² ], Vth = 0 [V], Vd−Vss = 0 [V], the drain current Ia and the drain current Ib are Ia = Vin ² where Vin> 0 (11) Ia = 0 where Vin ≦ 0 (12) Ib = − (− Vin) ² where Vin <0 (13) Ib = 0 However, Vin ≧ 0 (14). In this case, the load current I _L flowing through the load circuit 10
Since a synthesized composite current drain current Ia and the drain current Ib, a _{I L = Ia + Ib (15} ).

Here, according to the equations (11) and (12), the drain current Ia flows only when the input signal voltage Vin is a positive voltage exceeding 0 [V], and according to the equations (13) and (14), the drain current Ia is obtained. It can be seen that Ib flows only when the input signal voltage Vin is a negative voltage less than 0 [V]. Therefore the characteristics of the load current I _L obtained by the combined current of the drain current Ia and the drain current Ib will be characteristic of the drain current Ia and the drain current Ib appears intact. According to Equations (11) to (14), since both the drain current Ia and the drain current Ib are quadratic functions of the input signal voltage Vin, the linearity is very poor and large distortion occurs. Become. Note that an amplifier that operates at the operating point as described above is generally called a class B amplifier.

In order to improve the linearity of the class B amplifier, the level shift amount Vd of the level shift circuit 14 is made smaller than the negative power supply voltage Vss so that (Vd-Vss) becomes a positive voltage. There is a way. For example, K = 1, Vth = 0
When [V] and (Vd−Vss) = 5 [V], the above equations (9) and (10) are expressed as follows: Ib = − (− Vin + 5) ² where Vin <5 (16) Ib = 0 Vin ≧ 5 (17) In this case, the load current _IL is as described above (1).
1), (12), (16) and _{(17), I L = - (- Vin} + 5) 2 where _{Vin <0 (18) I L} = Ia + Ib = 10 · Vin-25 where 0 ≦ Vin ≦ 5 (19) _IL = Ia = Vin ² where Vin> 5 (20)

[0014] To determine the linearity of the load current I _L (1
8), (19), (20) is differentiated by the input signal voltage Vin of _{formula, I L '= -2 · Vin} + 10 where _{Vin <0 (21) I L} ' = Ia + Ib = 10 where 0 ≦ Vin ≦ 5 (22) _IL ′ = Ia = 2 · Vin where Vin> 5 (23) is obtained. Drain current Ia, the drain current Ib in FIG. 7 shows the characteristics of the load current I _L and the load current of the slope I _L '. (2
1) to (23) and from FIG. 7 the load current I _L of the inclination I _L 'is independent of the input signal voltage Vin input signal voltage Vin
It can be understood that the range of 0 ≦ Vin ≦ 5. Therefore, linear amplification is possible in this range, but the input signal voltage Vin
When Vin <0 or Vin> 5, the slope I _L ′ of the load current depends on the input signal voltage Vin. That is, the slope of the load current I _L by the value of the input signal voltage Vin becomes nonlinear for changes.

In this circuit, the input signal voltage Vin is linear.
To expand the amplification range, the upper limit of the range of equation (22)
Level that determines the value (Vd-Vss) to be large
The shift amount Vd may be determined. In this case, the input signal
Load current I for change in voltage Vin_LSlope I_L’Is big
It becomes. This load current I_LSlope I_L’Is the rate of change
Therefore, it becomes the gain of the push-pull amplifier. That is, the line
Once the shape region is determined, the gain I _L’Is uniquely determined
As a result, there arises a problem of lack of design flexibility.
The problem of the nonlinear characteristics described above is due to the bipolar transistor.
This also occurs in the case where the data is used. There
Thus, the present invention provides a wide range of the input signal voltage Vin.
It can be a linear amplification circuit that can perform linearization over a wide range.
To provide a linear amplifier circuit capable of achieving a desired gain.
And for the purpose.

[0016]

In order to achieve the above object, a first linear amplifier circuit according to the present invention comprises a source electrode or an emitter electrode of a first transistor in which an input signal is supplied to a gate electrode or a base electrode. A first transistor formed by connecting a drain electrode or a collector electrode of a second transistor supplied to a gate electrode or a base electrode after an inverted input signal is level-shifted by a first level shift circuit; A push-pull amplifier circuit, a source electrode or an emitter electrode of a third transistor to which an inverted input signal is supplied to a gate electrode or a base electrode, and an input signal whose level is shifted by a second level shift circuit to a gate electrode or The drain electrode or the collector electrode of the fourth transistor supplied to the base electrode is Second configured by being continued
A push-pull amplifier circuit, a connection point between the first transistor and the second transistor, and a connection point between the third transistor and the fourth transistor,
A load circuit is provided between the connection point and the ground.

In the first linear amplifier circuit of the present invention, the input signal voltage value at which the first transistor shifts from the inactive state to the active state, and the third transistor changes from the inactive state to the active state. Input signal voltage to transition to
With the value being equal, the input to which the second transistor and an input signal voltage value <br/> to transition to the active state from the inactive state, the fourth transistor is shifted from the inactive state to the active state The level shift amount in the first level shift circuit and the level shift amount in the second level shift circuit may be set so that the signal voltage value becomes equal . Further, in the first linear amplifier circuit of the present invention, the level shift amount in the first level shift circuit and the level shift amount in the second level shift circuit are varied to flow to the load circuit. The slope of the current change may be set to a desired slope.

According to the second linear amplifier circuit of the present invention, which can achieve the above object, a source electrode or an emitter electrode of a one-type first transistor in which an input signal is supplied to a gate electrode or a base electrode; A first push-pull amplifier circuit configured by connecting a source electrode or an emitter electrode of a second transistor of the other type to which a signal is level-shifted by a level shift circuit and supplied to a gate electrode or a base electrode; A source electrode or an emitter electrode of a third type transistor in which an inverted input signal is supplied to a gate electrode or a base electrode; and a gate electrode or a base electrode obtained by inverting the input voltage level-shifted by the level shift circuit. The source electrode or emitter electrode of the other type of fourth transistor supplied to the electrode. A second push-pull amplifier circuit configured by connecting the electrodes, a connection point between the first transistor and the second transistor, and a connection point between the third transistor and the fourth transistor. And a load circuit connected between the connection point and the ground.

Further, in the second linear amplifier circuit according to the present invention, by changing the level shift amount in the level shift circuit, the slope of the change in the current flowing through the load circuit is set to a desired slope. You may. Further, in the second linear amplifier circuit according to the present invention, the input signal voltage value at which the first transistor shifts from the inactive state to the active state, and the third transistor shifts from the inactive state to the active state. with the input signal voltage value is equal <br/>, the input signal voltage value the second transistor is shifted from the inactive state to the active state, the fourth
ON the transistor shifts from the inactive state to the active state
The force signal voltage value may be made equal .

Further, the first and second embodiments of the present invention are described.
When the input signal voltage changes in one direction from Vo, the output current flowing through the first transistor changes, and the output current flowing through the third transistor does not change. The input signal voltage is V
When the input signal voltage changes from o to the other direction, the output current flowing to the third transistor changes, and the output current flowing to the first transistor does not change, and the input signal voltage changes from (Vo + Va) in one direction. When the input signal voltage changes from (Vo + Va) to the other direction, the output current flowing through the fourth transistor changes while the output current flowing through the second transistor does not change. The output current flowing through the second transistor may be changed while the output current flowing through the fourth transistor does not change.

According to the present invention, the positive current is compensated for in addition to the first push-pull amplifier in which the transistor for supplying the positive current to the load circuit and the transistor for supplying the negative current to the load are cascaded. A second push-pull amplifying circuit in which a transistor for performing the operation and a transistor for compensating the negative current are cascaded, and the output current of the first push-pull amplifying circuit is compensated by the output current of the second push-pull amplifying circuit. As a result, linearity can be ensured in all input signal voltage ranges.
In addition, an input signal voltage is supplied to a transistor for supplying a negative current to a load circuit and a transistor for compensating for a positive current through a level shift circuit. The gain can be adjusted to any gain.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first circuit configuration of a linear amplifier circuit according to an embodiment of the present invention. In the linear amplifier circuit shown in FIG. 1, the drain of a positive current supply N-type field effect transistor 11 is connected to a positive power supply terminal 101, the gate is connected to an input terminal 103, and the source is a negative current supply N-type. It is connected to the drain of the field effect transistor 12. The drain of the N-type field effect transistor 12 for supplying negative current is connected to the source of the N-type field effect transistor 11 for supplying positive current, the gate is connected to the output terminal of the first level shift circuit 30, and the source is negative. The power supply terminal 102 is connected. In this manner, the first push-pull amplifier circuit is configured by cascade-connecting the positive current supply N-type field effect transistor 11 and the negative current supply N-type field effect transistor 12.

The drain of the N-type field effect transistor 17 for supplying a positive compensation current is connected to the positive power supply terminal 101, the gate is connected to the output terminal of the inverting amplifier 13 having an amplification factor of 1, and the source is connected to the negative compensation terminal. It is connected to the drain of the current supply N-type field effect transistor 18. Further, an N-type field effect transistor 18 for supplying a negative compensation current
Is connected to the source of the N-type field effect transistor 17 for supplying a positive compensation current, its gate is connected to the output terminal of the second level shift circuit 31, and its source is connected to the negative power supply terminal 102. As described above, the N-type field effect transistor 17 for supplying the positive compensation current and the N-type field effect transistor 18 for supplying the negative compensation current are connected in cascade to form a second push-pull amplifier circuit. Furthermore, the N-type field effect transistor 11 for supplying a positive current
Source and N-type field effect transistor 12 for supplying negative current
Is connected to the connection between the source of the N-type field effect transistor 17 for supplying a positive compensation current and the drain of the N-type field effect transistor 18 for supplying a negative compensation current. The load circuit 10 is connected between 200. The voltage signal input from the input terminal 103 is applied to the inverting amplifier 13 having the amplification factor of 1 and the second level shift circuit 31, and the inverting amplifier 1 having the amplification factor of 1 is applied.
The output of 3 is applied to the first level shift circuit 30.

Next, the operation of the linear amplifier of the present invention shown in FIG. 1 will be described. In the conventional amplifier circuits shown in FIGS. 5 and 6, the drain current Ia flowing through the N-type field effect transistor 11 for supplying a positive current and the drain current Ib flowing through the N-type field effect transistor 12 for supplying a negative current are combined. It had secure an area of the load current I _L to be linear with respect to the input signal voltage Vin input, as shown in FIG. In this case, at the point where the drain current Ia or the drain current Ib becomes 0, that is, at the region of 0 ≦ Vin ≦ (Vd−Vss) as described above, the N-type field effect transistor 11 for supplying a positive current and the N-type load current I _L supplied as synthesized current since the drain current flows to both of the field effect transistor 12 is linearity can be ensured. But Vin
In the region of <0 and Vin> (Vd−Vss), the positive current supply N
The drain current flows through only one of the field-effect transistor 11 or the N-type field-effect transistor 12 for supplying a negative current. Therefore, the output characteristic (quadratic function characteristic) of the field transistor using had it supposed to become nonlinear appears as a characteristic of I _L.

[0025] Therefore, in the first linear amplifier circuit according to the present invention, the load current I _L regardless of the value of the input signal voltage Vin to a linear, positive compensation current supply N type field as a compensation current source An effect transistor 17 and an N-type field effect transistor 18 for supplying a negative compensation current are provided. A compensation drain current Ia 'for compensating for a negative current flowing through these transistors 17 and 18, and a drain current for compensating for a positive current
FIG. 2 shows an example of the relationship between Ib ′ and the drain current Ia and the drain current Ib flowing through the positive current supply N-type field effect transistor 11 and the negative current supply N-type field effect transistor 12. Here, the drain current Ia and the drain current Ib are the same as the conventional example shown in FIG. 7 (Vd−Vss) = 5, where Vd is the level shift amount of the first level shift circuit 30.
[V], K = 1, Vth = 0 [V]. The drain current Ia ′ is line-symmetric with respect to the vertical axis with respect to the point where the drain current Ia becomes 0 (Vin = 0). Further, by setting the level shift amount of the second level shift circuit 31 to Vdi and (Vdi−Vss) = − 5 [V], the drain current Ib ′ is reduced to a point (Vin = 5) where the drain current Ib becomes zero. [V]) as a reference, and is also line-symmetric with respect to the vertical axis. That is, the voltage value of (Vd−Vss),
The absolute value is equal to the voltage value of (Vdi−Vss), and the positive and negative polarities are opposite polarities.

Since the load current I _L is the sum of the currents flowing through the respective field effect transistors 11, 12, 17, and 18, it is expressed by I _L = Ia + Ia '+ Ib + Ib' (24). Since Ia + Ia ′ and Ib + Ib ′ are line-symmetric with respect to the vertical axis with respect to Vin = 0 as shown in FIG. 2, Ia + Ia ′ = Vin ² (25) Ib + Ib ′ = − (Vin−5) ² ( 26) Therefore, the equations (25) and (26) are
4) is substituted into formula, I _L = Vin ² - a ^{(Vin-5) 2 = 10} · Vin-25 (27). Here, when the equation (27) is differentiated by Vin, I _L ′ = 10 (28), and it can be seen that the load current I _L becomes a straight line with a slope of 10. From this, it can be seen that the first linear amplification circuit according to the present invention is linear with respect to all input signal voltage values without depending on the input signal voltage Vin as shown in FIG.

Further, the first linear amplifier circuit according to the present invention changes the level shift amount Vd of the first level shift circuit 30 and the level shift amount Vdi of the second level shift circuit 31 to thereby reduce the load current. it is possible to change the slope of I _L. Gradient I _L 'is the input signal voltage of the load current I _L
Vin is the load current I gain from the ratio of the change in _L with respect to a change in, by changing the level shift amount Vd and the level shift amount Vdi, it is possible to adjust the gain I _L '. That is, the voltage values of (Vd−Vss) and (Vdi−Vss) are selected (the drain current Ib and the drain current Ib ′ are set to 0).
By changing the input signal voltage Vin that becomes [A]), the gain I _L ′ can be changed. The ability to adjust the gain _IL 'will be described with reference to the example shown in FIG.

FIG. 3A shows that (Vd-Vss) is 10 [V].
And (Vdi−Vss) is set to −10 [V].
In this case, the characteristic curve of the drain current (Ia + Ia ') becomes as shown by a, and the characteristic curve of the drain current (Ib + Ib') becomes as shown by b. In this case, the gain I _L1 ′ which is the slope of the load current I _L1 is 20. Also, as shown in FIG. 3B, (Vd−Vss) is changed to 20 [V] and (Vdi−Vss).
Vss) is -20 [V], the drain current (Ia + I
The characteristic curve of a ′) becomes as shown by a, and the characteristic curve of the drain current (Ib + Ib ′) becomes distant as shown by b. In this case, the gain I _L2 ′, which is the slope of the load current I _L2 , increases to 40. Further, if (Vd-Vss) is changed to 4 [V] and (Vdi-Vss) is set to -4 [V], the characteristic curve of the drain current (Ia + Ia ') becomes as shown in a, and the drain current ( The characteristic curve of (Ib + Ib ′) approaches as shown by b. In this case, the gain _IL3 ', which is the slope of the load current _IL3 , decreases to 8.

Thus, (Vd-Vss) and (Vdi-Vss)
Is increased, the characteristic curve a and the characteristic curve b are separated from each other, and the gain I _L ′ can be increased. On the contrary, the absolute values of (Vd−Vss) and (Vdi−Vss) can be reduced. Then, the characteristic curve a and the characteristic curve b come closer, and the gain I _L ′ can be reduced. In addition, (V
When the values of (d−Vss) and (Vdi−Vss) are set to 0 [V], the gain I
_L ′ becomes 0, (Vd−Vss) is a negative voltage, and (Vdi−Vss)
If s) is a positive voltage, the gain _IL 'has a negative slope, so that the gain _IL ' can also be negative. That is, any gain from a positive gain to a negative gain can be set. In this case, the level shift amount Vd, Vdi or the voltage value of the negative power supply voltage Vss is externally controlled, and (Vd−Vss) and (Vdi
-Vss), the first linear amplifier according to the present invention can be used as a variable gain amplifier circuit. The voltage values of (Vd-Vss) and (Vdi-Vss) are varied so that the absolute values are substantially equal and the positive and negative polarities are opposite.

In the above-described first linear amplifier according to the present invention, the circuit is constituted by the N-type field-effect transistor. However, by setting the positive and negative polarities of the positive power supply Vdd and the negative power supply Vss to the opposite polarities, A circuit can be formed with a field-effect transistor of the type. The first aspect of the present invention described above.
Although the threshold voltage of the field effect transistor in the linear amplifier of the above is set to 0 [V], it may be an enhancement type or a depletion type. When the threshold voltage is not 0 [V], the level shift amounts of the first level shift circuit 30 and the second level shift circuit 31 are adjusted so as to satisfy the current relationship shown in FIG.
A level shift circuit having a level shift amount corresponding to the threshold voltage may be provided at the gate of the field effect transistor 17 for supplying the positive compensation current. Also, the field effect transistor is M
OS (Metal Oxide Semiconductor), MIS (Metal I
nsulator Semiconductor), insulated gate type, MES
(Metal Semiconductor), SIT (Static induction)
Transistor) or any other junction type.

Further, the N-type field effect transistor is
It can be replaced with a bipolar transistor. In this case, drain to collector, gate to base,
The same effect can be obtained by replacing the source with the emitter and adjusting the level shift amounts of the first level shift circuit 30 and the second level shift circuit 31 so as to satisfy the current relationship shown in FIG. However, a level shift circuit having a level shift amount corresponding to the base-emitter voltage Vbe (about 0.8 [V] in the case of a silicon transistor) at which the collector current of the NPN bipolar transistor to be used starts to flow is provided for each NPN. It must be inserted into the base of a bipolar transistor.
Also, by inverting the positive and negative polarities of the positive power supply and the negative power supply, PNP can be used instead of the NPN type bipolar transistor.
A bipolar transistor can also be used. Furthermore, HEMTs (High Ele
ctron Mobility Transistor) and HBT (Heterojunctio)
n Bipolar Transistor) may be used.

Next, FIG. 4 shows a circuit configuration of the second linear amplifier circuit according to the present invention. As shown in FIG. 4, the drain of a positive current supply N-type field effect transistor 11 is connected to a positive power supply terminal 101 and the gate thereof is connected to an input terminal 10.
3, the source of which is connected to the source of the P-type field effect transistor 20 for supplying a negative current, and the source of the P-type field effect transistor 20 for supplying a negative current is connected to the source of the N-type field effect transistor 11 for supplying a positive current. The source is connected, the gate is connected to the output terminal of the level shift circuit 16, and the drain is connected to the negative power supply terminal 102, thereby forming a first push-pull amplifier circuit.
The N-type field effect transistor 17 for supplying a positive compensation current
Is connected to the positive power supply terminal 102, its gate is connected to the output terminal of the first inverting amplifier 13-1 having an amplification factor of 1, and its source is connected to the source of the P-type field effect transistor 22 for supplying a negative compensation current. The source of the P-type field effect transistor 22 for supplying the negative compensation current is connected to the source of the N-type field effect transistor 17 for supplying the positive compensation current, and the gate thereof is connected to the second inverting amplifier 13 having the amplification factor of 1. -2, and the drain thereof is connected to the negative power supply terminal 103 to form a second push-pull amplifier circuit.

The connection between the source of the N-type field effect transistor 11 for supplying a positive current and the source of the P-type field effect transistor 20 for supplying a negative current, and the connection between the source of the N-type field effect transistor 17 for supplying a positive compensation current and P for compensation current supply
The connection of the source of the field effect transistor 22 is connected, and the load circuit 10 is connected between the connection and the ground terminal 200. Further, the input signal voltage Vin input from the input terminal 103 is also applied to the level shift circuit 16 and the first inverting amplifier 13-1 having an amplification degree of 1, and the output of the level shift circuit 16 is applied to the second inversion amplifier having the amplification degree of Are also applied to the inverting amplifier 13-2.

The second linear amplifier circuit according to the present invention shown in FIG. 4 is similar to the first linear amplifier circuit according to the present invention shown in FIG.
And N-type field effect transistor 18 for supplying a negative compensation current
Are respectively connected to a P-type field effect transistor 2 for supplying a negative current.
The same operation and effect as those of the first linear amplifier circuit according to the present invention are obtained by substituting 0 and the P-type field effect transistor 22 for supplying a negative compensation current.

That is, in the linear amplifier circuit according to the present invention shown in FIG. 4, the gate of the N-type field effect transistor 17 for supplying the positive compensation current is connected to the first inverting amplifier 13 having the amplification factor of 1.
By inserting −1, the drain current Ia ′ flows in the region where the input signal voltage Vin is Vin <0. Also, assuming that the voltage effect in the load circuit 10 is small and the level shift amount of the level shift circuit 16 is Vd, the negative current supply P
-Source voltage Vg of p-type field effect transistor 20
sc is given by: Vgsc = Vin + Vd-0 = Vin + Vd (29) On the other hand, the gate-source voltage Vgsd of the P-type field effect transistor 22 for supplying a negative compensation current is supplied to the gate of the transistor 22 by the second inverting amplifier 13-
Since 2 is inserted, the polarity of Vgsd is inverted, and Vgsd = − (Vin + Vd) −0 = − (Vin + Vd) (30)

Here, assuming that the threshold voltage Vth = 0, Vgs
At c = Vgsd = 0, the drain current Ib and the drain current Ib ′ start flowing. In this case, the input signal voltage Vin at which the drain current Ib and the drain current Ib ′ start flowing is (2
Since it suffices to substitute 0 for the gate-source voltage Vgsc and the gate-source voltage Vgsd in the expressions 9) and (30), Vin = −Vd (31) From this equation (31), the input signal voltage Vin is Vin = −
At the time of Vd, both the drain current Ib and the drain current Ib ′ become 0, and the gate-source voltage Vgsc becomes Vgsc <0 in the voltage range of Vin <−Vd, so that the drain current Ib flows. Further, when the input signal voltage Vin is Vin> −Vd
In this voltage range, the gate-source voltage Vgsd becomes Vgsd <0, so that the drain current Ib ′ flows. As described above, the level shift amount Vd may be set to Vd = −5 [V] in order to match the current characteristics shown in FIG.
The Ib and the drain current Ib 'match the current characteristics shown in FIG. With the above configuration, the second linear amplifier of the present invention can obtain the same effects as those of the first linear amplifier of the present invention.

In the second linear amplifier of the present invention, a bipolar transistor can be used instead of a field effect transistor. That is, each of the positive current supply N-type field effect transistor 11 and the positive compensation current supply N-type field effect transistor 17 is replaced with first and third NPN-type bipolar transistors, and the negative current supply P-type Each of the effect transistor 20 and the P-type field effect transistor 22 for supplying a negative compensation current is replaced with second and fourth PNP bipolar transistors. Further, the collectors of the first and third NPN bipolar transistors correspond to the drain, gate and source of the positive current supply N-type field effect transistor 11 and the positive compensation current supply N-type field effect transistor 17, respectively. A base and an emitter are connected, and second and fourth PNP bipolar transistors corresponding to the drain, gate and source of each of the negative current supply P-type field effect transistor 20 and the negative compensation current supply P-type field effect transistor 22 Connect the collector, base and emitter of the transistor. Then, by adjusting the level shift amount of the level shift circuit 16, a linear amplifier circuit having a current relationship shown in FIG. 2 can be obtained. However, a level shift having a level shift amount corresponding to the base-emitter voltage Vbe (about 0.8 [V] in the case of a silicon transistor) at which the collector current of the NPN bipolar transistor or the PNP bipolar transistor to be used starts to flow. It is necessary to insert the circuit into the base of each NPN-type bipolar transistor or PNP-type bipolar transistor.

Although the threshold voltage of the field effect transistor in the second linear amplifier according to the present invention is set to 0 [V], it may be an enhancement type or a depletion type. Thus, the threshold voltage is 0
If not [V], the level shift amount of the level shift circuit 16 is adjusted so as to satisfy the current relationship shown in FIG. 2, and the positive compensation current supply field effect transistor 17 and the negative compensation current supply field effect transistor 22 are adjusted. May be provided with a level shift circuit in which the level shift amount is set according to the threshold voltage. Further, the N-type field effect transistor and the P-type field effect transistor shown in FIG.
Insulated gate type such as S (Metal Insulator Semiconductor), MES (Metal Semiconductor), SIT (Static
Any type of junction type such as induction transistor may be used.

When an N-type field-effect transistor (or P-type field-effect transistor) is referred to as a one-type transistor in this document, the other transistor is a P-type field-effect transistor (or N-type field-effect transistor). When an NPN-type bipolar transistor (or a PNP-type bipolar transistor) is expressed as a one-type transistor, the other-type transistor is a PNP-type bipolar transistor (or an NPN-type bipolar transistor). Furthermore, instead of a field effect transistor, HEMT (High Electron Mobi)
lity Transistor) and HBT (Heterojunction Bipolar)
Transistor) can also be used.

[0040]

As described above, according to the present invention, in addition to the first push-pull amplifier circuit in which a transistor for supplying a positive current to a load circuit and a transistor for supplying a negative current to a load are cascaded, a positive current A second push-pull amplifier circuit in which a transistor for compensating for the negative current and a transistor for compensating for the negative current are cascaded, and the output current of the first push-pull amplifier circuit is compensated by the output current of the second push-pull amplifier circuit As a result, linearity can be ensured in all input signal voltage ranges. In addition, an input signal voltage is supplied to a transistor for supplying a negative current to a load circuit and a transistor for compensating for a positive current through a level shift circuit. The gain can be adjusted to any gain.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first circuit configuration in a linear amplifier circuit according to an embodiment of the present invention.

FIG. 2 shows a compensation drain current Ia ′ for negative current compensation, a drain current Ib ′ for positive current compensation, a drain current Ia for positive current supply, and a negative current supply for the linear amplifier circuit according to the embodiment of the present invention. FIG. 6 is a diagram showing a relationship between the drain current Ib and the drain current Ib.

FIG. 3 is a diagram illustrating a relationship between a level shift amount and a gain in the linear amplifier circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second circuit configuration in the embodiment of the linear amplification circuit of the present invention.

FIG. 5 is a circuit diagram showing a circuit configuration of a conventional push-pull amplifier circuit.

FIG. 6 is a circuit diagram showing another circuit configuration of a conventional push-pull amplifier circuit.

FIG. 7 is a diagram illustrating current linearity of a conventional push-pull amplifier circuit.

[Explanation of symbols]

 10: Load circuit 11: N-type field-effect transistor for supplying a positive current 12: N-type field-effect transistor for supplying a negative current 13, 13-1, 13-2: Inverting amplifier with an amplification of 1 14, 16: Level shift circuit 17 : N-type field effect transistor for supplying a positive compensation current 18: N-type field effect transistor for supplying a negative compensation current 20: P-type field effect transistor for supplying a negative current 22: P-type field effect transistor for supplying a negative compensation current 24: Negative current Supply P-type field effect transistor 30: First level shift circuit 31: Second level shift circuit 101: Positive power supply terminal 102: Negative power supply terminal 103: Input terminal 200: Ground terminal

Claims (7)

(57) [Claims] An input signal is supplied to a gate electrode or a base electrode of a first transistor, and an inverted input signal is level-shifted by a first level shift circuit to provide a gate electrode or a base electrode. A first push-pull amplifier circuit configured by connecting a drain electrode or a collector electrode of a second transistor supplied to an electrode; and a second push-pull amplifier circuit configured to supply an inverted input signal to a gate electrode or a base electrode. The source electrode or the emitter electrode of the third transistor is connected to the drain electrode or the collector electrode of the fourth transistor whose input signal is level-shifted by the second level shift circuit and supplied to the gate electrode or the base electrode. A second push-pull amplifier circuit configured by: A connection point between the transistor and the second transistor, a connection point between the third transistor and the fourth transistor, and a load circuit connected between the connection point and the ground. A linear amplifier circuit. Wherein the input signal to the input signal voltage value of the first transistor is changed from the inactive state to the active state, the third transistor is shifted to the active state from the inactive state
No. together and a voltage value is equal to the input signal, wherein the second transistor is shifted from the inactive state to the active state
And the voltage value, the fourth transistor so that the input signal voltage value to transition to the active state from the inactive state equal, and the level shift amount in the first level shift circuit, the second level shift circuit 2. The linear amplifier circuit according to claim 1, wherein the level shift amount is set in the linear amplifier. 3. A variable level shift amount of the first level shift circuit and a level shift amount of the second level shift circuit are varied, so that a gradient of a change in a current flowing through the load circuit is changed to a desired gradient. 2. The linear amplifier circuit according to claim 1, wherein the linear amplifier is set to: 4. A source electrode or an emitter electrode of a first type transistor in which an input signal is supplied to a gate electrode or a base electrode, and an input signal is level-shifted by a level shift circuit and supplied to a gate electrode or a base electrode. A first push-pull amplifier configured by connecting a source electrode or an emitter electrode of a second transistor of the other type, and an inverted input signal supplied to a gate electrode or a base electrode. A source electrode or an emitter electrode of a third type transistor, and a source electrode or an emitter of a fourth type transistor which is supplied to a gate electrode or a base electrode after an input voltage level-shifted by the level shift circuit is inverted. Second push-pull constituted by connection with electrodes A width circuit, a connection point between the first transistor and the second transistor, a connection point between the third transistor and the fourth transistor, and a load circuit connected between the connection point and ground. And a linear amplifier circuit characterized by comprising: 5. The linearity according to claim 4, wherein the level shift amount in said level shift circuit is varied to set a gradient of a change in a current flowing through said load circuit to a desired gradient. Amplifier circuit. 6. The input signal to the input signal voltage value of the first transistor is changed from the inactive state to the active state, the third transistor is shifted to the active state from the inactive state
No. together and a voltage value is equal to the input signal, wherein the second transistor is shifted from the inactive state to the active state
Voltage value and a linear amplifier circuit according to claim 4, wherein said fourth transistor is characterized in that the input signal voltage value to transition to the active state is equal to the inactive state. 7. When the input signal voltage changes from Vo to one direction, the output current flowing through the first transistor changes, and the output current flowing through the third transistor does not change. When the input signal voltage changes from Vo to the other direction, the output current flowing to the third transistor changes, and the output current flowing to the first transistor does not change, and the input signal voltage becomes (Vo + Va). ), The output current flowing through the fourth transistor changes, the output current flowing through the second transistor does not change, and the input signal voltage changes from (Vo + Va) to the other direction. when changes to, the together with the output current flowing through the second transistor is changed, so that the output current flowing in the fourth transistor does not change Linear amplifier circuit according to claim 1 or 4, wherein a is.