JP2896092B2 - Electronic circuit analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit analyzer, and more particularly, to an analyzer generally applied to an electronic circuit having a CPU (Central Processing Unit). recent years,
In various fields, high-performance electronic devices equipped with a CPU have been produced. ROM (Re
This is because the system can be easily modified or its functions can be changed simply by exchanging the ad only memory, and a highly flexible system can be developed. By the way, in such an electronic circuit, debugging of hardware and software is considerably difficult due to its high functionality, and some kind of debugging support device is indispensable.

[0002]

2. Description of the Related Art An in-circuit emulator (hereinafter, "ICE") for simulating an electronic circuit to be debugged (hereinafter, referred to as "target") has been used as a support device of this kind. In the ICE, the CPU on the ICE side is operated instead of the CPU on the target side, and the operation contents of the CPU are tracked and monitored one by one by emulator software, so that the operation state of the target is comprehensively determined. .

FIG. 9 is an overall configuration diagram of the ICE. 1 is a host computer such as a personal computer or a workstation,
Reference numeral 2 denotes an interface board mounted in an expansion slot of the host computer 1, reference numeral 3 denotes an ICE main body, and reference numeral 4 denotes a probe. 5 is a target-side CPU (hereinafter referred to as “TGT_
CPU ”). The TGT_CPU 5 is housed in, for example, a piggy-pack type package (a package having a socket on the back), the socket 6 of the probe 4 is inserted into the back socket of the TGT_CPU 5, and the I
The connection with the CE main body 3 is made. Reference numeral 8 denotes a cable connecting between the interface boat 2 and the ICE main body 3, and 9 denotes a cable connecting between the ICE main body 3 and the probe 4.

[0004] The ICE body 3 has a built-in CPU 10 (hereinafter referred to as "ICE_CPU") of the same type as the TGT_CPU 5, and dedicated emulation software is installed in the host computer 1 in advance. , Host computer 1
When the emulation software is run, the TGT_CPU 5 is first disconnected from the target bus, and the ICE_CPU 10 is connected instead. Thereafter, various debugging functions of the emulation software are used appropriately,
Emulation of target by CE_CPU 10 (T
GT_CPU5).

[0005]

By the way, an in-circuit emulator can emulate almost all operations of a target CPU and is very effective for debugging a complicated system. Generally, only a part of the function is used, so that there is a problem that the equipment cost is high. In addition, since a dedicated ICE corresponding to the type of the target CPU is required, for example, if the target CPU is to be upgraded, the ICE must be exchanged, and there is a problem that there is no versatility.

[0006]

Accordingly, an object of the present invention is to provide an inexpensive and versatile electronic circuit analyzer.

[0007]

The invention according to claim 1 is
An electronic circuit 1 to be analyzed is shown in FIG.
0 between the address bus 11 (or the address terminal) of the host computer 12 and the address bus 13 (or the address terminal) of the host computer 12. The address signal sent from one is assigned to the other address space and is sent to the other side. Address resending means 14 for resending, the address resending means
Is a predetermined area of the host computer address space,
Address changes between the address space of the electronic circuit to be analyzed
Conversion table, and the address conversion table
Means that data is accessed by the host computer.
Can be rewritten . Claim 2
According to the invention, the principle diagram is shown in FIG.
Address bus 11 (or address terminal) of the electronic circuit 10 of FIG.
And the address bus 13 of the host computer 12.
(Or address terminal) and sent from one side
Assigns the incoming address signal to the other address space
Address retransmission means 14 for retransmission to the other side;
The control terminal 16 of the elephant electronic circuit 10 and the host
Interposed between the control terminal 17 of the computer 12 and
The control signal sent from one is
Control to convert according to the architecture and retransmit to the other side
And the address retransmitting means is provided with
The address signal sent from the host computer is
Included in a predetermined area of the address space of the
Performing the retransmission operation when the
You. The invention according to claim 3 is an add-on of an electronic circuit to be analyzed.
Address or address terminal and the host computer
Interposed between the address bus and the address bus, from one side
Divide the transmitted address signal into the other address space
Address resending means for resending to the other side
The address resending means is sent from the host computer.
The incoming address signal is the address of the host computer.
The retransmission operation is performed when the
Along with the host computer's address space.
Between a predetermined area and the address space of the electronic circuit to be analyzed
Address conversion table, and the address conversion table
The conversion table is accessed by the host computer.
Thus, data can be rewritten.
According to a fourth aspect of the present invention, an address of an electronic circuit to be analyzed is provided.
Bus or address terminal and host computer address
Interposed between the bus and the address terminal and sent from one
Assigned address signal to the other address space
Address retransmitting means for retransmitting to the other side
Circuit control terminal and the host computer
Control terminal and sent from one side
Change control signals to match the other architecture
Control resending means to resend and resend to the other side,
The address retransmitting unit transmits the address from a host computer.
The received address signal is the address of the host computer.
When the retransmission operation is included in a predetermined area of the
And the address of the host computer is empty.
Between the specified area and the address space of the electronic circuit to be analyzed.
Characterized by having an address translation table between
You. The invention according to claim 5 is based on the principle diagram shown in FIG.
Thus, the address bus 11 of the electronic circuit 10 to be analyzed (or
Is an address terminal) and the address of the host computer 12.
Interposed between the bus 13 and an address terminal,
Address signal sent from the other address space
Address retransmission means 14, which allocates and retransmits to the other side,
The control terminal 16 of the electronic circuit 10 to be analyzed and the host
Interposed between control terminal 17 of computer 12
Control signal sent from one device to the other device.
-Convert to match the architecture and retransmit to the other side
Troll retransmission means 18 and electronic circuit 10 to be analyzed
Data bus 19 (or data terminal) of the host computer
Between the data bus 20 (or data terminal) of the data 12
Intervening, the data signal sent from one is transmitted to the other
Convert according to tabus (or data terminal) format
Data resending means 21 for resending data to the
The means for resending data is the address sent from the host computer.
Address signal in the address space of the host computer.
Perform the resending operation when it is included in the fixed area
Together with a predetermined area of the host computer's address space.
Address and the address space of the electronic circuit to be analyzed.
Address translation table, the address translation table
Means that data is accessed by the host computer.
Can be rewritten.

[0008]

[0009]

[0010]

[0011]

According to the present invention, data access between the host computer and the electronic circuit becomes possible irrespective of whether the address spaces of the source and destination of the address signal match or mismatch. Therefore, since one device can be applied to various electronic circuits, versatility can be improved and equipment cost can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 4 and 5 are views showing a first embodiment of the electronic circuit analysis device according to the present invention. First, the configuration will be described. FIG.
In the figure, reference numeral 20 denotes a host computer using a personal computer or a workstation. Although the CPU 21 of the host computer 20 is not particularly limited, for example, it is an 86 system CPU such as 8086,
(For example, 100 buses; not shown) are connected to the expansion slot 22.

A board 23 on which the electronic circuit analyzer of this embodiment is mounted can be mounted in the extension slot 22, and an address signal 2 is transmitted between the extension slot 22 and the board 23.
4 and data 25 and various control signals 26 are exchanged. The power supply to the board 23 may be performed from the expansion slot 22 or from a dedicated adapter.

Reference numeral 27 denotes an address conversion unit (address retransmission means) which is a main part of the electronic circuit analysis apparatus according to the present embodiment.
It has a measured area selection section 29 and an AND circuit section 30. The address decoding unit 28 determines whether or not the address signal 24 from the host computer 20 is included in a specific area (a predetermined area in the address space of the host computer 20). And outputs an area determination signal 31 corresponding to the position in the area. The area to be measured selecting section 29 is provided for each of the I
/ O (ROM 33, SRAM 34 and D
The AND circuit unit 30 generates an address signal 37 for each I / O of the electronic circuit 32 by performing an AND logic between the area determination signal 31 and the area select signal 36. 38 is a CPU of the electronic circuit 32, 39 is an address and data bus,
0 is data exchanged between the board 23 and the electronic circuit 32, and 41 is various control signals exchanged similarly.

Here, the address bit of the 100 bus is 1
Since it is 6/20 bits, the electronic circuit 3
2 is also 16/20 bits. In the figure, bits 0 to 16 are represented by codes TA0-1.
5 and the remaining bits 17 to 20 are represented by code TA1.
It is represented by 9-16. For example, the address space of the electronic circuit 32 ranges from [00000 _(H) ] (H is a symbol representing a hexadecimal number) to [FFFFFF _(H) ], and the SRAM 34
Is [7 **** _(H) ] (* is an arbitrary value between 0 and F), to access the SRAM 34, set TA19 to "0" and TA18 to TA16 to "1". do it. That is, while TA0-15 remains an arbitrary value, only TA19-16 is set to [0111 ₍₂₎ ] ([7
_(H) ]).

Therefore, in the case of this example, of the area select signals 36 from the area to be measured selecting section 29,
The signal corresponding to [7 _(H) ] may be selected by the AND circuit unit 30, and the selection operation may be performed by the area determination signal 31 from the address decoding unit 28. Here, the region selection signal 31 will be described with an actual example.
FIG. 5 is a diagram illustrating an address space of the host computer 20 (an example of the MS-DOS is not particularly limited). In this figure, [0000 _(H) ] to [9FFFF _(H) ]
640 KB up to 640 KB is a memory area (user memory) opened to the user, of which 128 KB from [80000 _(H) ] to [9FFFF _(H) ] is an area that can be arbitrarily separated. Now, considering that the 128 KB area is used to access the I / O of the electronic circuit 32, the 128 KB area is divided into n blocks, and the address decoding unit 28 blocks the m th block (the I / O to be accessed).
For example, when an address signal of m = 7) is detected in the case of the SRAM 34, the area determination signal 31 corresponding to the block number (m) may be activated.

Therefore, according to this embodiment, the address signal 24 from the host computer 20 is [80000]
For example, in the seventh block between _(H) ] and [9FFFF _(H) ], an area identification signal 31 indicating the block number (7) is output from the address decoding unit 28, and the AND circuit unit 30 selects the area. Since [7 _(H) ] in the signal 36 is selected, the address signal 37 retransmitted from the electronic circuit analysis unit 27 to the electronic circuit 32 is [7 **].
** _(H) ], and among the I / Os in the electronic circuit 32,
One having an address of [7 **** _(H) ], that is, S
The RAM 34 is selected.

As a result, as viewed from the host computer 20, it is the same as accessing the SRAM 34 with the address signal 24, and the selected SRAM 3
4 can be handled in the same manner as the I / O of the host computer 20 itself, so that the electronic circuit 32 can be used without using a conventional in-circuit emulator.
Can be simulated.

The present invention is not limited to the above embodiment. The point is that a predetermined area of the address space of the host computer 20 (of course, the 128 K
B), the address space of the electronic circuit 32 may be assigned, and the address decode unit 28 and the measured area selection unit 29 may be designed as appropriate while comparing the structures of the two address spaces. .

FIGS. 6 to 9 are views showing a second embodiment of the electronic circuit analyzing apparatus according to the present invention. Note that the same reference numerals are given to circuit elements common to the first embodiment, and description thereof is omitted. In the present embodiment, the configuration of the address translator is the first
This is different from the embodiment. That is, the address conversion unit (address retransmission unit) 50 of this embodiment includes a memory 51, an address decoding unit 52, and a mask circuit 53. The memory 51 is activated when the chip select signal 54 from the address decoding unit 52 is active. When read / write is possible and the mask signal 55 from the mask circuit 53 is active, the write operation is prohibited and the return of read data to the host computer 20 is prohibited.

Here, the chip select signal 54 becomes active when the address signal 24 from the host computer 20 is included in a specific area (a predetermined area of the address space of the host computer 20). The signal 55 becomes active after writing data (address conversion table) to the memory 51. FIG. 7 shows an example of the address conversion table.
With reference to data in column A (conversion source address), data in column B (conversion destination address) in the same row as the data is read.

The translation source address is the host computer 2
A value corresponding to the address space of 0, and the conversion destination address is a value corresponding to the address space of the electronic circuit 32. For example, in FIG. 7, the address space of the host computer 20 ranges from [100000 _(H) ] to [1F
0000 _(H) ] (that is, a part of the extended memory area).
Is the source address, [0] in the address space of the electronic circuit 32.
0000 _(H) ] to [F0000 _(H) ] are the conversion destination addresses. For example, [1000000] in column A
_(H) ], [00000 _(H) ] in column B can be read.

[0023] Now, D-RAM35 of the electronic circuit 32 _{[00000 (H)] ~ [} 6FFFF (H)] ([6FFF
F _(H) ] is assigned to the area of [70000 _(H) ] minus [10000].
The DRAM 35 can be accessed by referring to _(H) ] to [16FFFF _(H) ]. That is, column A of the address conversion table has a one-to-one correspondence with (A19-16 of) the address signal 24 of the host computer 20, and column B of the table has the electronic circuit 3
2 has a one-to-one correspondence with the address signal 37 (TA19-16), the difference between the two address signals 24 and 37 can be absorbed in this same table, as if it were part of the host computer 20. Thus, each I / O of the electronic circuit 32 can be handled.

Although the address translation table is written from the host computer 20 to the memory 51 in the second embodiment, the present invention is not limited to this. The memory 21 may be non-volatile. The memory (that is, the address conversion table) may be replaced according to the combination of the host computer 20 and the electronic circuit 32.

The common part (000) of the table shown in FIG.
0) may be omitted, as shown in FIG. A per line
It is sufficient to secure 5 bits in the column and 4 bits in the B column, and the capacity of the memory 51 can be reduced. In each of the above embodiments,
Although address conversion is performed between the host computer and the electronic circuit, it is preferable to perform control signal conversion and data bus format conversion in addition to this. This is because, depending on the type of CPU mounted on the electronic circuit, the control signal or data bus of the host computer cannot be used as it is.

[0026]

According to the present invention, regardless of the coincidence / mismatch between the address spaces of the source and destination of the address signal,
Data access between the host computer and the electronic circuit becomes possible. Accordingly, one device can be applied to various electronic circuits, and versatility can be improved and equipment cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the invention according to claim 1;

FIG. 2 is a principle diagram of the invention according to claim 2 ;

FIG. 3 is a principle diagram of the invention according to claim 5 ;

FIG. 4 is a configuration diagram of a first embodiment.

FIG. 5 is a memory map of the host computer of the first embodiment.

FIG. 6 is a configuration diagram of a second embodiment.

FIG. 7 is a conceptual diagram of an address conversion table according to a second embodiment.

FIG. 8 is a conceptual diagram of a preferred address conversion table of the second embodiment.

FIG. 9 is a configuration diagram of an in-circuit emulator.

[Explanation of symbols]

 10: Electronic circuit 11, 13: Address bus 12: Host computer 14: Address resending means 15: Address conversion table 18: Control resending means 21: Data resending means

Claims (5)

(57) [Claims] 1. An address signal interposed between an address bus or an address terminal of an electronic circuit to be analyzed and an address bus or an address terminal of a host computer. an address retransmitting means for retransmitting to the side, the address retransmission hand
The column is a predetermined area of the address space of the host computer.
And the address space of the electronic circuit to be analyzed.
Address translation table, the address translation table
Files are accessed by the host computer.
An electronic circuit analyzer characterized in that data can be rewritten . 2. An address bus or address of an electronic circuit to be analyzed.
Address terminal and the address bus of the host computer or
An address that is interposed between the
Allocate the address signal to the other address space and send to the other side
Address resending means for resending, and a component of the electronic circuit.
Troll terminal and control of the host computer
Control that is interposed between terminals and sent from one side
Signal to the other architecture
Control resending means for resending to the
Be retransmitted means, when the address signal sent from the host computer is included in a predetermined area of the address space of the host computer, the electronic circuit analyzing apparatus characterized by performing the retransmission operation. 3. An address bus or address of an electronic circuit to be analyzed.
Address terminal and the address bus of the host computer or
An address that is interposed between the
Allocate the address signal to the other address space and send to the other side
Together with the address retransmitting means for retransmitting said address retransmission means, when the address signal sent from the host computer is included in a predetermined area of the address space of the host computer, when executing the retransmission operation
A predetermined area of the address space of the host computer;
Address changes between the address space of the electronic circuit to be analyzed
Conversion table, and the address conversion table
Means that data is accessed by the host computer.
An electronic circuit analysis device characterized by being able to rewrite data. 4. An address bus or address of an electronic circuit to be analyzed.
Address terminal and the address bus of the host computer or
An address that is interposed between the
Allocate the address signal to the other address space and send to the other side
Address resending means for resending, and a component of the electronic circuit.
Troll terminal and control of the host computer
Control that is interposed between terminals and sent from one side
Signal to the other architecture
Control resending means for resending to the
The means for resending data is the address sent from the host computer.
Address signal in the address space of the host computer.
Perform the resending operation when it is included in the fixed area
Together with a predetermined area of the host computer's address space.
Address and the address space of the electronic circuit to be analyzed.
An electronic circuit analysis device having a conversion table . 5. An address bus or address of an electronic circuit to be analyzed.
Address terminal and the address bus of the host computer or
An address that is interposed between the
Allocate the address signal to the other address space and send to the other side
Address retransmitting means for retransmitting, controls said a control terminal of the electronic circuit interposed between the control terminal of the host computer retransmits the control signal sent from one to convert in accordance with the other architecture to the other side Resending means and data of the electronic circuit.
Data bus or data terminal and the data of the host computer.
Data bus and data terminals, and sent from one
Data signal sent to the other data bus or data terminal
Resend to convert to the format of the data and resend to the other side
Means, and the address retransmitting means comprises a host computer.
Address signal sent from the host computer
Data is contained in a predetermined area of the data address space,
Executing the retransmission operation, and
Address area of the electronic circuit to be analyzed.
Having an address translation table between the address space and
The address translation table stores the address from the host computer.
An electronic circuit analysis device characterized in that data can be rewritten by access .