JP2680475B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor suitable for use as a memory for image data that requires high-speed data rewriting. Memory device

(Prior Art) FIG. 7 is a schematic configuration diagram of a conventional semiconductor memory device. As can be seen from FIG. 7, in this semiconductor memory device, the address AR / AR bar (A1R / A1R bar to AXR / AXR bar) is input to the row decoder RD. The row decoder RD selects one of the word lines WL1 to WLs. Further address A (N + 1) / A (N + 1) bar ~AMC / AMC 1 single column decoder CD2 bar is input P (= 2 ^MN)
Column decoders CD1 (1), CD1 (2), ..., CD (P)
One of the following. Addresses A1C / A1C bar to ANC / ANC bar are input to each column decoder CD1. Each column decoder CD1 selects one of the 2 ^N = j column blocks CB in the memory unit MP. Each column block CB
Has n columns C, and n data can be input / output simultaneously. It is a so-called xn bit, 2 ^N column specification. In each column block CB, the memory cell MC includes s N-channel MOS transistors Q1, Q2, ...
And s N-channel MOS capacitors C1, C2, ... Connected to those transistors. Each transistor is connected to one of the pair of bit lines BL and NBL and each word line WL. And
The n pairs of bit lines BL1, NBL1; BL2, NBL2; ... Are connected to the n sense amplifiers SA1, SA2 ,. The n sense amplifiers SA1, SA2, ... Include n pairs of input line I / O1, through n pairs of N-channel MOS transistors Qp1, Qp2, ..., Qn1, Qn2 ,.
It is connected to NI / O1; I / O2, NI / O2, ... n pairs of input lines
I / O1, NI / O1; I / O2, NI / O2, ... are n input drivers IO / D
Are connected to 1, IO / D2, ... And n pieces of data D1, D2 ,. On the other hand, n pairs of transistors, for example, the gates of transistors Qp1 and Qn1, Qp2 and Q
A control column decoder CD1 is connected in parallel to the gate of n2, the gate of Qp3 and Qn3, the gate of Qp4 and Qn4, and the like. That is, n columns in one column block CB are simultaneously selected by the output from the decoder CD1.

WI / O1, WI / O2, ... are input / output pins.

In the above device, data writing to the memory cell is performed as follows. That is, n input drivers
IO data D1, D2, ... are given to IO / D1, IO / D2, ..., and column address A1C / A1C bar to ANC / ANC are given to the column decoder CD1.
Give a bar, column address A to column decoder CD2
(N + 1) C / A (N + 1) C bar to AMC / AMC bar are given. As a result, n pieces of data D1, D2, ... Can be written to each of the n columns by one access. That is, n pieces of write data D1, D2, ...
Are given to n pairs of input lines I / O1, NI / O1; I / O2, NI / O2, ... through the input buffers (input drivers) IOD1, IOD2 ,.
N pairs of bit lines BL1, NBL1; BL2, N from n pairs of transistors Qp1 and Qn1, Qp2 and Qn2, ... acting as transfer gates through n sense amplifiers SA1, SA2 ,.
Supplied to each of BL2, ... As a result, through n transistors Q1, Q2, ..., n capacitors (cells)
The n pieces of data D1, D2, ... Are simultaneously written to C1, C2 ,.

When the semiconductor memory device having the above-mentioned configuration is used as an image memory, a normal write cycle or a high speed write cycle using a page mode or the like may be used for writing data. Many. In this case, the number of data that can be written by one access is n, which is the same as the number of input drivers IO / D1, IO / D2, ....

(Problems to be Solved by the Invention) Since the conventional semiconductor memory device is configured as described above, it has the following problems. That is,
Very little data can be written by one access. Therefore, it is not suitable for use as a memory for images. That is, in order to satisfy various image processing functions such as painting and color display, it is difficult for the conventional memory device described above to handle a small amount of write data and a low processing speed.

The present invention has been made in view of the above, and an object thereof is to provide a semiconductor memory device capable of writing a large amount of data with one access.

[Configuration of the invention]

(Means for Solving the Problems) In the device of the present invention, a plurality of memory cells are arranged in a matrix, and each memory cell is connected to one word line and one bit line, and each word The line activates the memory cell connected to it,
One bit line is for inputting / outputting data to / from one of the activated memory cells, and the memory cell is divided into p column blocks arranged in the row direction. The block has j columns, and runs in the column direction common to the plurality of column blocks.
A memory cell array having one data line, and the i-th one of these data lines is connected to the i-th bit line in each column block via a switching element, and a 1-bit data line. It is possible to repeat the cycle of the data input terminal to which is added and the latch and output of the added 1-bit data. Depending on the timing of the cycle, the added data can be used as write data or as a column direction mask control signal. As a mask control signal including at least one of I / O direction mask control and a signal, a register that can be output, a row decoder that selects one of the word lines, and a first column address are added, and the address is decoded. And a first column decoder that outputs one of the first column selection signals The second column address is input, the address is decoded, one of the second column selection signals is output, one of the column blocks is selected, and the j switching elements in the selected column block are turned on. A second column decoder for connecting bit lines of all columns in a selected column block to corresponding data lines, and a plurality of switches for connecting the register and the j data lines in parallel, Each of these switches individually turns on and off between the register and one of the data lines, and a plurality of switches are switched to a normal mode and a block write mode by adding a mode switching signal. When one of the data lines is turned on, one of the switches is turned on in response to one of the first column selection signals from the first column decoder. Connected to the register, the block write mode, regardless of the first column selection signal output from said first column decoder,
A control circuit for turning on all of the switches to connect all the data lines to the registers and for performing a mask operation by the mask control signal, wherein the control circuit has j column direction mask circuits. ,
Each mask circuit is connected in series between each data line and the register, and each mask circuit includes one of the first column selection signals from the first decoder and j column direction masks. A first switch circuit which receives one of the signals and a mode switching signal and outputs one of the first column selection signal and one of the column direction mask control signals depending on the level of the mode switching signal;
A second switch circuit, to which the output of the first switch circuit is applied and which cuts off between the data line and the register by the output, is configured.

(Operation) In the normal mode, the first column decoder (CD1) connects the register (CR1) to one data line (eg DQ1, NDQ1)
The second column decoder (CD2) selects one memory cell block [eg CB (1)]. As a result, the write data is transmitted to one data line (DQ1, NDQ1) via the register (CR1). In addition, in this state, only one memory cell block [CB (1)] is selected, so that in the selected memory cell block [CB (1)], the data line representing the write data is Write data for one convenient memory cell connected via the bit lines (BL1, NBL1). On the other hand, in the block write mode, the first column decoder (CD1) connects the register (CR1) to all j data lines (DQ1 to DQj, NDQ1 to NDQj), and the second column decoder (CD ″) is 1 One memory cell block [eg CB (1)] is selected, whereby one write data is fan-shaped through the register (CR1), and j
It is transmitted to all the data lines (DQ1 to DQj, NDQ1 to NDQj). Therefore, this one data is connected to all the j bit lines (BL1 to BLj, NBL1 to NBLj) in the selected memory cell block [CB (1)] and connected to those bit lines in total. Is written in the memory cell.

In the block write mode, the function of the column direction mask that makes the number of data lines connected to the register any number, and the number of memory cell blocks selected by the second column decoder (CD2) make any The function of the O-direction mask can be selectively or simultaneously provided.

(Embodiment) FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

This device shows a device capable of simultaneously writing n bits. The circuit for each bit has the same configuration.
1st bit (WI / O1) part (1st memory unit UNT
(1)) will be mainly described. Second column decoder CD2
Address A (N + 1) C / A (N + 1) C bar to AM
The C / AMC bar is input and one of the decode signals CS21 to CS2p is output as a decode signal. The decode signal is added to the memory unit MP (1). A column control circuit CC (1) is connected to the memory unit MP (1).
One of the decode signals CS11 to CS1j from the first column decoder CD1 is added to the circuit CC (1). That is, the decoder CD1 has the address A1C / ATC bar to ANC / AN.
C bar is added, and it is decoded and decoded signal CS1
Outputs one of 1 to CS1j. The control circuit CC (1) includes a color register CR1 and a driver IOD1.
Input / output pin WI / O1 is connected via. The same applies to the other memory units UNT (2) to UNT (n).

Part of the circuit of FIG. 1 is specifically shown in FIG.
That is, FIG. 2 shows in detail the portion of the first unit UNT (1) of FIG. The memory unit MP (1) is the second
The memory unit MP (1) has the same configuration as that of the memory unit MP (1) shown in FIG. Therefore, the same parts are designated by the same reference numerals.
Also, the control circuit CC (1) is for each column block.
It has j sub-control circuits SCC (1) to SCC (j) corresponding to the number j of columns in CB and one WI / O mask control WI / O.MC. Each sub control circuit SCC
Has a switching circuit CMC and a DQ buffer DQBuf.

First column decoder CD1, control circuit CC (1)
The details of are shown in FIG.

The decoder CD1 has j NAND circuits NAND11 to NAND1j. Each NAND circuit has address A1C / A1C bar to ANC / A
NC bar is added, and the output end is 1 of inverters IV11-IV1j
Connected to the control circuit CC (1) through the two.

In the switching circuit CMC1 in each sub-control circuit SCC in the control circuit CC (1), the decode signal CS11 from the decoder CD1 and the time t to the input / output pin WI / O1 are input.
₄ and the input data D1 (t ₄₎ of the (first reference 5 Figure) are input in parallel. The switching circuit CMC1 switches between the signals CS11 and D1 according to the level "1" or "0" of the control signal BW and outputs the signal.
Output as CM1. This output CM1 is the DQ buffer DQBuf1
Is added to Buffer according to the level "1", "0" of CM1
DQBuf1 is in the state where the input is connected to the output and the state where it is disconnected.

The row decoder RD is configured as shown in FIG. 4, for example.

The apparatus shown in FIGS. 1 to 4 has two operation modes (normal operation mode and block write mode), and in the block write mode, column-direction mask / I / O respectively.
The function of the direction mask can also be provided.

 First, the normal operation mode will be described.

In this mode, decoders RD, CD1 and CD2
One memory cell MC is selected for each WI / O. Each color register CR1 is previously stored in the selected one memory cell MC.
The data stored in ~ CRn is written.

That is, focusing on the first bit, as can be seen from FIG. 2, the row decoder RD selects one of the word lines WL1 to WLs. Now, assume that the word line WL1 is selected. The column decoder CD2 outputs one of the decode signals CS21 to CS2p. For example, the decode signal CS21 is output, and j columns C (1) to C in the memory cell block CB (1) are output.
It is assumed that (j) is activated. The column decoder CD1 outputs one of the decode signals CS11 to CS1j. For example,
It is assumed that the decode signal CS11 is output. The signal CS11 is applied to the switching circuit CMC1. As can be seen from FIG. 3, the control signal BW is also added to this circuit CMC1. This signal BW is at "0" level in the normal operation mode. Therefore, the level "1" of the input signal CS11 is output
It is added to buffer DQBuf1 as CM1. This allows
The buffer DQBlf1 is switched to the on state (a terminal side). On the other hand, the WI / O mask control W / IO / MC operates the data D1 (t) added to the pin WI / O1 at time t2 in FIG.
It is switched to the ON state (non-masked state) by the "1" level signal in 2). As a result, the data D1 previously stored in the color register CR1 is written in the memory cell MC (1).

 Next, the block write mode will be described.

In the case of this mode, regarding the first bit, for example, the data stored in the color register CR1 in advance is stored in the column block CB (1) among the memory cells connected to the word line WL1 shown in FIG. 5) in j) are written simultaneously. The same applies to the 2nd to nth bits in FIG.

That is, it is assumed that the row decoder RD selects the word line WL1, the first column decoder CD2 outputs the signal CS21, and the second column decoder CD1 outputs the signal CS11. In this mode, the control signal BW is "1".
Therefore, the switching circuits CMC1 to CMCj are all on the D1 side (b
Terminal side). For this D1, time t4
D1 (Fig. 5) is taken in. In this mode, D1 = “1” at t4. For this reason,
"1" is added to the buffers DQBuf1 to DQBufR as CM1. Therefore, all the buffers DQBuf to DQBufj are turned on. On the other hand, at time t2, D1 is added to the WI / O mask control WI / O · MC. Therefore, the mask control WI / O / MC is in the ON state. As a result, the data D1 previously stored in the color register CR1 is stored in the word line WL among the memory cells in the column block CB (1).
Written to j things leading to 1.

A mask in the I / O direction and a mask in the column direction can be applied in the block write mode.

First, the mask in the I / O direction in the block write mode will be described.

As can be seen from FIG. 2, data D1 was added as a control signal to the WI / O mask control WI / O / MC corresponding to the input / output pin WI / O1. In other words, the mask control WI / O / MC corresponding to the nth bit has the pin
Data Dn (t2) added to WI / On at time t2 is added as a control signal. In the simple block write mode, at t2, n pieces of data D1 (t2) to Dn (t
All of 2) are at the "1" level. However, when masking in the I / O direction, n pieces of data D1 (t2) to Dn (t2)
Any one of them may be set to "0". Data of “0” Dn
No data is written in the memory unit MP corresponding to the mask control WI / O / MC to which (t2) is added.

Further, masking in the column direction in the block write mode is performed as follows.

That is, for example, description will be made with reference to FIG. The "0" level data Dj (t4) at time t4 may be added to any of the switching circuits CMC1 to CMCj. Thereby, for example, "0" data is added to the buffer DQBuf1. The buffer DQBuf1 is switched to the off state (Fig. 3). As a result, the data in the color register CR1 is not transmitted to the data lines DQ1 and NDQ1. Thereby, for example, the column C in the column block CB (1)
Even if writing to the memory cells in (2) to C (j) is performed, writing to the memory cell belonging to column C (1) is not performed. That is, the mask is applied in the column direction.

In each of the above explanations, for the sake of clarity, only the part of the circuit has been focused on. However, in other portions having the same configuration, writing is performed in each mode in the same manner as the above description.

The timing of the above block write is shown in FIG. That is, the row address (C) and the mask data (G) are determined at the timing t2. At this time, the column address strobe CAS bar (B) is at H level, and DT / OE bar (E)
Is at the H level and DSF (F) is at the L level, the block write mode is entered.

Alternatively, at timing t4, the column address A3C / A3C bar to A8C / A8C bar (C) and the column selection (G) are determined. At this time, when DSF (F) is at H level, block write is executed. By the way, when the column address strobe CAS bar (B) falls (t4), the column address input is A3 which is input to the column decoder CD2.
The addresses A1C and A2C which are C / A3C bar to A8C / A8C bar and are input to the column decoder CD1 are invalid address data.

In the block write mode, the mask function can be provided. As shown in the timing chart of FIG. 5, the mask function in the I / O direction is turned on / off according to the level of the WB / WE bar (D) at the time of the fall of the row address strobe RAS bar (A) at the timing t2. . That is, when the WB / WE bar (D) is at the L level, the masking function in the I / O direction becomes effective, and the masking in the I / O direction is performed according to the level of the input data D1 to D8 at this time. That is,
When the data D1 to D8 is at the H level, the mask is not applied in the I / O direction, and when the data D1 to D8 is at the L level, the mask in the I / O direction is enabled. Further, masking in the column direction is performed with the data of the data D1 to D4 (G) at the time of falling to the column address strobe CAS bar (A) at time t4.

Tables 1 and 2 show examples of the mask function in the I / O direction and the column direction during block write. As shown in Table 1, when the input data D1 to D8 is "01100111",
As shown in Table 2, the data corresponding to the input data D1, D4, D5 is masked. On the other hand, when the column block selection data selected by the input data D1 to D4 is "1101", the column 3 is masked as shown in Table 2. As a result, when "00110101" is written in advance in the color registers CR1 to CR8 through the input drivers IOD1 to IOD8, as shown in Table 2, the color registers CR1 to C are set in the unmasked bits and columns.
The contents of R8 will be written.

Table 2 shows the following in relation to FIG. That is,
Now, it is assumed that the decoder DC2 selects the decoder DC (1) and the control unit BLW selects the block write mode.
When the mask function is not operating, the data “00110101” stored in advance in the color registers CR1 to CR8 (see Table 1)
Is written in each of the four column blocks CB (1) to CB (4). That is, for example, regarding the column block CB (1), columns C (1) to C (8) of the memory cells MC selected by a certain word line WL are included.
Memory cells MC belonging to "0", "0", "1", "1", "0",
"1", "0", and "1" data are written to each one.
The same applies to the columns C (1) to C (8) of the column blocks CB (2) to CB (4). On the other hand, when the mask function is operated and the mode is as shown in Table 2, data writing is performed as follows. That is, in the column block CB (3), writing is not performed on any of the columns C (1) to C (8). That is, the data remains as it is. In the column blocks CB (1), CB (2), CB (4), writing is not performed for the columns C (1), C (4), C (5). As a result, for example, regarding the column block CB (1), the columns C (2), C
For the memory cells belonging to (3), C (6), C (7), and C (8), the data "0", "1", "1", in the color registers CR2, CR3, CR6, CR7, CR8 "0" and "1" are written, and writing is not performed to the memory cells belonging to the other columns C (1), C (4) and C (5).

 The input data D1 to D8 can be set arbitrarily.

The control signal BW is generated, for example, by the circuit shown in FIG. Signals BRIN and BCIN applied to NAND in the figure
And DSIN are signals synchronized with the rising and falling edges of the signals RAS bar, CAS bar and DSF bar, respectively.

As described above, according to the present embodiment, it is possible to write 2 ^N times as much data as one access compared to the conventional RAM, and if the data amount is the same, 2 ^N times as much writing speed can be realized. . For example, in the case of the block write in the 4-column specification, N = 2, and it is possible to write 2 ² = 4 times the data amount at a time. Further, the block light is very effective in the processing of image processing, such as filling of a rectangular area.
For example, if the I / O direction corresponds to the pixel direction, ×
8 bits configuration, 8 for block write with 4 columns
It is possible to write simultaneously for × 4 pixels. Further, by specifying the mask function, the processing on the boundary of the area can be performed very easily and at high speed. Furthermore, when I / O is used as color information, 8 ×
It is also possible to use 8 out of 4 bits as color information and 4 as data in the pixel direction.

As described above, according to the embodiment of the present invention, since the same data can be simultaneously written in each column of a plurality of column blocks, the amount of data that can be written by one access increases, and the data can be written at high speed. It becomes possible to write,
Further, the mask function enables delicate control of write data, and thus a semiconductor memory device effective for image storage or image processing can be obtained.

〔The invention's effect〕

According to the present invention, the mode can be switched between the normal mode and the block write mode. Therefore, there is a writing method of writing one data to a memory cell in one column in a memory cell block, and one data. It is possible to write data in the memory cells in all the selected columns in the memory cell block.

That is, in the normal mode, one switch that connects the register for storing the write data and each of the plurality of data lines can be turned on by the first column decoder, so that one write data is converted into one data line. Transmit,
The one data can be sent to one bit line connected to the one data line through a switch and written to one memory cell connected to the bit line. Further, in the block write mode, the write data is written. Since all the switches connecting the storage register and each of the plurality of data lines can be turned on by the first column decoder, one write data is transmitted to the plurality of data lines, and the one data is transmitted to the plurality of data lines. Each bit line connected to the data line can be sent to each bit line via each switch to write data in each memory cell connected to the bit line. That is, one data can be written into one memory cell for convenience and a plurality of memory cells can be written for convenience, and these can be used properly.

Further, according to the present invention, since a register is connected to the data input terminal and the data can be output as the write data or the mask control signal according to the data input and output cycle in the register, the same input terminal can be output. It is possible to selectively use the data of (1), and thus it is possible to achieve the intended purpose of the data write mask while reducing the number of input terminals.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a specific example of a part of the circuit, and FIG. 3 is a circuit diagram showing a specific example of each block in FIG. FIG. 4 is a circuit diagram showing an example of a row decoder, FIG. 5 is a timing chart for explaining the operation of the embodiment, FIG. 6 is a circuit diagram showing an example of a circuit for generating a signal BW, and FIG. FIG. 4 is a schematic configuration diagram of a conventional semiconductor memory device. UNT ... memory unit, MC ... memory cell, WL ... word line, BL ... bit line, CB ... column block, RD ...
... row decoder, AR / AR bar ... row address, CD1 ...
… First column decoder, CD2 …… Second column decoder,
A1C / A1C bar to AMC / AMC bar ... Column address, CS21
~ CS2p …… Second column selection signal, CS11 to CS1j …… First column selection signal, DQ …… Data line, WI / O …… Data input terminal, CR …… Register, BW …… Mode switching signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References Japanese Patent Laid-Open No. 1-3897 (JP, A) Japanese Patent Laid-Open No. 61-289596 (JP, A)

Claims (1)

(57) [Claims] 1. A plurality of memory cells are arranged in a matrix, each memory cell is connected to one word line and one bit line, and each word line activates a memory cell connected to it. One bit line inputs / outputs data to / from one of the activated memory cells, and the memory cell is divided into p column blocks arranged in the row direction. Has been done,
Each column block has j columns, and further has j data lines running in the column direction common to the plurality of column blocks, and the i-th one of these data lines is the column block. It is possible to repeat the memory cell array, the data input terminal to which 1-bit data is added, and the latch and output cycle of the added 1-bit data, which are respectively connected to the i-th bit line in Depending on the timing of the cycle, the added data can be output as write data or as a mask control signal including at least one of a column direction mask control signal, an I / O direction mask control and a signal. , A row decoder for selecting one of the word lines, and a first column add Address, the first column decoder which decodes the address and outputs one of the first column selection signals, and the second column address which is input and decodes the address and one of the second column selection signals To select one of the column blocks, turn on the j switching elements in the selected column block, and connect the bit lines of all columns in the selected column block to the corresponding data lines, A second column decoder, and a plurality of switches for connecting the register and the j data lines in parallel, each switch being individually turned on between the register and one of the data lines. , The switch is turned off, and a mode switching signal is applied to switch between the normal mode and the block write mode. By turning on the one of said switches receiving one of the first column selection signal from Mudekoda, connect one of the data lines to the register, the block write mode, the first
Regardless of the first column selection signal output from the column decoder, all the switches are turned on to connect all data lines to the registers, and a mask operation is performed by the mask control signal. The control circuit has j column-direction mask circuits, each mask circuit is connected in series between each data line and a register, and each mask circuit is connected to the first decoder from the first decoder. One of the one column selection signals, one of the j column direction mask signals, and the mode switching signal are added, and one of the first column selection signal and the column direction mask control is performed depending on the level of the mode switching signal. The first switch circuit, which outputs one of the signals, and the output of the first switch circuit are added, and the output of the first switch circuit adds the data. Having a second switch circuit for Tsudan between lines and registers, semiconductor memory device.