JP2662533B2 - Logic analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer having a disassembly function.
Converts input data to the corresponding symbol set for Iza
Logic analyzer with display function. Execution of a system mainly composed of processing units
Relocatable objects to develop possible code
Use compilers or assemblers that generate code.
And very many. Such a program is continued one after another.
And load it from the logic state analyzer.
It takes time to recognize the list of available traces
In the worst case, it cannot be recognized. Even a disassembler
Also use any address signal in the original source program
Cannot be replaced with the corresponding symbol. To replace
How different software tools interact
How to create relocatable object code
Need to know how to make the final absolute value
You. Turn traced events into a set of source programs
A significant amount of non-decimal arithmetic is required to make
You. The hardware of the system under test must be normal
I know, debugging is just software
The problem becomes even more complicated. But many
Hardware and software bugs
there's a possibility that. So what happened
Therefore, it is possible to analyze based on information trace
Of particular importance. Does not work as programmed
In many cases, in this case, trace
It is not wise to think of a hardware version of
Think of the gram list as a guide for understanding the trace
Is useful. Therefore, if you do not rearrange the trace,
Traces can be quite annoying. tray
The absolute value corresponding to the address and operand
It is particularly desirable to replace the symbols with those used in the original source program.
It will be better. Such symbols are in individual places or
Refers to a range of locations. Enter source program
If you can define similar symbols in addition to
Useful. The reference sign of the line number in the source program is
Race or on the line of the actual source program
It is also useful. This caused the entire program flow
It will be a great help when going. In the logic analyzer of the present invention,
Other improvements and troubleshooting related to the operation of the remote machine
Includes items related to Statema
The trace for thin is 001001,010001,010011 etc.
This is a series of successive states. In such a state, "IN
"CP-REG" (step up the P register), "WAIT-MEM"
C ”(wait for storage to complete) or STM (note
Start a memory cycle)
Often it is possible. Logic analyzer tray
That such labels can be used
Is desirable. Each state in this list is a label or a label
Will be one of the values associated with Some in the latter case
Several states during the process, for example a memory read cycle
There may be. Label RMCY indicates the initial state of the process
You. RMCY + 3 is in the group labeled RMCY
This shows a fourth state. The logic analyzer source program described here
Ability to include system symbols and lines in the trace list
Forces the code (absolute or re-
Compiler or assembler that generated
Calling the symbol table created by
Link analyzer or relocation loader
Arising from invoking your decision. This information
Use the logic analyzer during various inspection processes.
Can be used in the trace list
it can. Yet another benefit comes from the ability to do this. logic
Analyzer extends the process of defining trace conditions
And can be simplified. Depends on trace conditions
This determines the conditions for starting the trace and the information to be imported.
You. According to the invention, which absolute value is taken
Without knowing, write the source program in the trace condition.
No. can be used. This means that their absolute values
When a bug is found and fixed or in a different variant
Change as software is developed and tested
This is extremely useful. However, various symbol tables and low
Logic analysers configured to use map
Isa simply means that one or more programs have a different length than before.
Or the program is loaded in a different order
Need to change the trace condition
There is no. Depending on the symbolic nature of the relocatable trace condition,
It becomes unnecessary. These principles are based on a system under test incorporating a memory management device.
Applies to logic analyzers done with
Can be extended to In such a system to be measured,
The relocatable address at which the processing device operates
Is further modified in real time by the storage manager
A de facto address. The corrected address is stored in memory
The actual physical address sent to the device. The value is
Which parts of storage are assigned to which programs or tasks
It is determined by the operation time condition indicating whether the operation has been performed. This percent
This is dynamic and generally involves relocation addresses that exist during operation.
Given as a fixed absolute offset to be applied to the
I can not do such a thing. This relocated address is itself
Assembler or compiler generated based on some relocation
This is the offset from the relocated address. like this
Addresses managed by various storage devices are displayed in the source list.
A certain amount of offset from the relocatable value
Dynamically offsetting relocated values
Contains some absolute values resulting from The above dynamic offset is handled in the system under test
Not a separate one for
It need not be obscure to the riser. Various
Symbol representing dynamic offset to logic analyzer
Can be defined for Then the flow of offset
Certain criteria for maintaining public knowledge of
(Determined by the system to be measured)
Analyzer configured in accordance with the embodiment of the present invention
Continuously adjusts the "true" absolute trace specifications during operation
Tracing using the symbol determined by the user
Can be. Also, when the trace is at a position in the storage device,
A trace on a dynamically determined program
Even primitive symbols can be inserted into the trace list
Noh. Hereinafter, an embodiment of the present invention will be described. FIG. 1 is a block diagram of the logic analyzer used in the logic analyzer of the present invention.
Diagram showing the outline of the program and showing the functional relationships between the components
It is. Referring to Appendices A to U and referring to FIG.
The operation and utility of Ming will also be described. Then, from FIG.
The internal operation of the present invention will be described with reference to FIG. In FIG. 1, the main program 2 and the related sub
Gram 3 is a data structure 4 named "DATA-BLOCK"
Work with. In the case of this embodiment, the program 2 and the sub
Written in Pascal language together with Program 3
Have been. The name of the main program is "MAIN"
The name of the program is "FACTOR". These two paths
Related to local programs and their data structures.
While compiling RAM MAIN and FACTOR, PASCAL compiler
Utilities from the runtime library called by
There is a security program. It's called PARAMETER
Parameter Pass Routine 5 and the name MULTIPLY
Multiplication routine 6 and the specified bit in the specified word
BOOLEANIN to check if it is set
Name routine 7. For example, BOOLEANIN is PASCA
Used to evaluate the L "IF" statement. Below, this program
Let us briefly consider each of the system elements. Page i of Appendix A contains a page
The source list in PASCAL language of the program MAIN is shown
ing. Program MAIN sets data structure DATA BLOCK to 0
To the successive factorial powers of up to 20 consecutive integers. To do this
Is an external name that is conveniently named DATA BLOCK
Reference an integer array. The index into the array is INDEX
Named and supplied with an external FACTORAIAL
A value n! Is sent back to the integer n. A simple FOR
The loop calculates the factorial of the value of the index
Assign if specified. This is the point from 0 to 20
Data value. Source of functional subprogram FACTOR in PASCAL language
List on Page i of Appendix B (PAGE i OF APPENDIX B)
Show. About the logical structure of subprogram FACTOR3
Not detailed. Programs MAIN2 and FACTOR3 are just example situations
As part of the work piece. This is FA
Includes confirmation or troubleshooting of CTOR operation
I have. More specifically, this example involves three supply values.
Includes tracing FACTORIAL behavior
You. To do this, pass the parameter NUMBER to the function FACTORIAL.
And execute the IF statement on statement number 10 using BOOLEANIN
Items such as summing with sentence number 12
You. To state these matters, the relevant part of the trace is
To consider with the Gic State Analyzer
So during this important part of FACTORIAL
Because you can observe what is happening. In short, this
The idea is that the input, the output, and some important points in between
Is to observe. Page i of Appendix C (PAGE i OF APPENDIX C) is MAIN
Satisfies the referenced "external" and satisfies the storage requirements of the integer array.
Annotated assembly language program DATA BLOCK to give
It is. The operation part of the DATA BLOCK is line number 21. here
Has 21 words under the "BSS21" directive, the first of which
Is related to the symbol DATA BLOCK. Program DATA BLO
CK should not generate executable code
Is also a text file that can be assembled
Program by taste. The important thing in the current example it does
Is the name of all assembly language labels in the program.
To create a symbol table. One of them is DATA BLO
CK. This becomes important for words. Important incidental matters
"BSS21" directive is still a program size value
Is to increase. This will later be
An easy way to make BLOCK look 21 words long
Therefore, those words are generated by the assembler
Has the effect of retaining 21 words even if it does not contain
You. To run the workpiece program, run the program
Compile MAIN2 and FACTOR3 with appropriate PASCAL compiler
And insert DATA BLOCK4 into the appropriate assembler (i.e.
Process in the system under test that executes the
Must be assembled in one of the
No. Then you have to rearrange and load all the work
Absent. Then the work piece program becomes executable
You. During this run, the logic analyzer
The specified condition (defined by the trace condition) has occurred
To select all events or only selected events.
It can be traced selectively. (All here
Event will be selected). The format format is "A
Dress, Data, and State logic configurations
Characteristics of the electrical signals monitored by the
Match to special groupings. The trace obtained is a trace
Record of system operation near the conditions specified in the
You. In the trace in each appendix, the trigger event is
It is traced third and traced from a large number of traces.
You can see what happened following the Riga event. But first
First, compile and load programs MAIN2 and FACTOR3.
Must be done. Appendix C uses DATA-BLOCK4
The results have already been shown. With this in mind, programs MAIN2 and FACTOR3
Compiled extension compiler for Appendix D and E
Think of a table. The ultimate goal of the example follows the trace condition
Is to get a good trace. Where INDEX is an integer
Ready to start tracing when assigned the value 3
And the address is equal to FACTORIAL and the status is opcode
Indicates when to trigger when is equal to (ie,
The first object code directive for FACTORIAL is
Fetched for execution). Such traces
In order for the matter to be effective,
Syntax features of each logic state analyzer
According to the appropriate switch settings and key movement union
Not only have to translate
Special (ie absolute) for things like NDEX
You must give an address and a number. Also FACTOR
If the user calls another routine, the user
The addresses in those parts of the
Not ready to translate to a meaningful place
I have to. To do this, the user must use a linker or
Using the roadmap provided by the relocation loader
Knowing which routine contains such an address
Check the compiler table for that routine and
Trace what actions are represented by the trace
become. Duplications in the lists of Appendixes D and E in connection with these operations
Note that several important items appear. each
In the leftmost column of the list, the compiler will write
The relocatable address for each word of the generated code is written.
There is. Enter SOURCE LINE
Column shows the original PASCAL source that issued the relevant machine directive.
The line number of the list is listed. I got this source line
The machine code is shown below and entered. Appendix
On line 26 of page i of page D (PAGE i OF APPENDIX D)
INDEX (this is related to line 18 of the MAIN PASCAL source list)
User defined in the source program.
The resulting symbol becomes a code that uses the symbol INDEX. However
To use this INDEX, you now have an executable machine language
Execution definitions are needed during the gram shunt. This is Appendix D
In row 42 of page i, the relocatable hexadecimal address is 0010
This is performed using "BSS1" which is H. Logic stay
INDEX to run the example
For 0010H assigned to AIN compiled code
Must be replaced with the final relocatable number
No. What is the absolute address of the first command executed by FACTOR
Is actually specified by the conventional trace specification.
You need to do something like that. Utility programs PARAMETER5, MULTIPLY6,
And call BOOLEANIN7 again. The compiler uses
Generate code that uses the routine. Page of Appendix E
Lines 14, 22, and 38 of PAGE i OF APPENDIX E
See JSM Directive. In the trace in this example
Includes such a JSM and its related operations. This
Is not unreasonable, if something is wrong
If these utilities are used to understand the nature of the failure,
The behavior of a utility routine or other utility routine
You have to check the work. Now, when does the utility of a runtime library actually mean
Even a mysterious relocatable machine cord
There are some devices that are only programs. More progress
Methods can be relocated to the runtime library for each application
Not only functional code, but also the source itself or extensions
Include a text file containing the edited content
It is. If this latter method is available, a complete tray
The work in each of the following stages depends on the
There is no practical element of such a library to run
It is at least less complicated than it is. Appendix F, G, and
And H are three practical routines PARAMETER5 and MULTIPL, respectively.
Assembler list for Y6 and BOOLEANIN7
You. Page i of Appendix I (PAGE i OF APPENDIX I)
Gram MAIN to DATA BLOCK and library program
Where for each of up to MULTIPLY is run from the BOOLEANIN
It is a road map indicating whether or not the data is loaded. "PROG
Each block of code starts in the column labeled `` RAM''1
Hexadecimal value is described. Roadmaps such as those in Appendix I are included in Appendixes J, K, and
Relocatable list, as shown in the following example for
When tracing the flow of the program written with
It is what you need. APPENDIX J
Which probe is the address (Addr
ess) tracks, which are data tracks,
To let you know which is the status line, etc.
This is an expression specification. Each track name has a data label (data labe
l) It is described under. Data labels such as Status
Related to multiple numbers. That is, two or more states
Exists. These various numerical values can also be represented symbolically.
Can be arranged in a symbol map. Format
By design, the electrical logic pole that the signal is to follow
Gender and threshold level. Appendix K (APPENDIX K)
Logic State Analyzer works on workpiece
Information that is to be recorded while monitoring the execution of the ram
These are trace conditions that define the nature of the report. Evaluate the example
To investigate the properties of BPC (Binary Processor Chip)
It is not necessary, but the command sequence, bus structure and
See U.S. Pat. No. 4,180,854 for the internal configuration. By the way, the trace specification in Appendix K indicates that INDEX
Start tracing when assigned, address is FACTOR
When equals to IAL and state equals to opcode
It is a condition to trigger. To have this meaning
To create a race, enable "After address = ???
A constant and clear numerical value like "Yo"Don't give as
I have to. In other words, the user is in the second line of Appendix K
You have to reach a certain "8012H". This feature
In another example, "8012H" starts at MAIN and loads at 8002H,
Note that INDEX is at 10H (relocatable) of MAIN
Can be found. 8002H plus 10H equal 8012H. Also,
This is not a formidable task by itself, but
Arithmetic is needed in so many places when tracing is interrupted
become. Furthermore, the user memorizes 8002H, in hexadecimal notation
It is very complicated to adjust. Because it is a program
When the program changes (how many times this
May immediately be involved in completely different relocation criteria.
A new relocatable address appears to be involved
Because. So, this is a general statement about APPENDIX L
This is the situation, which is the program from Appendix A to H
Appendixes J and K to
This is an abbreviation of the tracking obtained. Page of Appendix L
"08013 LDA 8030" is displayed in the line of trigger (TRIGGER)
Note that there is. According to the roadmap in Appendix I
Address 8013H is the starting point of program FACTOR. line
+004 has "JSM 806D" and the line +006 is added to 806DH.
Les changes continue. Just looking at the trace in Appendix L,
The meaning of 806DH is unknown. To find out the meaning of 806DH
By first examining the roadmap (Appendix I)
806DH enters between 8069H and 808FH, so absolute
Need to recognize that Les 806DH points to something in PARAMETER
There is. The load-based hexadecimal value for PARAMETER is 806
9H. Subtract load-based hexadecimal value from referenced location
Subtract 0004H, which is relocatable in PARAMETER
Location. Well, the assembly list of PARAMETER (Appendix
Looking at line 49 on page ii) of F, location 0004H is labeled PARAM
Note that it is assigned to ETER ENTRY. But
So, "JSM 806D" is actually "JSM PAREMETER ENTRY"
It is. Similar analysis is related to other address changes (JMP, JSM, etc.).
Applies to RET and RET. Additional “macro” supplied by the user to the logic analyzer
In general, the specification specifies the style and trace specification.
And at the same time
Risers are relocated as required for symbolic trace specifications
And trace by symbol
The non-rearrangement necessary for the creation of the list can be performed. Attached
Record M (APPENDIX M) has two symbol maps
Such map specifications, each of which is a single value
Or in relation to various symbols for a range of numbers
I have. A single value can be specified independently in any radix.
You can also set irrelevant (don't care). these
Are absolute values, from the roadmap or absolute
Obtained from the list. In the general case, one or more of these
May contain a collection of unique symbol maps. Two or more
The reason why the above symbol map is necessary is that symbols are generally
Represent logically incoherent phenomena such as
It is. For example, the BPC microprocessing device described earlier
, The address of zero represents the A register,
Zero state (given certain control line grouping methods
Represents a store write cycle. Color
Need to separate different types of symbols into separate groups
Are thus separate and independent for the same value
Because you get it. These collections generally go to processing equipment.
Functionally represent the work represented by the various symbols that enter
This shows the split. However, the actual
It is absolutely necessary for the air signal itself to be incoherent
is not. What is needed is logical independence. For example, BP
In C, the address and data lines are one and the same.
However, different types of information occur at different times. Black
Qualify properties (see US Patent 4,338,677)
This makes the logic state analyzer
Are logically separated but electrically common
Components can be demultiplexed. This time, especially with reference to Appendix M,
The symbol FACTORIAL is specified on the line as a single unique absolute value 8013H
Have been. In the seventh line, the symbol Z is from absolute value 22H to 0C2H.
Defined as a range. All values that fall within this range
And may or may not fall within that range
Appears in the trace list in relation to the reference location. Standard
Start of range, end of range, or 0
It is convenient to select. However, other values are acceptable
May be executed. For example, the value in Z
Z plus or minus offset in source list
Appear as. However, the offset here is related to 42H.
Be involved. This feature indicates that if the index is zero, the symbol is compiled.
Useful for groups or arrays. In line 8 of Appendix M, the symbol MAIN relates to the beginning of the range
The absolute range is defined as 8002H to 8012H. 14th
Absolute range 0F9F0H where the symbol STACK on the line relates to the end of the range
To 0FA17H. Finally, on the 31st line, the symbol Error changes to 1 ××× B (×
Is irrelevant meaning). Binary 1000 to 2
Any value in the range up to 1111 hex in the trace list
Simply appears as the symbol Error. In this embodiment, the map specification is set in one of two ways.
Is determined. In the first method, the user can use various software.
Hardware tools (assembler, compiler, linker, etc.)
Some of them are located in various places other than the system to be measured.
(Some can be operated with different types of equipment).
A table of information corresponding to the desired map specification by collecting the information
Make up. The user then puts this information on a keyboard, etc.
Input to the logic analyzer. Turn on map use
The second method is to allow the user to copy files from a mass storage medium.
Start by preparing the information tables in the right format. Next
Insert a disk or tape into the logic analyzer
And load it into the logic analyzer
Command to read the file and get the map specification
Communication with the logic analyzer
become able to. File RS232 or IEEE488
It can be transmitted by any suitable data link. Changes to related style specifications in connection with the addition of map specifications
It is desirable to do. Appendix N (APPE
NDIX N), which is the previous style specification shown in Appendix J.
And somewhat different. Differences are at lines 15, 26, and 37
Appearing in a row. The meaning of line 15 is the data label address
The default symbol map for is the symbol map named Address-
That's what it means. Other suitable symbol maps of other names as well
It is possible, and if desired, one of them can be
Can be used instead. Same for the state map
The same general situation exists. The default map that applies on line 37
The map is identified as a map named Stat-Map.
Other state maps with different names can exist as well.
Wear. Line 26 denies the existence of the default data map.
Have been. The lack of such a map means that the data
Is simply represented by its absolute value in the trace list.
Means that In this example,
The absolute value base is reversed to hexadecimal when there is no specification.
Fault set. Finally, in the format specification
Therefore, even if such an omitted map is specified, the omitted state is actually
Choose which symbol map to use if achieved
It just does. Specifying some special symbol maps
And (somewhere else), in this case
The default state cannot be obtained. This "somewhere else" is a trace
In the list, which is also now in Appendix K, for example.
Somewhat different. Well, in Appendix O (APPENDIX O)
Indicates a modified trace specification. This is
Using the symbols for making the same measurements as specified in Record K
I have. However, although the symbol map is not described,
The short selection function is executed. Appendix O has another tray
The specification also shows that the measurement is completely different.
Become. It is the data given in the format specification
Ignore default choices specified for labels
This is because the number map is described. The important point is the symbol map
Actually executing the specification is a modified trace specification
Is to happen. Well, it is shown in pages i and ii in Appendix P (APPENDEX P).
The trace list shown is compared with the trace list shown in Appendix L.
Compare. In particular, the line +004 in Appendix L and the line +004 in Appendix P
Compare. The disassembled directive is listed as "JSM 806D"
On the other hand, the latter is "JSM PARAMETER + 000
4 ". "PARAMETER + 0004" is a parameter
Comes in source program for pass routine 5
PARAMETER corresponding to the symbol "PARAMETER-ENTRY"
Represents a relocatable location in a named file. This
In the case of the map specification in Appendix M, the symbol "PARAMETER-ENTR
Since "Y" is not included, it is in the range from 8069H to 808EH
All references to numeric values in the
Will be What is the absolute value 806DH and the symbol PARAMETER-ENTRY?
Both are the fourth places in the range. Refer again to the map specification in Appendix M. Symbol FACTORIA
L is specified as absolute value 8013H, and the symbol FACT
OR is specified to be in the range from 8013H to 8038H. FACT
ORIAL is thus a value in FACTOR. Well, in Appendix P
Look at the Trigger line on page i. FACTORIAL
Special values are written, for example, in lines +001 to 005
As the value related to the beginning of the range FACTOR
Is represented as FACTORIAL. In the page i of Appendix P, the lines +066 and +077 are opposite the reference position.
The range Z on the opposite side is demap-referenced. Line +075 is
Demap related to the end of its defined range 0F90FH to 0FA17H
Represents a reference to the STACK that was This time, from the Trigger line in Appendix P, +005, +066, +075,
And +077 to the same line in Appendix L. Appendix
It is clear that the trace list of P is quite easy to use.
It is obvious. In the trace list in Appendix L,
Itself is disassembled, but operands and addresses
Is unclear to the link to the symbol of the source program creation
There are many things that remain. Appendix P Training
Source list from line +065 to +074 trace is a professional
Program execution in Gram BOOLEANIN7
After program execution is in the range labeled FACTOR
And the FACTOR limits are used up to the range of executable code.
Support FACTOR3 for subprograms written by users
That it is clear that you know
In clear contrast. The trace list improved from Appendix P is partially described in Appendix M.
It is possible through the use of the map specification. However,
The special map specification is clearly improved, but what?
Excessive action needs to be added in the example of the user. You
In other words, the user can key the names of various symbols and their numerical values
I have to go in. This is the environment surrounding Appendix Q
Is in contrast. Returning briefly to Appendix I, tabular output from the linker
(I.e. a piece of information about the "roadmap")
Is line 18 "absolute & link-com file name = W
ORKPIECE: EXAMPL ". This
Its meaning is specified as "WORKPIECE: EXAMPL: link-sym"
In the relation file, among others, the name "user compartment"
Record of the range and its associated beginning and end in storage
Is included. User ward
The picture names are linked and loaded into various program sections
Is the same as the file name. Then, returning to Appendix Q, define ".... link-sym file WORKPIECE: EXAMPL"
I think ... This command is user-defined and part of the map specification.
Issue instead of keying in the name of the issue and its range.
The "... define ...." instruction itself is an appendix
Not shown as part of Q, but rather issued its order
The result. The results are shown in lines 25 to 34 of Appendix Q.
This is “linked-files” information. This is used in Appendix M
Some extra information compared to the map specification
Is to be part of. This extra information is in the range of the symbol
Is given a starting and ending value for.
This allows the address or operand to make it absolute
Any such range by simple means of expressing by value
Are within the range, while those within such range
Special notation as a unique symbol or related to its scope
Tray to be expressed as related to the issue
It will be possible later to show in the slist. Before examining the resulting trace list, it will be somewhat different
Trace specifications must also be considered. The user
Consider the trace specifications with the symbols INDEX and FACTORIAL.
Will be obtained. But with the new map specification in Appendix Q
Indicates that the information is implicit, but these symbols are
Not shown pleasantly. That is, the symbol INDEX is MAIN: EX
Overall in a file named AMPL (line 44 of Appendix D)
And the symbol FACTORIAL is FACTOR: EXAMPL
(See Appendix E, line 55)
Function is declared. This absolute connection
In the race specification, the file name MAIN: EXAMPL and the symbol INDEX,
File name FACTOR: EXAMPL and symbol FACTORIAL
It becomes clear by doing. Appendix R (Appendix R)
See lines 2 and 4. Next is shown on pages i and ii of Appendix S.
Consider the resulting trace list. First, the line
Observe the +004 example. This line of tracking now reads "FACTOR + 0
0002 JSM PARAMETER-ENTRY, PARAMETER .... ''
Have been. What is the difference between line +004 in Appendix S and line 004 in Appendix P?
Operand of JSM Directive is not just PARAMETER + 0004 but now
The degree is represented as PARAMETER-ENTRY. This
This is a file created when PARAMETER: EXAMPL is assembled.
Based on inspection. The actual complete specification of this file
Is PARAMETER: EXAMPL: asmb-sym. This is a file
Manages compilers, assemblers, and linkers, etc.
Operating system used to manage
Rules for `` file name: user id: file type ''
I do. "PARAMETR" following the operand of JSM is complete.
See full file specification. That is the operand of JSM
Identifies a file that is specified to symbolically represent
You. However, the display device is limited to 80 columns, and the user
Can recognize such "name: user id: type" rules.
It seems that it is only possible to give only the name part
In general, it is an appropriate compromise. For trace lists such as Appendixes P and S, the total value
(State analysis generated from logic state analyzer)
To the symbol (in the file used by the linker)
Looking. Using maps for the trace list in Appendix S
In the file WORKPIECE: EXAMPL
Finding the absolute value of a symbol with the more comprehensive nature of information
Operation for all addresses and operands.
You can do it. For example, refer to Appendix S, line +006
Teru. It is simply "... PARAMETER + 00004 STA PARAMETER
+0000 ..... ", not" .... PARAMETER-ENTRY, STA
DOPEVECTOR, PARAMETER .... " As mentioned in connection with Appendix S, once
Once you have the ability to inspect source files, trace
Source program that caused the runtime behavior to be caught by
Gram line numbers can be included in the trace list
become. For example, in Appendix T (APPENDIX T), Trigger
Lines to +004 relate to line # 8 of the source program
You can see that it is. Such associations are compiled
Source lines. The assembled source line is already
In general, word by word or byte by byte
Properties and object code that can execute the properties
Is similar to the
I'm coping. Appendix T contains the same trace list as before, such a source
Line numbers have been added. For example, line -00 in Appendix T
2, it is written as ".... # 18 MAIN00-L2, MAIN STM ..."
I have. This means that some source program in a file named MAIN
Compiler issues label MAIN00 L2 on gramming line 18
Issued a JSM command that was generated and executable.
You. The next executable directive is a file named FACTOR, etc.
Comes from sources that are Now consider Appendix U. Here
For tracing the examples used throughout the discussion of
There is a complete trace list of Contains line numbers
Not only one copy of each relevant primitive line
At the beginning of each block with a different source line number
ing. FIG. 2 is a block diagram of the logic analyzer of the present invention.
It is shown. Figure 2 shows the logic state analyzer.
Includes both riser and emulator. In FIG.
As shown, the logic state analyzer module
And the emulator module 9 are provided.
It works and is supported by the host system 10.
Emulation bus preprocessors are generally
Corresponds to the switching elements 13 and 14. As shown in Fig. 2, the logic state analysis
The module 8 connects the data to the system 50 to be measured.
Clock probe pod 11 and data probe
Received via the module 12 or the emulator module 9
Can be In any case, the present invention
With the data received by the state analyzer module 8,
Operate. To facilitate this, the logic state
The analyzer module 8 is a switching element,
Multiplexers 13 and 14 are incorporated. The host system 10 includes the emulator module 9 and
Both of the logic state analyzer module 8
Control behavior. An operation containing various instructions for this purpose
Rating system is coded in system ROM15
And is executed by the microprocessing device 17. With this control
Interacts with the user via the keyboard 18 and display 19
Operate and operate the “soft key”, “soft front panel”,
Concepts such as "proportion" are included. 22 is the I / O bus
Is. If a mass storage device 20 is present,
Recall instruction files to establish commonly used equipment
Stored in a labeled instruction file and executed at will
be able to. Similarly, the results of various measurements
It can be saved for analysis and comparison. Module of emulator and logic analyzer
8 includes preparing various tables of information
Some of this information is stored in the system RAM 16 area.
And some are in modules 8 and 9
Held in a callable location. These places are
Microprocessor address started by microprocessor 17
In response to a storage cycle on the data / data bus 21. to this
Therefore, the trigger recognition device 23 and the memory recognition device 24
Be able to program individually and selectively
Its proper recognition work on the measurement can be performed.
These operations ultimately cause the trace storage device 25 to
It produces status data on the remembered status bus 26. this
Is the raw data of the trace list and appendixes P, S, T and
U will be stylized as noted in any of the above. Such stylization is in part preferred as shown in FIG.
In the embodiment, the system ROM 15 of the host system 10 is copied.
Executed by the operating system
This is performed by various routines. This includes system RAM1
Various Finds In Any Of 6 And 20 Mass Storage
Examine various tables and files of information that can be
That is included. Much of this required information has been described earlier.
As you can see, users can use various software tools.
Various programs that can be traced using
Compile and assemble with RAM and data structures
And when loading. Now this information is exactly
What are the various trays drawn in Appendixes P, S, T, and U
Back to how it is used to make slists
I will do it. Appendix generates the example program for the workpiece in Fig. 1.
Files that are created on the way
The schematic layout of the files is shown. Attachments related to these files
The part of the record is also shown. Fig. 3 shows a table without appendixes P, S, T, and U.
Related to a particular type of data
Trace specifications, format specifications and map specifications
It is arranged in a diagram. In particular, captured data 27
The state analyzer module 8 stores the trace
This is to be stored in the device 25. This is used
As useful as possible and as easily as possible
Raw information that is supposed to work
You. This is, in turn, the software symbol 28 or the analysis symbol
Correct certain trace symbols 32 classified as any of 29
It is done by translating well. Software symbol 28
Are simply symbols that appear in various source programs.
Symbols passed by piles and assemblies
You. Analysis symbol 29 is the logic state analyzer module.
What the operator of the module has already specified in programming
Is required if the question is
You. In the present embodiment, each corresponding measured system
Related to the signal line and can take various values
Shows the case of a data label. For example, three tracks
State, or read, write, command fetch, etc.
It may have various absolute values to mean. This color
Various data labels have different values given symbolic names.
Map. Perform further analysis
The special program whose execution is being traced.
It is necessary to specify the corresponding symbol only for analyzing
Yes, you can add that symbol to the symbol map
If not, the symbol must be added to the source
Will be. Edit them again by adding them to the symbol map.
There is no need to edit, reassemble, reload, etc. Data label 30 is specified by format specification 34
However, the symbol map 31 is defined by a map specification 33.
Once these two specifications are made, the software symbol 28
The symbol which is one of the analysis symbols 29 to trace specification 35
Trace squirrel that can be used and then not rearranged
You can put it in 36. Therefore, analysis with software symbol 28
A symbol linked with the symbol 29 is called a trace symbol 32. Figure 4 shows the trace specification with the corresponding absolute address
Process flow to replace software symbol 28 in 35
It is a figure. Analysis symbol 29 can be included in the trace specification.
But its absolute value is obtained from the associated symbol map 31.
You. The flowchart for this has been omitted. Figure 5 is logic
・ In the trace list created by the state analyzer
The absolute value of
The process of replacing symbols with symbols according to race symbols
It is a figure. This flowchart illustrates the various specified
The procedure for searching for the type symbol is shown. If the user
In a symbol map whose absolute value has other signals associated with it
Is defined from a set of software symbols.
Indicates that the analysis symbol is the symbol used for the trace list.
You. This allows the user to source code during the debugging process.
Program without re-editing, re-assembling and re-editing
Software symbols can be renamed without loading
You. The following are described in Appendices T and U, respectively.
Source line numbers and trays containing source lines
Applied to source lists. That is, the line number is
And appear in the: asmb-sym file. The line is Taka
Are generally symbols in the list as if they were symbols.
Appears in the body column and is similar to the algorithm in the flowchart of FIG.
It can be extracted by an algorithm. In particular, judgment 37
Make small changes related to a positive path through
When needed line numbers can be provided so that process 38
And 39 must be adjusted. Also the source line itself
Process 38 also provides a source line if
You. The next note is that the present invention uses a storage device control unit (MMU).
When using in connection with the system under test
Apply. In such systems, the MMU is referred to as the processing unit.
Intercept the storage bus between storage devices. The logic analyzer
A dress probe is located between the processing unit and the MMU.
Special considerations must be taken when connected to addresses.
No need. The existence of MMU is indistinguishable. However, if the address probe is
If connected to a physical address between
Generally, some special actions are required. First, the MMU
Generally determined or selected by the operating system
Adjusting the address of the memory cycle according to the quantity
become. This amount is the contents of some callable registers
Sometimes. Logic analyzers are
Monitor the write operation to the
You have to do it. Then raw trace information
Mapping between the absolute value of the symbol and the available trace symbols
And used for various tracking, style, and map specifications.
In the other direction between the symbol used and its associated absolute value.
There is a change in the relationship of FIG. 3 for ping. The above
For the first mapping, the pre-subtraction is the physical location
make. As described above, the added amount is supplied to the MMU and
Will be monitored by the analyzer and will respond to previous commands. Another method of utilizing the present invention is in the mass storage device of FIG.
The file that was once in trace storage 25
It is related to the state including the image of the source. This
Trace files are logic state analysers
It is not necessary to even generate from the
No. The data in it is collected under completely different circumstances and collected.
Removable media and appropriate data links
Reach mass storage device 20 by a number of convenient means, including transmission
You can do it. Once in mass storage 20, this
Such a file is, according to the present invention, as if it were actually
It operates as if it came from the trace storage 25.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an outline of a program used in a logic analyzer of the present invention. FIG. 2 is a block diagram of the logic analyzer of the present invention. FIG. 3 is a diagram showing the relationship between trace specifications, format specifications, map specifications and each symbol of the logic analyzer of the present invention. FIG. 4 is a flow chart in the case of replacing symbols and absolute addresses of the logic analyzer of the present invention. FIG. 5 is a flow chart in the case of replacing a trace symbol and an absolute value of the logic analyzer of the present invention. 8: Logic state analyzer module 9: Emulator module, 10: Host system, 11: Clock probe pod, 12: Data probe pod, 15: System ROM, 16: System RAM, 1
7: Microprocessor, 18: Keyboard, 19: Display, 20: Mass storage, 23: Trigger recognizer, 24: Memory recognizer, 25:
Trace storage.

Claims (1)

(57) [Claims] A trace list generated from a source program that incorporates symbolic labels and representing symbolic labels of selected logic states that occurred during execution of the target system by linked and loaded and relocated machine code object programs. Generating a logic analyzer coupled to a file associated with linking and loading of the machine code object program, generated as a symbol label used in the source program, and a logic state in the target system.
Correspondence means for creating a correspondence table between corresponding rearranged absolute addresses in the rearranged machine code object program; and predetermined logic which is coupled to the correspondence means and sets a trace condition by the symbol label. A trace specification means for causing a state value to be included in the selected trace; a trace specification means coupled to the trace specification means and the target system, and generated by the target system and set by the trace specification means. Logic state collection means for collecting a value of a logic state satisfying a condition; storage means coupled to the logic state collection means for storing the logic state value collected by the logic state collection means; Storage means coupled to the storage means; A logic analyzer comprising: conversion means for converting a lock state value into an associated symbol label; and output means coupled to the conversion means for displaying a logic state included in the trace with a numerical value and a symbol label. 2. 2. The logic analyzer according to claim 1, wherein the correspondence table includes a correspondence defined by a user. 3. The converting means converts a value of a logic state falling within a range of an absolute address associated with a symbol label into an offset with respect to a predetermined number in the range, and displays the offset and the symbol label by the output means. The logic analyzer according to claim 1, wherein