JP2549001B2 - Video signal acquisition circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal capturing circuit suitable for application to, for example, a ghost removing device that captures a signal of a specific line from a video signal and processes the signal.

[Prior Art] As is well known, a signal (specific signal) different from the video information such as a character signal and a ghost removal reference signal is inserted in the vertical blanking period in the video signal. Conventionally, a video signal capturing circuit for capturing such a specific signal and processing the signal has been proposed.

An example of the video signal capturing circuit will be described with reference to FIG.

In FIG. 3, reference numeral 1 is an input terminal to which a video signal Vin output from, for example, a video detection circuit (not shown) is supplied, and the video signal Vin is supplied to the sync separation circuit 2 and the waveform acquisition determination circuit 3. It

The vertical sync signal separated by the sync separation circuit 2 is generated by the frame pulse FD and the horizontal sync signal generated by the horizontal pulse HD in this example.
The gate signal generation circuit 4 generates the gate signal GT.
This gate signal GT is supplied to the fetch determination circuit 3.

The capture discrimination circuit 3 captures the video signal gated by the gate signal GT and discriminates whether or not this signal is a target specific signal (ghost removal reference signal).

If it is not the specific signal, the error signal NG is sent to the gate signal generating circuit 4. When the signal is a specific signal, the specific signal Vsg is supplied from the capture signal output terminal 5 to various signal processing circuits (not shown).

FIG. 4 shows an example of the gate signal generation circuit 4, and FIG. 5 is a timing chart of each signal when the signal of the Kth line is fetched from the input video signal Vin.

In FIG. 4, the counter 7 is used to generate the gate signal GT. Reference numeral 8 is an initial value setting circuit for the counter 7, which is loaded into the counter 7. Reference numeral 6 is a circuit for generating a load signal for loading an initial value.

An OR gate 11 is connected to the set terminal SET of the load signal generation circuit 6, and a reset signal RST and an error signal NG are supplied to the OR gate 11.

The reset signal RST is a signal that becomes high level for a short time when the power switch is turned on.

The frame pulse FD is input to the I terminal of the load signal generating circuit 6, and the horizontal pulse HD is input to the clock terminal CLOCK.

When the set terminal SET is low, the output from the O terminal is also low. However, when the set terminal SET is inverted from high to low, the frame pulse FD input immediately after it is inverted to low is counted for one clock. It is output from the O terminal as the load signal LOAD of 7 (see FIG. 5).

The counter 7 is a counter that uses the horizontal pulse HD as a clock, and when the load signal LOAD becomes high, the initial value setting circuit 8
Read more initial values. In this example, the initial value is 4 as shown in FIG. Then, counting is continued from this initial value of 4.

Eventually, if you count up to K-1, Q as shown in Fig. 5
The gate signal GT is output from the (K-1) terminal. Further, the counter 7 continues counting, and when 524 is counted, Q (5
24) Output the reset signal RESET from the terminal. When this reset signal RESET is input from the reset terminal RESET of the counter 7, the count value returns to 0 as shown in FIG. 5, and the counting is repeated from there. That is, this counter 7 operates as a 525-ary counter.

[Problems to be Solved by the Invention] Now, a video signal capturing circuit configured as described above,
In particular, in the configuration of the gate signal generation circuit 4, the vertical sync signal, and hence the frame pulse FD
When the signal is disturbed, the gate signal may not be generated in the line in which the target specific signal is inserted.

Therefore, the ghost and the like become small enough to capture the target signal, and it takes a long time to wait until the vertical synchronizing signal is accurately output.

Therefore, the present invention proposes a video signal capturing circuit that solves such a problem.

[Means for Solving the Problems] In order to solve the above problems, in the present invention,
It is composed of a counter that makes a full count by the number of lines that make up the frame, and a gate signal generating means that counts the horizontal sync signals separated by synchronization and generates a gate signal at a specific line, a counter output obtained at full count, and this. 1
Select one of the counter outputs shifted by the line,
And a reset signal forming means that uses the selected counter output as a reset signal of the counter, and when a target signal is not gated on a specific line,
The reset signal forming means is operated to change the reset signal.

[Operation] When the captured signal is not the intended specific signal, the select circuit 10 is controlled to replace the signal supplied to the terminal A (counter output A) with the signal supplied to the terminal B. (Counter output Y) is used as a reset signal RESET. This signal Y is a signal shifted by one line from the signal A.

As a result, the count operation of the counter 7 is increased or decreased by one count by the new reset signal RESET. As a result, the gate signal GT shifted by one line is generated. This makes it possible to generate the gate signal GT for gating the specific signal of interest.

Example Next, an example of the video signal capturing circuit according to the present invention is applied to the ghost removing device described above.
A detailed description will be given with reference to FIG.

However, the overall configuration of the video signal capturing circuit is the same as that of the conventional example, and therefore its description is omitted.

FIG. 1 is a specific example of the gate signal generating circuit 4 when the Kth line of the input video signal Vin is taken in, and FIG. 2 is a timing chart of various signals in the configuration.

In the present invention, 7 is a gate signal generating means, which is composed of a counter which, like the conventional example, makes a full count in the number of constituent lines of one frame. Therefore, the gate signal generating means is hereinafter referred to as the counter 7.

Further, 20 is a reset signal forming means, which is a counter output of the counter 7 obtained at full count,
This is for selecting any one of the counter outputs shifted by one line and using the selected counter output as the reset signal RESET of the counter 7.

Therefore, the reset signal forming means 20 is composed of the select circuit 10 and the latch circuit 9, and the counter output A and the counter output Y obtained by delaying the counter output A by one line are selected by the select circuit 10, and the selected counter is selected. The output is used as the reset signal RESET.

The error signal NG is supplied to the select circuit 10 as the select signal.

A load signal generation circuit 6 is connected to the counter 7, and a reset signal RST is set to its set terminal SET.
Is supplied.

Other configurations are the same as those in FIG. 4, and therefore detailed description will be omitted.

Now, in the case of such a configuration, since the low level error signal NG is supplied to the select terminal SEL of the select circuit 10 in the normal state, in this case, the counter output A is output from the Y terminal. Has been done.

That is, when the counter 7 counts 524, the select circuit 10 outputs the counter output A from the Q (524) terminal of the counter 7 as the reset signal RESET.

This reset signal RESET is the reset terminal R of the counter 7.
When input from ESET, the count value is 0 as shown in Fig. 2.
Return to and repeat the count from there. That is, this counter 7 operates as a 525-ary counter.

Here, if the horizontal synchronizing signal and therefore the frame pulse FD is disturbed by the influence of a ghost, etc., and the gate signal GT is shifted to the (K-1) th line as shown in FIG. The signal captured by the GT is discriminated as an unintended signal (not a specific signal), and the error signal NG becomes high level.

When the select terminal SEL of the select circuit 10 becomes high level, the counter output Y input to the B terminal is supplied as the reset signal RESET this time as shown in FIG.

Since the counter output Y is a signal delayed by one line from the counter output A, when the counter output Y is used as the reset signal RESET, the count value of the counter 7 returns to 0 after a delay of one clock. It will be. As a result, the counter 7 normally operating in 525
However, in this case, it operates as a 526-ary counter.

Therefore, the gate signal GT is delayed by one line, that is, generated in the Kth line in the next frame in which the capture is incorrect (see FIG. 2). Since the signal fetched by the gate signal GT is the target specific signal, the error signal NG from the fetch discrimination circuit 3 is inverted to the low level. As a result, the output of the select circuit 10 is switched to the input from the A terminal again.

Therefore, the counter 7 becomes a 525-ary counter as before, and the gate signal GT is always generated on the Kth line as it is.

From the above, even when the frame pulse FD is disturbed by a ghost or the like, the gate signal GT is set to 1
The target specific signal can be easily extracted by delaying the line.

In the above description, the count value of the counter 7 is set to 1
Although the case where the count is increased and the gate signal GT is shifted one line backward has been illustrated, the case where the count number is decremented by one line and shifted forward is also applicable.

Further, the case where the gate signal GT of one line is generated in one frame has been illustrated, but the same applies to the case where the gate signals of a plurality of lines are generated in one frame. Further, although the frame pulse FD is used as the load signal LOAD for the counter 7, a vertical synchronizing signal or the like may be used instead.

[Effects of the Invention] As described above, according to the present invention, a target signal (specific signal) is promptly inserted in a line in spite of disturbance of a vertical synchronization signal (or frame pulse) due to a ghost or the like. Corresponding gate signals can be generated.

Therefore, since the target specific signal can be taken in in a short time, the present invention is extremely suitable when applied to the above-described circuit system for extracting the ghost elimination reference signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a gate signal generating circuit used in a video signal capturing circuit according to the present invention, and FIG.
FIG. 3 is a waveform diagram for explaining the operation of generating a gate signal, FIG. 3 is a block diagram of a video signal capturing circuit, FIG. 4 is a block diagram of a gate signal generating circuit used for this, and FIG. It is a waveform diagram to be provided. 3 ... Capture determination circuit 4 ... Gate signal generation circuit 6 ... Load signal generation circuit 7 ... Gate signal generation means (counter) 8 ... Initial value setting circuit 9 ... Latch circuit 10 ... Select circuit 20 ... Reset signal forming means

Claims (1)

(57) [Claims] 1. A gate signal generating means for counting a horizontal synchronizing signal, which is synchronously separated, to generate a gate signal on a specific line, which is constituted by a counter which makes a full count in the number of lines constituting one frame, and is obtained at the time of full counting. A counter output and a reset signal forming means for selecting one of the counter outputs obtained by shifting the counter output by one line and using the selected counter output as a reset signal of the counter, a target signal is output on the specific line. A video signal capturing circuit, wherein the reset signal forming means operates so as to change the reset signal when the gate signal is not gated.