JP2022050236A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide a semiconductor device suppressed in plasma damages.SOLUTION: A semiconductor device comprises: a first conductivity type region of a first conductivity type provided on a front face of a compound semiconductor layer; a second conductivity type region of a second conductivity type provided below the first conductivity type region; a contact region of the second conductivity type provided so as to be extended from the front face to the second conductivity type region; an interlayer insulating film provided above the compound semiconductor layer; a body electrode provided on the contact region; a source electrode connected with the body electrode via a source opening of the interlayer insulating film; and a gate electrode provided above the compound semiconductor layer. An end of the body electrode is embedded in the interlayer insulating film, and provided so as to be closer to the gate electrode than the source electrode in a place direction of the front face.SELECTED DRAWING: Figure 1A

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Conventionally, a semiconductor device including a P-type electrode layer and a body electrode is known (see, for example, Patent Documents 1 to 3).
Patent Document 1 Japanese Patent Application Laid-Open No. 2014-120039 Patent Document 2 Japanese Patent Application Laid-Open No. 2014-120540 Patent Document 3 Japanese Patent Application Laid-Open No. 2015-141979

It is preferable to provide a semiconductor device that suppresses plasma damage.

In the first aspect of the present invention, the first conductive type region provided on the front surface of the compound semiconductor layer and the second conductive type region provided below the first conductive type region. The second conductive type region, the second conductive type contact region extending from the front surface to the second conductive type region, the interlayer insulating film provided above the compound semiconductor layer, and the contact region. The body electrode is provided with a source electrode connected to the body electrode via the source opening of the interlayer insulating film, and a gate electrode provided above the compound semiconductor layer, and the end portion of the body electrode is provided. Provided is a semiconductor device embedded in an interlayer insulating film and provided closer to a gate electrode than a source electrode in the plane direction of the front surface.

The body electrode may be in contact with both the contact region and the interlayer insulating film.

The semiconductor device may include a gate insulating film provided between the gate electrode and the compound semiconductor layer. In the plane direction of the front surface, the horizontal distance from the end of the gate electrode to the nearest body electrode may be equal to or greater than the thickness of the gate insulating film.

The gate electrodes may be repeatedly arranged in a predetermined arrangement direction. In the alignment direction, the width of the body electrodes may be greater than the width of the contact area.

The body electrode may contain at least one of Ni, Pd, TiN, Ti or Al.

The material of the body electrode may be the same as the material of the gate electrode.

The film thickness of the body electrode may be the same as the film thickness of the gate electrode.

The film thickness of the body electrode may be 10 nm or more and 200 nm or less.

The compound semiconductor layer may be GaN.

The interlayer insulating film may be an oxide containing Si.

The semiconductor device may have a planar type structure.

In the second aspect of the present invention, there are a step of forming a gate insulating film above the compound semiconductor layer, a step of forming a body electrode after forming the gate insulating film, and a step of forming an interlayer insulating film after forming the body electrode. Provided is a method for manufacturing a semiconductor device including a step of forming a semiconductor device.

The method for manufacturing a semiconductor device may include a step of forming a gate electrode and a body electrode at the same time.

In the arrangement direction in which the gate electrodes are repeatedly arranged, the width of the body electrode may be larger than the width of the source opening for connecting the source electrode to the body electrode.

The method for manufacturing a semiconductor device may include a step of providing a contact region on the front surface of the compound semiconductor layer. In the arrangement direction in which the gate electrodes are repeatedly arranged, the width of the body electrode may be smaller than the width of the source opening for connecting the source electrode to the body electrode and may be larger than the width of the contact region.

The method for manufacturing a semiconductor device may include a step of providing a contact region on the front surface of the compound semiconductor layer. In the arrangement direction in which the gate electrodes are repeatedly arranged, the width of the body electrodes may be smaller than the width of the contact region.

The outline of the above invention does not list all the features of the present invention. A subcombination of these feature groups can also be an invention.

An example of the configuration of the semiconductor device 100 is shown. An example of the manufacturing method of the semiconductor device 100 according to FIG. 1A is shown. The subsequent steps of the manufacturing method shown in FIG. 1B are shown. An example of the configuration of the semiconductor device 100 is shown. This is a modification of the semiconductor device 100. This is a modification of the semiconductor device 100. This is a modification of the semiconductor device 100. This is a modification of the semiconductor device 100. An example of the manufacturing method of the semiconductor device 100 according to FIG. 5A is shown. An example of the manufacturing method of the semiconductor device 100 is shown. An example of the manufacturing method of the semiconductor device 100 is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

In the present specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "top", "bottom", "front", and "back" are not limited to the direction of gravity or the direction of mounting on a substrate or the like when mounting a semiconductor device.

In the present specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. In the present specification, the plane parallel to the upper surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis.

In each embodiment, an example in which the first conductive type is N-type and the second conductive type is P-type is shown, but the first conductive type may be P-type and the second conductive type may be N-type. In this case, the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities.

FIG. 1A shows an example of the configuration of the semiconductor device 100. The semiconductor device 100 of this example includes a semiconductor substrate 10, a compound semiconductor layer 20, an interlayer insulating film 30, a gate electrode 40, a body electrode 50, a source electrode 60, and a drain electrode 70.

The semiconductor device 100 functions as a field effect transistor (FET). The semiconductor device 100 of this example is a vertical MOSFET and has a planar type DMOS structure.

The semiconductor substrate 10 is a compound semiconductor substrate. The semiconductor substrate 10 may be a nitride semiconductor substrate. The semiconductor substrate 10 of this example is an N-type self-supporting GaN substrate. The semiconductor substrate 10 may be a SiC substrate. The semiconductor substrate 10 may be manufactured by any method such as a vapor phase growth method or a liquid phase growth method. The semiconductor substrate 10 may be obtained by cutting out an epitaxially grown GaN layer. The semiconductor substrate 10 may be omitted.

The compound semiconductor layer 20 is provided on the upper surface of the semiconductor substrate 10. The compound semiconductor layer 20 has a compound semiconductor such as GaN or SiC. The compound semiconductor layer 20 may be manufactured by any method such as a vapor phase growth method or a liquid phase growth method. The compound semiconductor layer 20 of this example is an N-type GaN layer epitaxially grown on the semiconductor substrate 10 by using the MOCVD method. In one example, the dopant concentration of the compound semiconductor layer 20 is 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less, but is not limited thereto. The compound semiconductor layer 20 of this example has a first conductive type region 21, a second conductive type region 22, and a contact region 24.

The first conductive type region 21 is a first conductive type region provided on the front surface 23 of the compound semiconductor layer 20. The first conductive type region 21 of this example is provided in connection with the body electrode 50. Further, the first conductive type region 21 is provided by being electrically connected to the body electrode 50. The first conductive type region 21 is an N + type source region. The first conductive region 21 is formed by doping impurities from the front surface 23. The N-type dopant may be Si or Ge when the compound semiconductor layer 20 is GaN.

The second conductive type region 22 is a second conductive type region provided below the first conductive type region 21. The second conductive type region 22 of this example is a P-type well region. The second conductive type region 22 of this example is provided so as to cover the lower surface and the side surface of the first conductive type region 21. The second conductive region 22 is formed by doping impurities from the front surface 23. The P-type dopant may be Mg when the compound semiconductor layer 20 is GaN. The doping concentration of the second conductive region 22 is 1.0 × 10 ¹⁶ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less.

The contact region 24 is a second conductive type region provided on the front surface 23 of the compound semiconductor layer 20. The contact region 24 is provided so as to extend from the front surface 23 to the second conductive type region 22. The contact regions 24 may be repeatedly arranged at predetermined intervals in the X-axis direction. Further, the contact regions 24 may be repeatedly arranged at predetermined intervals in the Y-axis direction. The contact area 24 of this example is a P + type contact area. The doping concentration of the contact region 24 is higher than the doping concentration of the second conductive type region 22. The doping concentration of the contact region 24 is 5.0 × 10 ¹⁸ cm ^-3 or more and 5.0 × 10 ²⁰ cm ^-3 or less.

The interlayer insulating film 30 is provided above the compound semiconductor layer 20. The interlayer insulating film 30 may be provided with a source opening 62 for connecting the source electrode 60 to the compound semiconductor layer 20. The interlayer insulating film 30 may be an oxide containing Si. The interlayer insulating film 30 may be a laminated film in which a plurality of insulating films are laminated.

The gate electrode 40 is provided above the compound semiconductor layer 20. The gate electrode 40 controls the electrical conductivity of the compound semiconductor layer 20 in response to the application of the gate voltage. For example, the gate electrode 40 is a single layer film of TiN. The gate electrodes 40 may be repeatedly arranged at predetermined intervals in the X-axis direction. In the present specification, the X-axis direction is referred to as an arrangement direction.

The gate insulating film 42 is provided between the gate electrode 40 and the compound semiconductor layer 20. The material of the gate insulating film 42 may be an oxide or an oxynitride. The gate insulating film 42 may contain Si and O, and is, for example, a SiO ₂ film. Further, the gate insulating film 42 may contain at least one B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta or W.

The body electrode 50 is provided on the contact region 24. The body electrode 50 of this example is in contact with both the contact region 24 and the interlayer insulating film 30. The film thickness of the body electrode 50 may be the same as or different from the film thickness of the gate electrode 40. The film thickness of the body electrode 50 in this example is thinner than the film thickness of the gate electrode 40. The film thickness of the body electrode 50 may be 10 nm or more and 200 nm or less. For example, the film thickness of the body electrode 50 is 50 nm.

The material of the body electrode 50 may be the same as or different from that of the gate electrode 40. When the material of the body electrode 50 is the same as that of the gate electrode 40, the body electrode 50 and the gate electrode 40 may be formed at the same time. The body electrode 50 may contain at least one of Ni, Pd, TiN, Ti or Al. The material of the body electrode 50 of this example is Ni.

The source electrode 60 is connected to the body electrode 50 via the source opening 62 of the interlayer insulating film 30. The source electrode 60 may be provided in contact with the first conductive type region 21 in a region where the body electrode 50 is not provided on the front surface 23. The source electrode 60 may be made of the same material as the gate electrode 40, or may be made of a different material. The source electrode 60 of this example is a laminated film of titanium (Ti) and aluminum (Al). The body electrode 50 and the source electrode 60 are set to predetermined source potentials.

The drain electrode 70 is provided on the back surface 11 of the semiconductor substrate 10. The drain electrode 70 may be made of the same material as the source electrode 60, or may be made of a different material. The drain electrode 70 of this example is a laminated film of titanium (Ti) and aluminum (Al).

FIG. 1B shows an example of a method for manufacturing the semiconductor device 100 according to FIG. 1A. In this example, some steps of the manufacturing method of the semiconductor device 100 will be extracted and described. The region below the compound semiconductor layer 20 is omitted.

In step S100, the gate insulating film 42 is formed on the front surface 23 of the compound semiconductor layer 20. Further, a gate electrode 40 patterned in a predetermined shape is formed above the gate insulating film 42. The compound semiconductor layer 20 may be formed with a first conductive type region 21, a second conductive type region 22, and a contact region 24. The gate insulating film 42 of this example is a 100 nm SiO ₂ film formed by a plasma CVD method. In the plasma CVD method, a Si raw material is supplied by silane (SiH ₄ ) or TEOS (tetraethoxysilane), and a gate insulating film 42 is formed by using oxygen plasma or the like. The gate insulating film 42 may be an oxide film formed by heat treatment.

In step S102, the gate insulating film 42 is removed by etching to expose the front surface 23. In this example, the gate insulating film 42 in the region forming the body electrode 50 and the source electrode 60 is removed. The etching of the gate insulating film 42 may be wet etching.

In step S104, the body electrode 50 is formed. As described above, the body electrode 50 of this example is formed after the gate insulating film 42 is formed. By forming the gate insulating film 42 in step S100, it becomes easy to suppress plasma damage of the front surface 23. The body electrode 50 of this example is 50 nm Ni formed by vapor deposition. In step S106, an unnecessary portion of the body electrode 50 is removed.

FIG. 1C shows a subsequent step of the manufacturing method shown in FIG. 1B. In this example, the next step of step S106 of FIG. 1B is shown. The region below the compound semiconductor layer 20 is omitted.

In step S108, the interlayer insulating film 30 is formed above the gate electrode 40, the gate insulating film 42, and the body electrode 50. As described above, the interlayer insulating film 30 of this example is formed after the body electrode 50 is formed. In step S110, the source opening 62 is formed by dry etching of the interlayer insulating film 30. The formation of the source opening 62 exposes the body electrode 50. Since the body electrode 50 functions as an etching stop layer, plasma damage in the contact region 24 can be suppressed.

In step S112, the source electrode 60 is formed. The source electrode 60 is provided in connection with the body electrode 50 at the source opening 62. In the region where the body electrode 50 is not formed, the source electrode 60 may be formed on the front surface 23.

FIG. 1D shows an example of the configuration of the semiconductor device 100. In this example, the same cross section as in FIG. 1A is shown.

The cell pitch P indicates the pitch of the repeating structure in the arrangement direction. For example, the cell pitch P is the distance from the end of the gate electrode 40 on the positive side in the arrangement direction to the end of the adjacent gate electrode 40 on the positive side of the arrangement direction in the arrangement direction. The cell pitch P may be 8.0 μm or less, and may be 5.0 μm or less.

The source opening width Ws is the width of the source opening 62 in the arrangement direction. For example, the source opening width Ws may be 3.0 μm or less, and may be 1.0 μm or less. The source opening width Ws may be 0.5 μm or more. The source opening width Ws of this example is 1.0 μm.

The gate electrode width Wg is the width of the gate electrodes 40 in the arrangement direction. The gate electrode width Wg may be 1.0 μm or more and 5.0 μm or less. For example, the gate electrode width Wg is 3.0 μm.

The body electrode width Wb is the width of the body electrode 50 in the arrangement direction. The contact region width Wc is the width of the contact region 24 in the arrangement direction. The body electrode width Wb may be larger than the source opening width Ws and the contact region width Wc. The body electrode width Wb may be at least twice the contact region width Wc.

The film thickness Dgi is the thickness of the gate insulating film 42 in the depth direction. The film thickness Dgi may be 50 nm or more and 100 nm or less. The film thickness Dgi may be the same as or different from the film thickness of the body electrode 50.

The length Lsg is the distance between the source opening 62 and the gate electrode 40 in the arrangement direction. The length Lsg may be 0.2 μm or more and 1.0 μm or less. For example, the length Lsg is 0.5 μm. By shortening the length Lsg, the semiconductor device 100 can be miniaturized.

The length Lbg is the distance between the body electrode 50 and the gate electrode 40 in the arrangement direction. The length Lbg may be half the length Lsg and may be more than half the length Lsg. The length Lbg may be 0.1 μm or more and 0.5 μm or less. For example, the length Lbg is 0.25 μm. In the plane direction of the front surface 23, the horizontal distance from the end of the gate electrode 40 to the nearest body electrode 50 may be equal to or greater than the thickness of the gate insulating film 42. That is, the length Lbg is equal to or larger than the film thickness Dgi of the gate insulating film 42. As a result, it is possible to suppress a decrease in withstand voltage. Further, by setting the length Lbg to half or more of the length Lsg, it becomes easy to miniaturize while suppressing plasma damage and decrease in withstand voltage.

The end portion of the body electrode 50 is embedded in the interlayer insulating film 30 and is provided closer to the gate electrode 40 than the source electrode 60 in the plane direction of the front surface 23. That is, the length Lsg may be larger than the length Lbg. In this case, since the body electrode 50 is formed before the interlayer insulating film 30 is formed, the body electrode 50 functions as an etch stop layer when the source opening 62 is formed, and suppresses plasma damage in the contact region 24. can do.

The semiconductor device 100 of this example can suppress plasma damage to the contact region 24 and reduce the P-type contact resistance. In particular, when the compound semiconductor layer 20 is GaN, it is likely to be N-typed due to plasma damage, so that the effect of reducing the P-type contact resistance is high. Further, it is possible to reduce the risk of peeling of the body electrode 50 having poor adhesion to an oxide film such as Ni or Pd. The semiconductor device 100 of this example can suppress plasma damage to the contact region 24 without increasing the number of steps.

FIG. 2 is a modification of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1A in that it has a trench structure. In this example, the differences from the embodiment of FIG. 1A will be particularly described.

The first conductive region 21 is provided on the front surface 23 of the compound semiconductor layer 20. A contact region 24 may be provided in a part of the first conductive type region 21. The second conductive type region 22 is provided below the first conductive type region 21. The trench portion is provided so as to penetrate the first conductive type region 21 and the second conductive type region 22 from the front surface 23 side. The trench portion may be provided by extending to the compound semiconductor layer 20.

The gate electrode 40 is provided so as to extend in the depth direction of the compound semiconductor layer 20. The gate electrode 40 of this example has a T-shaped structure in the XZ cross section. The gate insulating film 42 is provided between the gate electrode 40 and the compound semiconductor layer 20 along the inner wall of the trench portion.

The cell pitch P of the trench structure may be 8.0 μm or less, and may be 5.0 μm or less. The cell pitch P of the trench structure can be made smaller than the cell pitch P of the planar structure. The cell pitch P of this example is 3.0 μm. The gate electrode width Wg of this example is 1.0 μm. The gate electrode width Wg of the trench structure can be made smaller than the gate electrode width Wg of the planar structure.

The length Lsg of the trench structure may be 0.2 μm or more and 1.0 μm or less, similarly to the length Lsg of the planar structure. The length Lbg of the trench structure may be 0.1 μm or more and 0.5 μm or less, similarly to the length Lbg of the planar structure.

In the semiconductor device 100 of this example, even in the trench structure, the end portion of the body electrode 50 is embedded in the interlayer insulating film 30, and the semiconductor device 100 is closer to the gate electrode 40 than the source electrode 60 in the plane direction of the front surface 23. It is provided. That is, since the body electrode 50 is formed before the interlayer insulating film 30 is formed, the body electrode 50 functions as an etch stop layer when the source opening 62 is formed, and suppresses plasma damage in the contact region 24. be able to.

FIG. 3 is a modification of the semiconductor device 100. The semiconductor device 100 of this example has a structure of a body electrode 50 different from that of the embodiment of FIG. 1D. In this example, the differences from the embodiment of FIG. 1D will be particularly described.

The body electrode width Wb of this example is smaller than the source opening width Ws. That is, the end portion of the body electrode 50 is not embedded in the interlayer insulating film 30. However, the body electrode 50 may be formed before the interlayer insulating film 30 is formed. The body electrode width Wb is larger than the contact region width Wc. As a result, plasma damage in the contact region 24 can be suppressed. The body electrode width Wb may be the same as the contact region width Wc.

The other structures may be the same as those in the embodiment of FIG. 1D. For example, the cell pitch P, the source opening width Ws, the gate electrode width Wg, and the film thickness Dgi are the same as those in the embodiment of FIG. 1D.

FIG. 4 is a modification of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 3 in that it has a trench structure. The body electrode width Wb of this example is smaller than the source opening width Ws, and the end portion of the body electrode 50 is not embedded in the interlayer insulating film 30. The body electrode 50 may be formed before the interlayer insulating film 30 is formed. Since the body electrode width Wb is larger than the contact region width Wc, plasma damage in the contact region 24 can be suppressed. In the semiconductor device 100 of this example, since the gate electrode width Wg can be made smaller than the gate electrode width Wg of the planar structure, the cell pitch P can be made smaller than the cell pitch P of the planar structure. As a result, the semiconductor device 100 can be miniaturized.

FIG. 5A is a modification of the semiconductor device 100. The semiconductor device 100 of this example has a structure of a body electrode 50 different from that of the embodiments of FIGS. 1D and 3. In this example, the differences from the examples of FIGS. 1D and 3 will be particularly described.

The width of the body electrode 50 is smaller than the width of the contact region 24 in the arrangement direction in which the gate electrodes 40 are repeatedly arranged. That is, the end portion of the body electrode 50 is provided so as to be separated from the gate electrode 40 by the contact region 24 in the surface direction of the front surface 23. Also in this example, plasma damage in the contact region 24 below the body electrode 50 can be suppressed, so that high resistance of the contact can be prevented. Although the semiconductor device 100 of this example has a planar structure, it may have a trench structure.

FIG. 5B shows an example of a method for manufacturing the semiconductor device 100 according to FIG. 5A. In this example, some steps of the manufacturing method of the semiconductor device 100 will be extracted and described. The manufacturing method of this example shows a case where the end portion of the body electrode 50 is not embedded in the interlayer insulating film 30.

In step S200, a gate insulating film 42 is formed on the front surface 23 of the compound semiconductor layer 20, and a part of the gate insulating film 42 is removed by etching. The compound semiconductor layer 20 may be formed with a first conductive type region 21, a second conductive type region 22, and a contact region 24. In this example, the gate insulating film 42 in the region forming the body electrode 50 and the source electrode 60 is removed. On the front surface 23, the first conductive type region 21 and the contact region 24 are exposed. The etching of the gate insulating film 42 may be wet etching.

In step S202, a gate electrode 40 patterned in a predetermined shape is formed above the gate insulating film 42. The gate electrode 40 may be formed by an etching process or a lift-off process.

In step S204, the body electrode 50 is formed on the contact region 24. As described above, the body electrode 50 of this example is formed after the gate insulating film 42 is formed. By forming the gate insulating film 42 in step S200, it becomes easy to suppress plasma damage of the front surface 23. Further, the body electrode 50 is formed so that the width of the body electrode 50 is smaller than the width of the contact region 24 in the arrangement direction.

FIG. 5C shows an example of a manufacturing method of the semiconductor device 100. In this example, the continuation process of FIG. 5B is shown. The region below the compound semiconductor layer 20 is omitted.

In step S206, the interlayer insulating film 30 is formed above the gate electrode 40, the gate insulating film 42, and the body electrode 50. As described above, the interlayer insulating film 30 of this example is formed after the body electrode 50 is formed. In step S208, the source opening 62 is formed by dry etching of the interlayer insulating film 30. The formation of the source opening 62 exposes the body electrode 50 and the front surface 23. Since the body electrode 50 functions as an etching stop layer, plasma damage in the contact region 24 below the body electrode 50 can be suppressed.

In step S210, the source electrode 60 is formed. The source electrode 60 is provided in connection with the body electrode 50 at the source opening 62. In the region where the body electrode 50 is not formed, the source electrode 60 may be formed on the front surface 23. The source electrode 60 of this example is provided apart from the gate insulating film 42.

FIG. 6 shows an example of a manufacturing method of the semiconductor device 100. In this example, the manufacturing method of the body electrode 50 is different from that in FIG. 5B. Although the semiconductor device 100 having a planar structure will be described, the same may be applied to the semiconductor device 100 having a trench structure.

Step S300 corresponds to step S200. In step S302, the gate electrode 40 and the body electrode 50 are formed at the same time. By forming the gate electrode 40 and the body electrode 50 in the same process, the manufacturing process can be simplified. The material of the gate electrode 40 is the same as the material of the body electrode 50. The film thickness of the gate electrode 40 may be the same as the film thickness of the body electrode 50.

In step S304, the gate electrode 40 and the body electrode 50 patterned in a predetermined shape are formed. The gate electrode 40 and the body electrode 50 of this example have a predetermined shape by dry etching. In the step following step S304, the interlayer insulating film 30 and the source electrode 60 may be formed by the same steps as in steps S206 to S210 of FIG. 5C.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 ... semiconductor substrate, 11 ... back surface, 20 ... compound semiconductor layer, 21 ... first conductive type region, 22 ... second conductive type region, 23 ... front surface, 24 ... contact region, 30 ... interlayer insulating film, 40 ... gate electrode, 42 ... gate insulating film, 50 ... body electrode, 60 ... source electrode, 62 ... source opening , 70 ... Drain electrode, 100 ... Semiconductor device

Claims (16)

The first conductive type region of the first conductive type provided on the front surface of the compound semiconductor layer, and
The second conductive type region of the second conductive type provided below the first conductive type region and the second conductive type region.
A second conductive type contact region extending from the front surface to the second conductive type region, and a contact region of the second conductive type.
An interlayer insulating film provided above the compound semiconductor layer and
With the body electrode provided on the contact area,
With the source electrode connected to the body electrode through the source opening of the interlayer insulating film,
A gate electrode provided above the compound semiconductor layer and
Equipped with
A semiconductor device in which the end portion of the body electrode is embedded in the interlayer insulating film and is provided closer to the gate electrode than the source electrode in the plane direction of the front surface. The semiconductor device according to claim 1, wherein the body electrode is in contact with both the contact region and the interlayer insulating film. A gate insulating film provided between the gate electrode and the compound semiconductor layer is provided.
The semiconductor device according to claim 1 or 2, wherein the horizontal distance from the end of the gate electrode to the nearest body electrode in the plane direction of the front surface is equal to or larger than the thickness of the gate insulating film. The gate electrodes are repeatedly arranged in a predetermined arrangement direction, and the gate electrodes are repeatedly arranged.
The semiconductor device according to any one of claims 1 to 3, wherein the width of the body electrode is larger than the width of the contact region in the arrangement direction. The semiconductor device according to any one of claims 1 to 4, wherein the body electrode contains at least one of Ni, Pd, TiN, Ti or Al. The semiconductor device according to any one of claims 1 to 5, wherein the material of the body electrode is the same as the material of the gate electrode. The semiconductor device according to any one of claims 1 to 6, wherein the film thickness of the body electrode is the same as the film thickness of the gate electrode. The semiconductor device according to any one of claims 1 to 7, wherein the film thickness of the body electrode is 10 nm or more and 200 nm or less. The semiconductor device according to any one of claims 1 to 8, wherein the compound semiconductor layer is GaN. The semiconductor device according to any one of claims 1 to 9, wherein the interlayer insulating film is an oxide containing Si. The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device has a planar type structure. The stage of forming a gate insulating film above the compound semiconductor layer,
After forming the gate insulating film, the stage of forming the body electrode and
A method for manufacturing a semiconductor device including a step of forming an interlayer insulating film after forming the body electrode. The method for manufacturing a semiconductor device according to claim 12, further comprising a step of forming a gate electrode and the body electrode at the same time. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein the width of the body electrode is larger than the source opening width for connecting the source electrode to the body electrode in the arrangement direction in which the gate electrodes are repeatedly arranged. A step of providing a contact region on the front surface of the compound semiconductor layer is provided.
13. The method for manufacturing a semiconductor device according to the description. A step of providing a contact region on the front surface of the compound semiconductor layer is provided.
The method for manufacturing a semiconductor device according to claim 12, wherein the width of the body electrode is smaller than the width of the contact region in the arrangement direction in which the gate electrodes are repeatedly arranged.

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