JP2017045813A - Wiring board - Google Patents

Abstract

To provide a wiring board capable of easily detecting the presence or absence of an electrical short circuit between a dummy pattern and a wiring conductor.
An insulating substrate in which a plurality of insulating layers 1a to 1d are stacked, a wiring conductor 2 deposited between the surface of the insulating substrate 1 and the insulating layers 1a to 1d, and an insulating layer 1a of the insulating substrate 1. ˜1d, a dummy pattern 7 that is not electrically connected to the wiring conductor 2, and a conductor pattern 6 that is attached to the surface of the insulating substrate 1 and is electrically connected to the dummy pattern 7. A wiring board 10 comprising:
[Selection] Figure 1

Description

  The present invention relates to a wiring board used for mounting a semiconductor element.

  An example of a conventional wiring substrate used for mounting a semiconductor element is shown in FIG. The conventional wiring board 20 mainly includes an insulating substrate 11 and a wiring conductor 12.

  In this example, the insulating substrate 11 is formed of four insulating layers 11a to 11d. The insulating layers 11a to 11d are stacked and integrated one above the other. A plurality of via holes 13 are formed in each of the insulating layers 11a to 11d.

  The wiring conductor 12 is formed by, for example, five conductor layers 12a to 12e. The conductor layers 12 a to 12 e are attached to the surfaces of the insulating layers 11 a to 11 d and the via holes 13.

  A central portion of the upper surface of the wiring board 20 is a mounting portion 20A on which the semiconductor element S is mounted. A plurality of semiconductor element connection pads 14 are formed on the mounting portion 20A. The semiconductor element connection pad 14 is formed of a conductor layer 12a. The electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 14.

  The lower surface of the wiring board 20 is a connection surface with the outside. A plurality of external connection pads 15 are formed on the lower surface of the wiring board 20. The external connection pad 15 is formed by the conductor layer 12e. The external connection pad 15 is connected to an electric circuit board (not shown).

  The semiconductor element connection pads 14 and the external connection pads 15 are electrically connected to each other through conductor layers 12a to 12e. The wiring board 20 is mounted on the electric circuit board by connecting the electrode terminal T of the semiconductor element S to the semiconductor element connection pad 14 and connecting the external connection pad 15 to the electric circuit board. Become.

  In this wiring board 20, when the electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 14, an automatic machine equipped with an image recognition device is used to connect the semiconductor element connection pad 14 and the electrode terminal T of the semiconductor element S. Is aligned. Therefore, a plurality of recognition marks 16 are formed in the vicinity of the mounting portion 20A. The recognition mark 16 is recognized by the image recognition device, and alignment is performed based on the recognition data.

  Further, in this wiring board 20, for example, a dummy pattern 17 may be provided in the conductor layer 12b for the purpose of reducing warpage or thickness variation. The dummy pattern 17 is disposed, for example, adjacent to the signal wiring conductor 12 and is not electrically connected to the pattern of the wiring conductor 12.

  By the way, in this wiring board 20, an electrical test is performed to check whether or not predetermined ones of the semiconductor element connection pads 14 and the external connection pads 15 are electrically connected normally. The electrical test is performed by connecting the test probe of the electrical inspection apparatus to each semiconductor element connection pad 14 and each external connection pad 15 and measuring the electrical resistance between the pads. If the pads are to be electrically connected to each other, the electrical resistance between them is several tens of ohms or less. If the pads are to be electrically insulated from each other, the electrical resistance between them is several hundreds. MΩ or more.

  However, in the conventional wiring board 20, the dummy pattern 17 is not electrically connected to the wiring conductor 12. Therefore, for example, even if an electrical short circuit occurs between the dummy pattern 17 and the signal wiring conductor 12 adjacent thereto, the short circuit cannot be detected. If the signal wiring conductor 12 and the dummy pattern 17 are electrically short-circuited, the signal may not be transmitted satisfactorily to the signal wiring conductor 12.

JP 2004-31828 A

  An object of the present invention is to provide a wiring board that can easily detect the presence or absence of an electrical short circuit between a dummy pattern and a wiring conductor.

  The wiring board of the present invention is an insulating substrate formed by laminating a plurality of insulating layers, a wiring conductor applied between the surface of the insulating substrate and the insulating layer, and an insulating substrate attached to the insulating layer of the insulating substrate. And a dummy pattern electrically unconnected to the wiring conductor and a conductor pattern that is attached to the surface of the insulating substrate and electrically connected to the dummy pattern. It is.

  According to the wiring board of the present invention, since the conductive pattern electrically connected to the dummy pattern is provided on the surface of the insulating substrate, the electrical resistance between the conductive pattern and the wiring conductor on the surface of the insulating substrate is measured. Thus, it is possible to easily detect the presence or absence of an electrical short circuit between the dummy pattern and the wiring conductor.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view showing an example of an embodiment of a wiring board according to the present invention. FIG. 3 is a schematic top view of a conductor layer including a dummy pattern in an example of an embodiment of a wiring board according to the present invention. FIG. 4 is a schematic cross-sectional view showing a conventional wiring board.

  Next, an example of an embodiment of a wiring board according to the present invention will be described with reference to FIGS. As shown in FIG. 1, the wiring board 10 of this example mainly includes an insulating substrate 1 and a wiring conductor 2.

  In this example, the insulating substrate 1 is formed by four insulating layers 1a to 1d. The insulating layers 1a to 1d are stacked and integrated one above the other. The thickness of each insulating layer 1a-1d is about 20-200 micrometers. A plurality of via holes 3 are formed in each of the insulating layers 1a to 1d. The diameter of the via hole 3 is about 20 to 200 μm. The insulating layers 1a to 1d are made of an electrically insulating material obtained by impregnating a heat-resistant substrate made of, for example, glass cloth with a thermosetting resin. Or it consists of a thermosetting resin sheet without a heat resistant base material. As the thermosetting resin, epoxy resin, bismaleimide triazine resin, allyl-modified polyphenylene ether resin, or the like is used.

  The wiring conductor 2 is formed of, for example, five conductor layers 2a to 2e. The conductor layers 2 a to 2 e are attached to the surfaces of the insulating layers 1 a to 1 d and the via holes 3. The thickness of the conductor layers 2a-2e is about 5-25 micrometers in the surface of the insulating layers 1a-1d. The conductor layers 2a to 2b are made of, for example, a copper plating layer or a copper foil.

  A central portion of the upper surface of the wiring board 10 is a mounting portion 10A on which the semiconductor element S is mounted. A plurality of semiconductor element connection pads 4 are formed on the mounting portion 10A. The semiconductor element connection pad 4 is formed by the conductor layer 2a. The semiconductor element connection pad 4 has a circular shape with a diameter of about 50 to 150 μm. The electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 4.

  The lower surface of the wiring board 10 is a connection surface with the outside. A plurality of external connection pads 5 are formed on the lower surface of the wiring board 10. The external connection pad 5 is formed by the conductor layer 2e. The external connection pad 5 has a circular shape with a diameter of about 200 to 600 μm. The external connection pad 5 is connected to an electric circuit board (not shown).

  The semiconductor element connection pads 4 and the external connection pads 5 are electrically connected to each other through conductor layers 2a to 2e. The wiring board 10 is mounted on the electric circuit board by connecting the electrode terminal T of the semiconductor element S to the semiconductor element connection pad 4 and connecting the external connection pad 5 to the electric circuit board. Become.

  In this wiring board 10, when the electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 4, the automatic connection device equipped with the image recognition device is used to connect the semiconductor element connection pad 4 and the electrode terminal T of the semiconductor element S. Is aligned. Therefore, a plurality of recognition marks 6 are formed in the vicinity of the mounting portion 10A. Here, a top view of the wiring board 10 is shown in FIG. For example, four recognition marks 6 are formed at positions corresponding to the centers of the outer peripheral sides of the mounting portion 10A. The recognition mark 6 is formed by a conductor pattern that is electrically independent from the wiring conductor 2. The recognition mark 6 has a circular shape or a rectangular shape, for example. The recognition mark 6 is recognized by the image recognition device, and alignment is performed based on the recognition data. The size of the recognition mark 6 is about 100 to 1000 μm in length and width. Note that the recognition mark 6 may be formed at a position corresponding to each outer corner of the mounting portion 10A. The recognition mark 6 may have another shape such as a triangular shape or a cross shape. Further, two, three, or five or more recognition marks 6 may be provided.

  Further, as shown in FIG. 1, in this wiring board 10, for example, a dummy pattern 7 is provided in the conductor layer 2b for the purpose of reducing warpage and thickness variation. Here, the top view of the conductor layer 2b provided with the dummy pattern 7 is shown in FIG. The dummy pattern 7 is provided in a portion where the pattern of the wiring conductor 2 is not formed. Thereby, the deviation of the distribution of the conductor pattern in the conductor layer 2b is reduced. Thereby, the curvature of wiring board 10 and thickness variation can be reduced.

  The dummy pattern 7 is disposed adjacent to the signal wiring conductor 2 and is not connected to any wiring conductor 2. However, as shown in FIG. 1, in the wiring board 10 of this example, each dummy pattern 7 is electrically connected to the recognition mark 6 on the upper surface of the wiring board 10 via the via hole 3D.

  Also in the wiring board 10 of this example, an electrical test is performed to check whether or not predetermined ones of the semiconductor element connection pads 4 and the external connection pads 5 are electrically connected normally. At this time, in addition to connecting the test probe of the electrical inspection device to each semiconductor element connection pad 4 and each external connection pad 5, it is also connected to each recognition mark 6. Then, by measuring the electrical resistance between each recognition mark 6 and each semiconductor element connection pad 4 and external connection pad 5, it is possible to easily check whether there is an electrical short circuit between the dummy pattern 7 and the wiring conductor 2. It becomes possible to detect. Therefore, according to the present invention, it is possible to provide a wiring board capable of easily detecting the presence or absence of an electrical short between the dummy pattern and the wiring conductor.

  In addition, this invention is not limited to an example of the above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the above-described embodiment, the dummy pattern 7 is electrically connected to the recognition mark 6 on the upper surface of the wiring board 10, but the electrical test conductor that is electrically independent of the wiring conductor 2 on the surface of the wiring board 10. A pattern may be provided separately from the recognition mark 6 and the electrical test conductor pattern and the dummy pattern 7 may be electrically connected.

1 .... Insulating substrate 1a-1d ... Insulating layer 2 .... Wiring conductor 6 .... Conductor pattern (recognition mark)
7. Dummy pattern

Claims (2)

  An insulating substrate formed by laminating a plurality of insulating layers, a wiring conductor deposited between the surface of the insulating substrate and the insulating layer, and an insulating substrate deposited between the insulating layers of the insulating substrate; A wiring board comprising: a non-connected dummy pattern; and a conductor pattern that is attached to the surface of the insulating substrate and is electrically connected to the dummy pattern.   The wiring board according to claim 1, wherein the conductor pattern is a recognition mark.

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