JP2016051759A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves a shorter interconnection, smaller parasitic resistance and a shorter switching time.SOLUTION: In a semiconductor device, a gate electrode 5 forms a via 3 in an insulation film 2 just above a region opposite to an electron supply layer 8 and an electron transit layer 9 via a gate oxide film 6, and the gate electrode 5 is pulled out to a chip surface by the most direct way and parasitic resistance is reduced further compared with the case of pulling out the electrode from an end of the gate electrode 5. This shortens a switching time. When assuming that a width of a via hole is a and a width of the region where the gate electrode faces the semiconductor via the gate film is b, it is preferable that a relation of b≥a is satisfied and b/a has a structure indicating a relation of 250≥b/a≥1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a high electron mobility transistor HEMT having an increased switching speed.

In a HEMT having a structure in which a via is formed in an insulating film and a gate electrode is extracted from the chip surface, it is difficult to increase the switching speed due to a problem of parasitic resistance caused by wiring layout, a problem of input capacitance, and the like.

JP 2013-2111548 A

The prior literature shows a layout for electrically coupling transistors through via holes, but does not show connection methods that can improve the characteristics of the transistors. It was difficult to do. The present invention solves the above problems, and provides a HEMT having a low switching resistance and a low parasitic resistance and input capacitance.

When the gate electrode of the EMT is taken out to the chip surface, a via hole is formed immediately above the gate electrode (just above the region where the gate electrode faces the semiconductor via the gate film), and the gate electrode is taken out therefrom.

  According to the present invention, a via is formed immediately above the gate electrode (immediately above the region where the gate electrode is opposed to the semiconductor via the gate film), and the electrode is taken out from the chip surface to the end of the gate electrode. Since the wiring can be made shorter than when the electrode is taken out from, the parasitic resistance can be reduced and the switching time can be shortened.

It is the gate electrode cross-section of HEMT of this invention. It is a gate electrode cross-sectional structure of a conventional HEMT. This is the relationship between the HEMT in which a via is formed immediately above the gate electrode and the electrode is taken out, and the parasitic resistance and chip size of the HEMT in which the electrode is taken out from the end of the gate electrode.

Hereinafter, the structure which becomes embodiment of this invention is demonstrated.

FIG. 1 is a cross-sectional view of the gate electrode portion of the HEMT according to the first embodiment. In the HEMT of the present invention, the electron transit layer 9 and the electron supply layer 8 made of a nitride compound semiconductor are used.
The structure has a gate electrode 5 and an electrode 4 on the gate electrode 5 on the top, and an insulating film thereon. A via hole 3 is formed immediately above the portion where the gate electrode 5 faces the electron supply layer 8 via the gate oxide film, and the extraction electrode 1 and the gate electrode are coupled via the via hole.

The gate electrode preferably has a three-layer structure of NiO / W / TiN or NiO / Ni / TiN, and the lead electrode preferably has a three-layer structure of Ti / AlCu / TiN in order to maintain good characteristics.

When the width of the via hole is a and the width of the region where the gate electrode faces the semiconductor through the gate film is b, the relationship of b ≧ a is established, and the relationship of b ≧ a is 250 ≧ b / a ≧ 1 It is preferable that it is a structure which shows. Within this range, it is possible to form a junction that can lower the parasitic resistance in terms of process and structure.

FIG. 3 shows the relationship between the chip size and the HEMT in which a via is formed immediately above the gate electrode and the electrode is taken out, and the HEMT in which a via is formed on the edge of the gate electrode and the electrode is taken out. HEMTs with a structure in which a via is formed immediately above the gate electrode and the electrode is taken out have little change in gate parasitic resistance even when the chip size is large. It turns out that it is advantageous.

DESCRIPTION OF SYMBOLS 1, Lead electrode 2, Insulating film 3, Via hole 4, Electrode 5, Gate electrode 6, Gate oxide film 7, Oxide film 8, Electron supply layer 9, Electron travel layer 10, Two-dimensional electron gas

Claims (3)

  High electron, characterized in that the gate electrode forms a via in the insulating film directly above the region facing the semiconductor through the gate oxide film, and then the gate electrode is taken out from the chip surface at the shortest distance and connected to the wiring on the chip surface Mobility transistor HEMT. 2. The semiconductor device according to claim 1, wherein the semiconductor region is made of a nitride compound semiconductor.
When the width of the via is a and the width of the region where the gate electrode faces the semiconductor through the gate film is b, the relation of b ≧ a is established, and the relation of b / a is 250 ≧ b / a ≧ 1 The semiconductor device according to claim 1, wherein the semiconductor device has a structure as shown in FIG.

Images