JP2010171063A - Method of manufacturing semiconductor wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide Cu-based wiring which exhibits high performance (low electric resistivity) and high reliability (high EM resistance) for a semiconductor device such as an Si semiconductor device represented by, for example, a ULSI (ultra large-scale integrated circuit). <P>SOLUTION: In a method of manufacturing the Cu-based wiring of a semiconductor device formed by embedding a Cu-Ti alloy directly in a recessed part provided to an insulating film on a semiconductor substrate, the Cu-Ti alloy contains 0.5 to 3.0 atom% of Ti, and is formed by a sputtering method and heated under heating conditions when or after being buried in the recessed part. Here, the heating is carried out under the conditions of 350 to 600°C in heating temperature, 10 to 120 min in heating time, ≥10 °C/min. in temperature rising speed from room temperature to the heating temperature, and 1×10<SP>-7</SP>to 1×10<SP>-4</SP>atm in oxygen partial pressure in a heating atmosphere. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wiring, and more specifically, for example, in a semiconductor device such as a Si semiconductor device represented by ULSI (ultra-large scale integrated circuit) and the like, high performance (low electrical resistivity) and high The present invention relates to a method for manufacturing a semiconductor wiring (Cu-based wiring) exhibiting reliability (high EM resistance).

  In recent years, design rules have been steadily reduced to meet the demands for high integration of LSIs (Large Scale Integrated Circuits) and high-speed signal propagation, reducing the wiring pitch, the wiring width, and the distance between wirings. Has been done. Further, in order to cope with the high integration of semiconductor devices, it has been studied to make the wiring into a multilayer structure.

  With the miniaturization and high integration of wiring circuits, the electrical resistance of the wiring itself (hereinafter sometimes referred to as wiring resistance) has become a problem. This is because an increase in wiring resistance causes a delay in signal transmission. Therefore, as a wiring material capable of reducing the wiring resistance, a Cu-based wiring material (hereinafter sometimes referred to as a Cu-based wiring material) is used instead of the conventional Al-based wiring material to form a Cu-based wiring. Has been tried.

  A damascene wiring technique is known as a method of forming a Cu-based wiring having a multilayer structure. In this technique, wiring grooves and interlayer connection holes (via / trench) (hereinafter, these may be collectively referred to as a recess) are formed in an insulating film provided on a semiconductor substrate, and the surface of the recess is made of pure Cu or Cu. Cover with Cu-based wiring material (thin film) such as alloy, and heat and pressurize the Cu-based wiring material to flow and embed it in the recess. Then, for example, by chemical mechanical polishing (CMP) method In this method, polishing is performed to remove unnecessary portion of the wiring material deposited on the portion other than the concave portion, and the Cu-based wiring is formed while leaving the wiring material only in the concave portion. In recent years, as the degree of integration increases, the aspect ratio (depth / hole diameter ratio) of the recesses tends to be higher.

  When a Cu-based wiring material is used, if the Cu-based wiring material and the insulating film are brought into direct contact, Cu diffuses into the insulating film and degrades the insulating properties of the insulating film. Such a problematic phenomenon is called electromigration (EM). Therefore, in order to prevent Cu from diffusing into the insulating film and to ensure the resistance to the EM, a barrier layer is provided between the Cu-based wiring and the insulating film. That is, in a general damascene wiring formation process, a barrier layer (TaN thin film or the like) is formed before the Cu-based wiring is formed in the recess formed in the insulating film.

  Since this barrier layer is required to exhibit a barrier property even when heated to a high temperature of about 500 to 700 ° C. so as to embed a Cu-based wiring material in the recess, a metal nitride film such as a TaN film or a TiN film is required. Is used. However, since such a metal nitride film has a higher electrical resistivity than the metal film, there is a problem that the electrical resistivity of the Cu-based wiring is effectively increased.

  In order to reduce the electrical resistivity of the Cu-based wiring, it is necessary to form the barrier layer as thin and uniform as possible. However, in the current film formation method (sputtering method), the barrier layer is formed thin and uniform. It is difficult. Although it is necessary to make the thickness of the barrier layer as thin as possible from the viewpoint of reducing the electrical resistivity, there is a problem that the barrier property cannot be sufficiently secured in the portion if the barrier layer is too thin as a whole or locally. In recent years, the width of wiring grooves and the diameter of connection holes have become smaller, and the depth / width ratio of wiring grooves and the depth / diameter ratio of connection holes have become larger. Is getting harder.

  Therefore, the present applicant forms a Cu alloy wiring directly in the concave portion without using a barrier layer (TaN thin film or the like), and heat-treats to make the barrier layer autonomous at the interface between the insulating film and the Cu alloy wiring ( We have proposed a damascene wiring formation technique that is formed in a self-aligning manner. For example, in Patent Document 1, a Cu alloy thin film containing 0.5 to 10 atomic% of Ti is formed in a concave portion of an insulating film with a thickness of 10 to 50 nm along the concave shape, and then purely formed in the concave portion with a Cu alloy thin film. It is proposed that a Cu thin film is formed and heated to 350 ° C. or higher to precipitate Ti between the insulating film and the Cu alloy thin film. As described above, a Cu alloy containing Ti having a small solid solubility limit with respect to Cu is formed along the recess, and by heating this, Cu and Ti are separated into two phases, and Ti is formed at the interface between the Cu-based wiring and the insulating film. The Ti concentrated layer is formed by abnormal diffusion. Since this Ti concentrated layer acts as a barrier layer, the effective electrical resistance can be reduced as compared with the conventional damascene Cu-based wiring.

JP 2008-021807 A

  By the way, a Cu-based wiring of a semiconductor device is required to have a more reliable and sufficiently reduced wiring resistance. However, under the heat treatment conditions described in Patent Document 1 and the like, the wiring resistance can be reduced, but more reliably and more reliably. It seems that further study is necessary to sufficiently reduce it. The present invention has been made in view of such circumstances, and the object thereof is to make the heat treatment conditions of the wiring appropriate when manufacturing a Cu-based wiring of a semiconductor device (Si semiconductor device, etc.). , Making full use of the self-barrier forming ability of Cu-Ti alloy, effectively reducing the wiring resistance of Cu-based wiring (especially Cu-Ti alloy wiring), high reliability and low electrical resistivity The present invention provides a method for manufacturing a secured semiconductor wiring (Cu-based wiring).

A method for manufacturing a semiconductor wiring according to the present invention is a method for manufacturing a semiconductor wiring in which a Cu-Ti alloy is directly embedded in a recess provided in an insulating film on a semiconductor substrate,
The Cu-Ti alloy contains 0.5 atomic% to 3.0 atomic% of Ti, and
It is characterized in that it includes a step of heating the Cu-Ti alloy under the following heating conditions after forming the Cu-Ti alloy by a sputtering method and after or after embedding the Cu-Ti alloy in the recess.
(Heating conditions)
Heating temperature: 350-600 ° C
Heating time: 10 to 120 min.
Temperature increase rate from room temperature to the above heating temperature: 10 ° C./min. Or more Oxygen partial pressure in a heating atmosphere: 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm

Another method of manufacturing a semiconductor wiring according to the present invention includes forming a layer made of a Cu—Ti alloy along a recess provided in an insulating film on a semiconductor substrate, and then attaching the layer made of the Cu—Ti alloy. A method of manufacturing a semiconductor wiring in which pure Cu is embedded in a recess,
The Cu-Ti alloy contains 0.5 atomic% to 3.0 atomic% of Ti, and
It is characterized in that it includes a step of forming the Cu—Ti alloy layer by a sputtering method and a step of heating the Cu—Ti alloy layer under the above heating conditions.

  According to the present invention, the wiring resistance of a Cu—Ti alloy that is in direct contact with a recess provided in an insulating film on a semiconductor substrate can be reliably and sufficiently lowered, and thus, for example, ULSI (ultra-large scale integrated circuit) or the like is representative. In a semiconductor device such as a Si semiconductor device, a semiconductor wiring (Cu-based wiring) exhibiting high performance (low electrical resistivity) and high reliability (high EM resistance) can be realized.

4 is a graph showing the relationship between the partial pressure of oxygen during heat treatment (heating temperature during heat treatment: 400 ° C.) and the electrical resistivity of a sample in Example 1. It is the graph which showed the relationship between the oxygen partial pressure at the time of the heat processing in Example 2 (heating temperature at the time of heat processing: 500 degreeC), and the electrical resistivity of a sample. It is the graph which showed the relationship between the oxygen partial pressure at the time of the heat processing in Example 3 (heating temperature at the time of heat processing: 600 degreeC), and the electrical resistivity of a sample. It is the graph which showed the relationship between the oxygen partial pressure at the time of heat processing in Example 4, and the electrical resistivity of a sample according to the kind of insulating film. It is the graph which showed the relationship between the heating temperature at the time of the heat processing in Example 5, and the electrical resistivity of a sample. It is the graph which showed the relationship between the heating time at the time of the heat processing in Example 6, and the electrical resistivity of a sample.

  The present inventors manufacture a Cu-based wiring (semiconductor wiring) with reduced electrical resistivity without separately forming a barrier layer at the interface between the insulating film and the Cu-based wiring (particularly, Cu—Ti alloy). In order to establish a method to do so, we have intensively studied. As a result, if the wiring portion that is in direct contact with the insulating film in the recess formed in the insulating film is made of a specific Cu-Ti alloy and the Cu-Ti alloy is heated under specific conditions, the above insulation is achieved. A self-barrier layer (a layer that concentrates at the interface between the insulating film and the Cu-based wiring and forms TiC at the interface to exhibit barrier properties) can be reliably formed at the interface between the film and the Cu-Ti alloy. It has been found that a Cu-based wiring having a reliable and sufficiently reduced wiring resistance (electrical resistance) can be obtained. Hereinafter, the present invention will be described in detail.

  First, in the present invention, a Cu—Ti alloy containing 0.5 to 3.0 atomic% of Ti is used in a wiring portion at least in direct contact with the insulating film in the recess formed in the insulating film. Ti is an element necessary for constituting the self-barrier layer, and 0.5 atomic% or more is necessary. However, when the amount of Ti becomes excessive, Ti that has not been segregated at the interface with the insulating film remains in a solid solution state in the wiring, or forms an intermetallic compound (Ti precipitate) with Cu. Such solute Ti and Ti precipitates increase the electrical resistivity of the Cu-based wiring. Accordingly, the Ti content is 3.0 atomic% or less.

  The remaining composition of the Cu—Ti alloy is Cu and inevitable impurities, but may contain, for example, Ag, Mg, Si, or the like.

As a form of Cu-based wiring in which a Cu-Ti alloy having the above composition is formed in a wiring portion that is at least in direct contact with the insulating film in a recess formed in the insulating film,
(1) Cu-based wiring in which a Cu-Ti alloy having the above composition is directly embedded in a recess provided in an insulating film on a semiconductor substrate;
(2) After forming a layer (Cu—Ti alloy layer) made of a Cu—Ti alloy having the above composition along the recess provided in the insulating film on the semiconductor substrate, the layer is made pure into the recess with the Cu—Ti alloy layer. An example is Cu-based wiring in which Cu is embedded.

  When obtaining the Cu-based wiring of (1) above, the surface of the recess formed in the insulating film is covered with a thin film made of a Cu—Ti alloy having the above component composition, and this is heated and / or pressurized to form Cu. The wiring material is made to flow and embedded in the recess, and then polishing is performed by, for example, a chemical mechanical polishing method to remove unnecessary wiring material deposited on the portion other than the recess, and the Cu material is left only in the recess. A method of forming a wiring is mentioned.

  Further, in order to obtain the Cu-based wiring of (2) above, a Cu—Ti alloy layer having the above component composition is formed as a seed layer along the recess provided in the insulating film, and then the recess with the Cu—Ti alloy layer is formed. In this method, pure Cu is embedded as a full wiring (wiring body portion), and then a Cu-based wiring is formed in the same manner as in the above (1).

  Formation of the thin film made of the Cu—Ti alloy in (1) and the Cu—Ti alloy layer in (2) (hereinafter, these may be collectively referred to as Cu—Ti alloy) are performed by a sputtering method. Because Cu—Ti is an alloy, it is difficult to form by the conventional electrolytic plating method and difficult to form even by the CVD method. Thus, by forming a Cu—Ti alloy by a sputtering method, a non-equilibrium solid solution phenomenon caused by vapor phase quenching can be utilized. In other words, by forming a Cu-Ti alloy with Ti having a small solid solubility limit with respect to Cu formed by a sputtering method, Ti is in a non-equilibrium solid solution state in an As-deposited state, and Ti diffuses. Cu-Ti alloy which is easy to do can be formed.

  In the case of the above (1), it is preferable to form a film with a Cu—Ti alloy as a thin film within a range of 100 nm to 500 nm in thickness by sputtering.

  In the case of (2), it is preferable that a layer made of a Cu—Ti alloy (Cu—Ti alloy layer) is formed along the recesses within a range of 10 nm to 50 nm in thickness by a sputtering method. When the film thickness is less than 10 nm, a Ti-concentrated layer having a sufficient thickness is not generated even when heated, and the barrier property is lowered. A more preferable film thickness is 15 nm or more, and further preferably 20 nm or more. On the other hand, if the film thickness exceeds 50 nm, bridging is likely to occur so that an excessive Cu—Ti alloy layer covers the opening of the recess, and voids are formed in the recess, resulting in deterioration of the quality of the Cu-based wiring. This is not preferable. A more preferable film thickness is 45 nm or less, and still more preferably 40 nm or less.

In order to form a Cu—Ti alloy by sputtering as described above, a Cu alloy target containing Ti may be used as a sputtering target, or a chip-on target having a Ti chip attached to the surface of a pure Cu target may be used. Sputtering in an inert gas atmosphere using the target can be mentioned. As the inert gas, for example, helium, neon, argon, krypton, xenon, radon, or the like can be used. Argon or xenon is preferably used, and argon is particularly inexpensive and can be suitably used. The inert gas may contain N ₂ gas or H ₂ gas.

  Other sputtering conditions (for example, ultimate vacuum, sputtering gas pressure, discharge power density, substrate temperature, interelectrode distance, etc.) can be appropriately adjusted within a normal range.

In the present invention, it is very important to heat the Cu—Ti alloy thus formed so as to satisfy all the following heating conditions. By heating under optimized conditions, the self-barrier forming ability of the Cu-Ti alloy can be sufficiently exerted, and the above-described self-barrier layer can be reliably formed at the interface between the insulating film and the Cu-Ti alloy. it can. Specifically, Ti in the Cu—Ti alloy undergoes two-phase separation, and Ti abnormally diffuses and concentrates at the Cu—Ti alloy / insulating film interface. The interface-enriched Ti reacts with the insulating film to form a layer made of a compound such as TiSi or TiC. This compound layer is extremely thin and uniformly formed at the interface. Further, by heating under the following conditions, Ti can be sufficiently abnormally diffused and concentrated on the surface of the Cu-based wiring (Cu—Ti alloy) that is not in contact with the insulating film. As a result, Cu can be prevented from diffusing into the insulating film, and solid solution Ti or an intermetallic compound of Ti existing in the Cu-based wiring can be eliminated, so that the wiring resistance is more reliably than that of the conventional damascene Cu-based wiring. A Cu-based wiring that can be reduced, has high performance (low electrical resistivity) and high reliability (high EM resistance) can be realized.
(Heating conditions)
Heating temperature: 350-600 ° C
Heating time: 10 to 120 min.
Rate of temperature increase from room temperature to the above heating temperature: 10 ° C./min. Or more Oxygen partial pressure in a heated atmosphere: 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm
Hereinafter, the reason for defining each condition will be described in detail.

<Heating temperature: 350-600 ° C.>
In order to cause abnormal diffusion of Ti contained in the Cu-Ti alloy wiring and segregate and concentrate at the interface between the insulating film and the Cu-Ti alloy, the alloy element (Ti) is added to the Cu-Ti alloy / It is necessary to move and react to a surface not in contact with the insulating film interface or the insulating film of the Cu-based wiring (Cu-Ti alloy). In order to move and react Ti in this metastable state, it is necessary to heat to 350 ° C. or higher. When the heating temperature is lower than 350 ° C., Ti remains in a solid solution state in Cu or forms an intermetallic compound with Cu. In either case, the electrical resistivity cannot be sufficiently lowered, and the effective electrical resistivity of the wiring is increased, which is not preferable. The heating temperature is preferably 400 ° C. or higher. On the other hand, even if the heating temperature is too high, Ti does not easily move or react in the metastable state, so the upper limit of the heating temperature is 600 ° C. Preferably it is 500 degrees C or less.

<Heating time: 10 to 120 min.>
Although the movement / reaction of the alloy element (Ti) in the metastable state at the heating temperature is almost completed within 10 min. (Min), in the present invention, in order to sufficiently promote the movement / reaction of the Ti, The holding time (heating time) at the heating temperature is 10 min. On the other hand, even if the heating time is too long, the effect of reducing the electrical resistivity is saturated and the productivity is lowered, so the heating time is 120 min. Or less.

<Temperature increase rate from room temperature to the above heating temperature: 10 ° C./min. Or more>
In order to move (diffuse) the alloying element (Ti) in the Cu—Ti alloy, a large number of diffusion paths (high-speed diffusion paths) are required, and it is necessary to form through grain boundaries as high-speed diffusion paths. This through grain boundary is formed by heating in the heating temperature range (350 to 600 ° C.). As the rate of temperature increase is faster, a columnar crystal structure is more likely to be formed, and more through grain boundaries are formed. . Therefore, the rate of temperature increase from room temperature to the heating temperature is set to 10 ° C./min.

<Oxygen partial pressure in a heated atmosphere: 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm>
In order to move (diffuse) the alloy element (Ti) in the Cu-Ti alloy to a surface not in contact with the insulating film of the Cu-based wiring (Cu-Ti alloy), a substance that promotes the reaction on the surface is required. Yes, oxygen is effective in this case. In order to sufficiently move (diffuse) Ti and reduce electric resistivity, the oxygen partial pressure in the heating atmosphere is set to 1 × 10 ⁻⁷ atm or more. On the other hand, if the oxygen partial pressure in the heating atmosphere is too high, Ti oxide is firmly formed on the surface and grain boundaries in the initial stage of heating, and the high-speed diffusion path of Ti is blocked. Cannot be reduced. Therefore, in this invention, the oxygen partial pressure in a heating atmosphere shall be 1 * 10 < ^-4 > atm or less.

  Heating under the above conditions can be performed at the following times.

  In the case of (1) above, (1-1) a Cu—Ti alloy (thin film) is formed by sputtering so as to cover the recess, and then heated to embed the Cu—Ti alloy in the recess, or Heating under the above conditions at the time of pressurization can be mentioned. Further, (1-2) a Cu—Ti alloy (thin film) is formed by sputtering so as to cover the recess, and the Cu—Ti alloy (thin film) is embedded in the recess to form a wiring, and then heated under the above conditions. To do. In addition, the conditions currently performed can be employ | adopted for the pressurization conditions for the said embedding, and the heating conditions for the embedding in the case of (1-2).

  In the case of (2) above, after forming the Cu—Ti alloy layer by sputtering along the recess, before or after forming the wiring main body portion made of pure Cu (formed by electrolytic plating, sputtering, etc.) And heating under the above conditions.

  In addition, the manufacturing method of the present invention is characterized in that after a specific Cu—Ti alloy is formed by a sputtering method, a step of heating the Cu—Ti alloy under the above conditions is provided. For other manufacturing steps and conditions, For example, the following conditions can be employed regardless of the particular conditions.

As the insulating film, a silicon oxide film (SiO ₂ ), SiCO containing SiC in the silicon oxide film (SiO ₂ ), SiCN, or the like can be used.

  The method of embedding pure Cu as a full wiring (wiring body part) in the case of forming the Cu-based wiring of (2) is not particularly limited. For example, an electrolytic plating method, a chemical vapor deposition method (CVD method), a sputtering method is used. , (Arc) ion plating method and the like can be employed. In particular, if electrolytic plating is employed, pure Cu can be filled while gradually filling from the bottom of the recess with the Cu-Ti alloy layer, so that even if the minimum width of the recess is narrow and deep, pure Cu is filled in the corners of the recess. It can be embedded throughout. In the case of the sputtering method, first, a pure Cu thin film is preferably formed so as to cover the concave portion with the Cu—Ti alloy layer, and then this pure Cu thin film is embedded in the concave portion with the layer made of the Cu—Ti alloy. In this case, the conditions described in Patent Document 1 can be employed as the sputtering method conditions and the embedding conditions (except for the heating conditions when heating is performed under the above conditions during embedding).

  Hereinafter, the present invention will be described in more detail with reference to examples. However, the following examples are not intended to limit the present invention, and may be implemented with appropriate modifications within a range that can meet the purpose described above and below. These are all possible and are within the scope of the present invention.

[Example 1]
A substrate on which a SiCO film as an insulating film is formed to a thickness of 100 nm is prepared on the surface of a silicon wafer, and a Cu-1.0 atomic% (at%) Ti alloy thin film is formed on the surface of the insulating film by a DC magnetron. A film was formed by a sputtering method so as to have a film thickness of 300 nm. The sputtering conditions (film formation conditions) were as follows, and the composition of the Cu alloy thin film was adjusted using a chip-on target as a target. As the chip-on target, a chip in which 3 to 6 Ti chips (rectangular plates having a thickness of 1 mm) were radially attached to the surface of a pure Cu target (80 mmφ) serving as a base was used.

(Deposition conditions)
Ultimate vacuum: 1 × 10 ⁻⁸ Torr or less Atmospheric gas during sputtering: Ar
Sputtering gas pressure: 8 × ¹⁰ -3 Torr
Discharge power: 300W
Target size: φ80mm
Substrate temperature (Ts): RT (water cooling)
Distance between electrodes: 100mm

  A sample (Cu alloy thin film) obtained by film formation was placed in a horizontal tubular furnace using a quartz tube and heat-treated. The heat treatment is performed by changing the heat treatment atmosphere to a vacuum atmosphere in which the degree of vacuum is changed or an atmosphere (Ar flow rate: 20 mL / min.) In which Ar gas having a different purity (residual oxygen concentration) is flowed. The partial pressure was changed. Heating rate: Heated from room temperature to 400 ° C. at 200 ° C./min. And subjected to heat treatment for 2 hours to obtain a heat-treated sample (Cu alloy thin film).

  Next, the sheet resistance of the Cu alloy thin film was measured by a four-probe method for the sample in the As-deposited (non-heat treated) state and the sample subjected to the heat treatment, and the electrical resistivity ( μΩ · cm) was calculated.

FIG. 1 shows the result of organizing the relationship between the oxygen partial pressure in the heat treatment atmosphere and the electrical resistivity of the sample. As can be seen from FIG. 1, the electrical resistivity varies depending on the oxygen partial pressure during the heat treatment, and there exists an optimum oxygen partial pressure region in which the electrical resistivity is minimized. Specifically, it can be seen that a low electrical resistivity of ⁴ μΩ · cm or less can be achieved by setting the oxygen partial pressure in the heat treatment atmosphere to 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm defined in the present invention. In addition, the electrical resistivity of the sample in an As-deposited (non-heat treated) state was 16 to 20 μΩ · cm.

[Example 2]
In the heat treatment, a sample was prepared and the electrical resistivity was measured in the same manner as in Example 1 except that the sample was heated from room temperature to 500 ° C. and kept at a heating temperature of 500 ° C.

  FIG. 2 shows the results of organizing the relationship between the oxygen partial pressure in the heat treatment atmosphere and the electrical resistivity of the sample. From FIG. 2, the electrical resistivity is slightly lowered as compared with the case of heat treatment at 400 ° C., and the oxygen partial pressure dependency of the electrical resistivity is the same as that shown in FIG. 1 (heating temperature during heat treatment: 400 ° C. ) Shows the same trend. That is, it is presumed that there exists an optimum oxygen partial pressure region where the electric resistivity is minimized, and the optimum oxygen partial pressure region where the electric resistivity is minimized is considered to be the same as when the heating temperature during the heat treatment is 400 ° C.

[Example 3]
In the above heat treatment, a sample was prepared and the electrical resistivity was measured in the same manner as in Example 1 except that the sample was heated from room temperature to 600 ° C. and held at a heating temperature of 600 ° C.

  FIG. 3 shows the result of organizing the relationship between the oxygen partial pressure in the heat treatment atmosphere and the electrical resistivity of the sample. From FIG. 3, the electrical resistivity is generally reduced as compared with the case where the heat treatment is performed at 400 ° C., and the oxygen partial pressure dependency of the electrical resistivity is as shown in FIG. 1 (heating temperature during heat treatment: 400 ° C.). The same tendency as in the case of. That is, it is presumed that there exists an optimum oxygen partial pressure region where the electric resistivity is minimized, and the optimum oxygen partial pressure region where the electric resistivity is minimized is considered to be the same as when the heating temperature during the heat treatment is 400 ° C.

[Example 4]
A sample was prepared and the electrical resistivity was measured in the same manner as in Example 1 except that a SiO ₂ film, a SiCO film, or a SiCN film was formed as an insulating film.

  FIG. 4 shows the relationship between the oxygen partial pressure in the heat treatment atmosphere (heating atmosphere) and the electrical resistivity of the sample for each type of insulating film. FIG. 4 shows that the electrical resistivity varies depending on the oxygen partial pressure during the heat treatment, but hardly changes depending on the type of the insulating film.

[Example 5]
To the formation of the SiO ₂ film as the insulating film, and in the heat treatment, the oxygen partial pressure in the heat treatment atmosphere (heating atmosphere) and 2 × ¹⁰ -6 atm, 600 ℃ heating temperature (temperature reached room temperature) from 350 ° C. A sample was prepared and the electrical resistivity was measured in the same manner as in Example 1 except that the electric resistance was changed.

  The result of arranging the relationship between the heating temperature during the heat treatment and the electrical resistivity of the sample is shown in FIG. FIG. 5 shows that the electrical resistivity decreases as the heating temperature during the heat treatment increases.

[Example 6]
In forming the SiO ₂ film as the insulating film and in the heat treatment, the oxygen partial pressure in the heat treatment atmosphere is set to 2 × 10 ⁻⁶ atm, and the heating time at 400 ° C. is changed between 0 to 120 min. Except for the above, a sample was prepared and the electrical resistivity was measured in the same manner as in Example 1.

  FIG. 6 shows the results of arranging the relationship between the heating time during heat treatment (the time for holding at the heating temperature) and the electrical resistivity of the sample. From FIG. 6, the electrical resistivity of the sample rapidly decreases by heat treatment, and in order to achieve an electrical resistivity of 4 μΩ · cm or less, it is necessary to set the heating time to 10 min. It can be seen that the effect of lowering the electrical resistivity is saturated even if the process is performed.

Claims (2)

A method for manufacturing a semiconductor wiring, in which a Cu-Ti alloy is directly embedded in a recess provided in an insulating film on a semiconductor substrate,
The Cu-Ti alloy contains 0.5 atomic% to 3.0 atomic% of Ti, and
Forming a Cu-Ti alloy by sputtering and heating the Cu-Ti alloy under the following heating conditions when or after the Cu-Ti alloy is embedded in the recess. Production method.
(Heating conditions)
Heating temperature: 350-600 ° C
Heating time: 10 to 120 min.
Temperature increase rate from room temperature to the above heating temperature: 10 ° C./min. Or more Oxygen partial pressure in a heating atmosphere: 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm A semiconductor wiring manufacturing method in which a layer made of a Cu-Ti alloy is formed along a recess provided in an insulating film on a semiconductor substrate, and then pure Cu is embedded in the recess with the layer made of the Cu-Ti alloy. There,
The Cu-Ti alloy contains 0.5 atomic% to 3.0 atomic% of Ti, and
A method of manufacturing a semiconductor wiring, comprising: a step of forming a layer made of the Cu-Ti alloy by a sputtering method; and a step of heating the layer made of the Cu-Ti alloy under the following heating conditions.
(Heating conditions)
Heating temperature: 350-600 ° C
Heating time: 10 to 120 min.
Temperature increase rate from room temperature to the above heating temperature: 10 ° C./min. Or more Oxygen partial pressure in a heating atmosphere: 1 × 10 ⁻⁷ to 1 × 10 ⁻⁴ atm

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