JP2010016122A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem of a redundancy function of a semiconductor integrated circuit in the prior art that the cost increases because many processing steps such as dicing of good chips of a functional group, open circuit of interconnect, and the like, are required, and the yield decreases and miniaturization of a product is impeded when redundancy circuitry is employed. <P>SOLUTION: A first semiconductor chip with bumps for external connection which are electrically connected with signal lines for delivering/receiving signals to/from a plurality of functional blocks in the chip, and a second semiconductor chip with pads for external connection which are electrically connected with signal lines for delivering/receiving signals to/from a plurality of functional blocks in the chip and are arranged to be mirror symmetrical with respect to the arrangement of bumps of the first semiconductor chip are joined together while facing the surfaces so that the bumps touch the pads, and the signal lines belonging, respectively, to the first semiconductor chip and the second semiconductor chip electrically connected with the bumps and pads are electrically connected at the joints of the bumps and pads. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to formation of a fault relief means and a redundant circuit in preparation for a failure.

  In a semiconductor integrated circuit in which a circuit is formed on a semiconductor chip, the occurrence of a defective chip directly affects the yield per wafer, which increases the cost of the semiconductor integrated circuit. As one method for relieving defective chips, a method has been proposed in which a non-defective functional block on a corresponding functional block is overlaid and electrically connected to a defective functional block on the chip as disclosed in Patent Document 1. Yes.

  On the other hand, large-scale semiconductor integrated circuits are required to be used in fields that require stable and normal operation, such as automobiles, aircraft, and the space industry. In these fields, it is required that failures in semiconductor integrated circuits are reliably detected in the field and no malfunction occurs. To configure a clock tree circuit with a small clock skew, the clock wiring and the buffer are fixed, and the buffer and wiring distance are constant. A method of forming a combination of various panels (for example, Patent Document 1) has been proposed.

JP-A-5-133631 Pages 2-4, Figure 1

  A method proposed as a conventional means for repairing a defect in a semiconductor integrated circuit is widely used because it requires many chip processing steps such as cutting out non-defective chips of functional blocks and cutting of wiring, and the chip processing cost increases. Not.

  Furthermore, when trying to make a redundant circuit configuration for failure in a conventional semiconductor integrated circuit, a method of forming a redundant circuit in the same chip, a method of arranging chips of the same function on the mounting substrate, etc. are used. However, there are problems such as deterioration in yield due to increase in chip area and reduction in product size due to increase in area of the mounting substrate.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to effectively improve the yield of a semiconductor integrated circuit and realize a redundant circuit configuration at a low cost by using the same means. And

A semiconductor integrated circuit according to the present invention includes:
A plurality of functional blocks arranged in the chip, inter-block signal wiring for transmitting / receiving signals to the functional block, and external connection bumps arranged on the chip surface and electrically connected to the signal wiring A first semiconductor chip comprising:
Similarly, a plurality of functional blocks disposed in the chip, inter-block signal wiring for transmitting / receiving signals to the functional block, disposed on the chip surface, electrically connected to the signal wiring, and the first semiconductor A second semiconductor chip provided with an external connection pad disposed so as to be mirror-symmetrical with the arrangement of bumps in the chip,
The first and second semiconductor chips and the second semiconductor are electrically connected to the bump and the pad, with the surfaces of the first semiconductor chip and the second semiconductor chip facing each other so that the bump and the pad are in contact with each other. The inter-block signal wiring belonging to each chip is electrically connected at the contact portion between the bump and the pad.

According to the semiconductor integrated circuit of the present invention,
A defective semiconductor chip composed of two mirrors is bonded together in a combination that complements a defective block to form a single semiconductor integrated circuit, thereby repairing the defective chip and converting the defective chip into a good semiconductor. An integrated circuit can be obtained.
In another invention, when configuring a semiconductor integrated circuit, an output signal control element for controlling an output signal from the functional block to the inter-block signal wiring by a signal from the outside of the functional block in advance in the semiconductor chip, , Select multiple signal input elements that input signals from multiple inter-block signal wires on the input side of the functional block, and select which signal input elements to input from outside the functional block to the output side of the multiple signal input elements If the desired configuration such as a selection circuit that can be used and a comparison circuit that compares the output signals of a plurality of functional blocks and holds the comparison result as an internal signal or outputs the signal to the outside of the functional block is used There is no need for physical processing such as cutting out functional blocks or cutting wires.

Embodiment 1 FIG.
1 is a block diagram showing a schematic configuration viewed from the surface of a semiconductor chip constituting a semiconductor integrated circuit according to Embodiment 1 of the present invention.
In FIG. 1, a semiconductor chip 1 has a functional block 2, a functional block 3, and a functional block 4 inside the chip. The functional block and the functional block are electrically connected by an inter-block signal wiring 5. The semiconductor chip 1 is formed in contact with the inter-block signal wiring 5 and has external connection bumps 6 electrically connected to the inter-block signal wiring 5. The formation location of the bump 6 for external connection is not limited to being on the inter-block signal wiring 5, but may be electrically connected to the inter-block signal wiring 5.
The semiconductor chip 101 has the same components as the semiconductor chip 1. That is, it has a functional block 102, a functional block 103, a functional block 104, an inter-block signal wiring 105, and a pad 106 for external connection. The semiconductor chip 101 is manufactured by using a mask for manufacturing the semiconductor chip 1 upside down. For this reason, the wiring arrangement of the semiconductor chip 101 is mirror-symmetric with respect to the wiring arrangement of the semiconductor chip 1.

  A bump is a protruding terminal formed on the surface of a semiconductor chip and directly exchanges signals with another semiconductor chip or a connection substrate, and is formed by processes such as vapor deposition, plating, and printing. Here, the material and forming method of the bump are not particularly limited.

The semiconductor integrated circuit according to the first embodiment of the present invention is configured by bonding the surfaces of the semiconductor chip 1 and the semiconductor chip 101 face to face. FIG. 2 is a vertical sectional view showing a schematic configuration of the semiconductor integrated circuit according to the first embodiment of the present invention.
Since the external connection bumps 6 formed on the surface of the semiconductor chip 1 and the external connection pads 106 formed on the surface of the semiconductor chip 101 are arranged at mirror-symmetric positions on the chip as described above. As shown in FIG. 2, the bumps 6 and the pads 106 arranged in large numbers on the chip face to face can be bonded to each other. In the semiconductor integrated circuit 201 configured as described above, the inter-block signal wiring 5 and the inter-block signal wiring 105 are electrically connected by the contact between the bump 6 and the pad 106.

FIG. 3 shows a circuit diagram of an electric circuit of a connection portion between functional blocks configured by being electrically connected between the semiconductor chip 1 and the semiconductor chip 101 by contacting the bump 6 and the pad 106. .
FIG. 3 shows an inter-block signal wiring circuit in which a signal is output from the functional block 3 arranged on the semiconductor chip 1 and input to the functional block 4. The function block 3 on the output side includes an output buffer 10 as an output signal control element and an output buffer 11 as an output signal control element on the output side. The output buffer 10 and the output buffer 11 have outputs on the output side of the function block 3. Connected to signal terminal 17.

  The function block 4 on the input side includes an input buffer 12 as a signal input element that receives a signal from the output buffer 10 and an input buffer 13 as a signal input element that receives a signal from the output buffer 11. The input buffer 12 and the input buffer 13 And a selection circuit 15 that selects and outputs one of the output signals of the input buffer 12 and the input buffer 13.

  Furthermore, the semiconductor chip 1 includes a control observation unit 16 that switches the output state of the output buffers 10 and 11 and instructs the selection circuit 15 to switch based on the comparison result of the comparison circuit 14.

A semiconductor chip 101 that is mirror-symmetrical with the semiconductor chip 1 is also identical in configuration to the semiconductor chip 1, and includes an output buffer 110 as an output signal control element, an output buffer 111 as an output signal control element, and an input buffer as a signal input element. 112 and an input buffer 113 as a signal input element, a comparison circuit 114, a selection circuit 115, and a control observation unit 116. The input side of the output buffer 110 and the output buffer 111 is connected to the output signal terminal 117 of the functional block 103.
Since the elements constituting the corresponding wiring and functional block of the semiconductor chip 1 and the semiconductor chip 101 are manufactured in exactly the same design and manufacturing process except that they are arranged in mirror symmetry, there is no significant difference in their characteristics. .

Next, the operation will be described.
Each of the semiconductor chip 1 and the semiconductor chip 101 is manufactured by a general semiconductor process in which a circuit is formed on the surface of a silicon wafer. In both chips, if a good product is obtained as a single chip, it can be packaged and shipped as a single chip.
Here, consider a case where there is a defect in part of the semiconductor chip 1 and the semiconductor chip 101. Assume that a defect exists only in the functional block 3 of the semiconductor chip 1 by using a defect detection and diagnosis means such as a scan test. On the other hand, the operation of the semiconductor chip 101 will be described based on an example in which a failure of the functional block 104 is detected by the same failure detection and diagnosis means. In this case, since the functional block 103 and the functional block 4 have normal functions, a semiconductor integrated circuit having the same function as the normal semiconductor chip 1 or the semiconductor chip 101 can be obtained by combining these functional blocks.

Specifically, the output buffer 11 of the semiconductor chip 1 is turned off, the selection circuit 15 is controlled from the control observation unit 16 so as to select the input buffer 13 side, and the output buffer 111 of the semiconductor chip 101 is turned on. Set from the control observation unit 116. Thereby, the signal connection between the functional block 103 and the functional block 4 which can operate normally is ensured. By appropriately setting the functional blocks between the semiconductor chip 1 and the semiconductor chip 101 as described above, defects in the semiconductor chip can be remedied.
In FIG. 3, for simplicity of explanation, the external connection bump 6 on the inter-block signal wiring 5 from the output buffer 11 and the external connection pad 106 on the inter-block signal wiring 105 from the output buffer 111. In this example, all of the external connection bumps 6 and the external connection pads 106 shown in FIG. 1 may be connected. In that case, the comparison circuits 14 and 114, the selection circuits 15 and 115, and the control observation units 16 and 116 perform appropriate operations.

  The semiconductor integrated circuit 201 obtained in this way is used as a component of various electronic devices by being sealed in an appropriate package or the like, or after being directly mounted on a board.

  As described above, defective products of two mirror-symmetrical semiconductor chips are bonded together in a combination that complements the defective block to constitute one semiconductor integrated circuit, so that the defective chip can be relieved and the two defective chips can be recovered. One good semiconductor integrated circuit can be obtained. When a semiconductor integrated circuit is configured, if a desired configuration is made in the semiconductor chip in advance, physical processing such as cutting out a functional block of wiring on the semiconductor chip or cutting of the wiring is not necessary.

Embodiment 2. FIG.
Although the first embodiment has shown an example in which a part of the functional blocks of both of the two semiconductor chips is a defective chip, it is also possible to configure a semiconductor integrated circuit by combining non-defective semiconductor chips with the same configuration. It is.
In this case, it is used as a redundant semiconductor integrated circuit in which two identical circuits are configured. In FIG. 3, by turning on the output buffer 10 and switching the selection circuit 15 to the input buffer 12 side, the semiconductor chip 1 can operate independently of the connected semiconductor 101.

  Similarly, the semiconductor 101 can operate independently by controlling the output buffer 110 and the selection circuit 115. When the output buffer 111 is controlled to be turned on at an appropriate timing during this operation, the comparison circuit 14 in the semiconductor chip 1 compares the signal value on the semiconductor chip 1 with the corresponding signal value on the semiconductor chip 101 and performs control observation. The comparison result can be read by the unit 16. When the semiconductor chip 1 and the semiconductor chip 101 are operating normally independently for the same input, the comparison results should always match. By detecting the case where the comparison results do not match, it is possible to detect that an abnormality has occurred in one of the two semiconductor chips. When an abnormality is detected, by determining which chip has a failure in combination with a test means such as a built-in self-test, the fault block separation means described in the first embodiment is used. The semiconductor integrated circuit is mounted so that the function of only the defective block of the semiconductor chip is not used, the redundant structure is maintained for the other functional blocks, and the comparison circuit 14 and the comparison circuit 114 are made effective in chip mutual comparison. You can continue to use the device.

  In the above description of the embodiment, the operation focusing on one of the bumps on the surface of the semiconductor chip is described so that the description is not complicated, but actually the same manufacturing process is applied to another bump on the semiconductor chip. The effect can be obtained by applying. The figures used in the description show only a very small number of bumps, but the gist of the present invention does not depend on the number of bumps, and the bumps balance the operation of the comparison circuit, selection circuit and control observation unit. Therefore, it can be configured by a large number or a small number.

  The present invention is applicable to semiconductor integrated circuits used in fields that require stable and normal operation such as automobiles, aircraft, and space industries, and is particularly convenient for large-scale semiconductor integrated circuits.

1 is a plan view showing a schematic configuration of a semiconductor chip constituting a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a vertical sectional view showing a schematic configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a circuit diagram showing a schematic configuration of an electric circuit formed in a semiconductor integrated circuit according to a first embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor chip, 2 * 3 * 4 * 102 * 103 * 104 functional block, 5 * 105 signal wiring between blocks, 6 bump, 106 pad, 10 * 11 * 110 * 111 output buffer, 12 * 13 * 112 113 input buffer, 14/114 comparison circuit, 15/115 selection circuit, 16/116 control observation unit, 101 second semiconductor chip, 201 semiconductor integrated circuit.

Claims (6)

A plurality of functional blocks arranged in the chip, inter-block signal wiring for transmitting / receiving signals to the functional block, and external connection bumps arranged on the chip surface and electrically connected to the signal wiring A first semiconductor chip comprising:
Similarly, a plurality of functional blocks disposed in the chip, inter-block signal wiring for transmitting / receiving signals to the functional block, disposed on the chip surface, electrically connected to the signal wiring, and the first semiconductor A second semiconductor chip provided with an external connection pad disposed so as to be mirror-symmetrical with the arrangement of bumps in the chip,
The first and second semiconductor chips and the second semiconductor are electrically connected to the bump and the pad, with the surfaces of the first semiconductor chip and the second semiconductor chip facing each other so that the bump and the pad are in contact with each other. A semiconductor integrated circuit characterized in that inter-block signal wiring belonging to each chip is electrically connected at a contact portion between a bump and a pad.   The functional block and inter-block signal wiring formed on the second semiconductor chip are arranged to be mirror-symmetric with each other on the functional block and inter-block signal wiring formed on the first semiconductor chip. The semiconductor integrated circuit according to claim 1.   2. The bumps and pads for external connection disposed on the first semiconductor chip and the second semiconductor chip, respectively, are formed on inter-block signal wirings on the respective semiconductor chips. The semiconductor integrated circuit according to claim 2.   A signal from the outside of the functional block controls the output signal from the functional block to the inter-block signal wirings respectively connected to the bumps and pads for external connection arranged in the first semiconductor chip and the second semiconductor chip, respectively. 4. The semiconductor integrated circuit according to claim 1, further comprising an output signal control element that is used in step 1.   A plurality of signal input elements on the input side of a functional block for inputting signals from inter-block signal wirings connected to bumps and pads for external connection disposed in the first semiconductor chip and the second semiconductor chip, 4. The selection circuit according to claim 1, further comprising: a selection circuit capable of selecting an output of which signal input element is input from the outside of the functional block on an output side of the plurality of signal input elements. 5. Semiconductor integrated circuit.   At least one of the first semiconductor chip and the second semiconductor chip is connected to the other semiconductor chip coupled in a face-to-face manner that can be observed through the connection between the output signal of the function block inside the semiconductor chip and the bump and the pad. 5. The comparison circuit according to claim 1, further comprising a comparison circuit that compares output signals of corresponding functional blocks and holds the comparison result as an internal signal or outputs the signal to the outside of the functional block. Semiconductor integrated circuit.

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