JP2008004783A - High withstand voltage semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high withstand voltage MOS semiconductor device capable of raising a withstand voltage in an off-state, and suppressing the deterioration of electric current ability. <P>SOLUTION: A MOS transistor includes: a first conductivity-type well region 4 to be formed on a semiconductor layer 3; a second conductivity-type high concentration source region 6 to be selectively formed on the well region 4; a second conductivity-type high concentration drain region 5 which is formed on the semiconductor layer 3, so as to be separated from the well region 4; a second conductivity-type middle concentration deep well region 11 to be formed in a region including the drain region 5; a second conductivity-type low concentration drift region 10 which is formed from the end of the well region 4 to the side of the drain region 5 in the semiconductor layer 3, and does not reach an embedded insulating film 2; and a gate electrode 9 via a gate insulating film 8 between the end of the source region 6 and the end of the low concentration drift region 10. The surface concentration of the deep well region 11 is made to be not more than that of the low concentration drift region 10 in the MOS transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high voltage semiconductor device formed on an SOI substrate and a method for manufacturing the same.

  As isolation between elements of a semiconductor device, a junction isolation technique using a PN junction has been used for many years. However, in recent years, an SOI (silicon on insulator) substrate having a buried insulating film is formed with dielectric isolation in which a trench reaching from the surface of the SOI substrate to the buried insulating film is formed, and an insulating film is formed inside the trench. It is coming. In particular, semiconductor devices in the field of high withstand voltage power, which generally require deep isolation, have the disadvantage that the area of the isolation region becomes large when PN junction isolation is used, but using SOI-trench isolation. Thus, the area of the separation region can be reduced, and there is an advantage that the chip can be miniaturized.

  From the above, high withstand voltage power elements formed on an SOI substrate have attracted attention. Generally, the performance of a high voltage power device is indicated by its breakdown voltage (breakdown breakdown voltage) and on-resistance, but these are in a trade-off relationship, and how to achieve both high breakdown voltage and low on-resistance. Focusing on this point, it has been developed for many years. Particularly in recent years, high withstand voltage power semiconductor products using an SOI substrate have also been mass-produced, and development of high withstand voltage and low on-resistance high withstand voltage power elements formed on the SOI substrate has become active.

  As an example of a conventional high voltage NMOS transistor, the one shown in FIG. 2 is known (for example, refer to Patent Document 1). It should be noted that the dimensions are different from the actual ones.

As shown in FIG. 2A, a low-concentration P-type semiconductor layer 3 is bonded on a support substrate 1 with a buried insulating film 2 interposed therebetween. In the P-type semiconductor layer 3, a P-type well region 4 and an N-type drift region 10 are diffused at intervals. Further, the N ⁺ type source region 6 and the P ⁺ type contact diffusion region 7 are diffused on the inner surface of the P well region 4, and the N ⁺ type drain region 5 is diffused on the inner surface of the N type drift region 10. . In the region including the N ⁺ -type drain region 5, the N-type deep well concentration diffusion layer 11 diffused deeper than that is diffused. Here, the impurity concentration of the N-type deep well concentration diffusion layer 11 is set to an intermediate level between the impurity concentrations of the N ⁺ -type drain region 5 and the N-type drift region 10. The concentration of the N-type drift region 10 is set to around 3.7 × 10 ¹⁶ [cm ⁻³ ], and the concentration of the N ⁺ -type drain region 5 is set to 1 × 10 ¹⁹ [cm ⁻³ ] or more. The surface concentration of the intermediate concentration layer 11 is about 1.5 × 10 ¹⁷ [cm ⁻³ ], which is set higher than the impurity concentration of the N-type drift region 10.

A field oxide film 14 is formed on the surface of the N-type drift region 10. Between the end of the N ⁺ type source region 6 and the end of the N type drift region 10, an N ⁺ type Poly-Si film gate electrode 9 is formed via a gate insulating film 8. A source electrode 12 is formed on the N ⁺ -type source region 6 and the P ⁺ -type contact diffusion region 7, while a drain electrode 13 is formed on the N ⁺ -type drain region 5.

In such a high breakdown voltage NMOS transistor, as a bias state when measuring the breakdown voltage when off, the source electrode, the gate electrode, and the substrate electrode are set to GND, and a positive potential is applied to the drain electrode. When a reverse bias is applied between the drain and source in this way, the P-type well region 4 and the P-type semiconductor layer 3 therebelow are depleted, and the voltage applied between the drain and source is supported by this depletion layer. ing. When the voltage applied between the drain and source is increased, the avalanche breakdown occurs when the electric field formed in the depletion layer reaches the critical electric field, so that current suddenly starts to flow between the drain and source. Thus, the applied voltage value at this time becomes the withstand voltage value of the transistor.
Japanese Patent Laid-Open No. 11-251597

FIG. 2B shows the relationship between the depth from the surface of the N ⁺ -type drain region 5, the N-type deep well concentration diffusion layer 11, and the N-type drift region 10 and the impurity concentration in the conventional example. In the conventional structure in which the deep well concentration diffusion layer is inserted, the surface concentration of the deep well concentration diffusion layer 11 is set higher than the impurity concentration of the N-type drift region 10. This is to suppress the on-state bipolar operation and increase the sustain breakdown voltage. Thereby, since the spread of the depletion layer near the surface is suppressed, there is a problem that it is difficult to improve the off breakdown voltage.

  This is because, when the concentration near the surface of the N-type deep well concentration diffusion layer 11 is high, if the voltage applied between the drain and the source is increased in the off state, the depletion layer near the surface is difficult to extend, and therefore the potential distribution has a slope. It becomes sudden and the electric field strength increases. When the depletion region reaches such a region where the electric field strength is strong, impact ionization occurs and avalanche breakdown occurs.

  Therefore, there has been a problem that it is difficult to improve the off breakdown voltage by inserting an N type deep well concentration diffusion layer having a high concentration near the surface.

  Accordingly, an object of the present invention is to provide a high breakdown voltage semiconductor device and a manufacturing method thereof that can further improve the off breakdown voltage in a structure in which a deep well diffusion layer is inserted.

  In order to achieve the above object, a high voltage semiconductor device according to a first aspect of the present invention is a high voltage semiconductor device formed on an SOI substrate having a semiconductor layer formed on a support substrate through a buried insulating film, A first conductivity type well region formed in the semiconductor layer; a second conductivity type high concentration source region selectively formed in the well region; and a second conductivity type formed in the semiconductor layer spaced apart from the well region. A conductive type high-concentration drain region, a second conductive type low-concentration drift region that is formed in the semiconductor layer from the end of the well region to the drain region side and does not reach the buried insulating film, and a predetermined region including the drain region. A medium-concentration deep well region having a second conductivity type and a gate electrode formed between the source region end and the low-concentration drift region end through a gate insulating film, Once again, characterized in that the following surface concentration of the low concentration drift region.

  A high breakdown voltage semiconductor device according to a second aspect of the present invention is the high breakdown voltage semiconductor device according to the first aspect of the present invention, comprising a body contact region of the first conductivity type formed in a region different from the source region of the well region.

  A high breakdown voltage semiconductor device according to a third aspect of the present invention is the high breakdown voltage semiconductor device according to the first or second aspect, wherein the semiconductor layer is of the first conductivity type.

  A high breakdown voltage semiconductor device according to a fourth aspect of the present invention is the high breakdown voltage semiconductor device according to the first, second or third aspect, wherein the junction with the semiconductor layer in the medium concentration deep well region is made by the junction between the low concentration drift region and the semiconductor layer. Deepen.

  According to a fifth aspect of the present invention, there is provided a high breakdown voltage semiconductor device manufacturing method according to the first aspect of the present invention, wherein the medium concentration deep well region and the low concentration drift region are formed by implanting impurity ions, respectively. And the step of setting the implantation energy of the medium concentration deep well region to be higher than the implantation energy of the low concentration drift region.

  According to the high breakdown voltage semiconductor device of the present invention, since the surface concentration of the medium concentration deep well region is set to be equal to or lower than the surface concentration of the low concentration drift region, when a high voltage is applied between the drain and the source, The depletion region extends from the surface side and the buried insulating film side to the low concentration drift region and is completely depleted before breakdown. Since the concentration in the vicinity of the surface of the deep well concentration diffusion layer is set lower than that in the conventional structure, the spread of the depletion region near the surface is promoted more than in the conventional structure, so that the gradient of the potential distribution can be moderated, and the electric field The strength can be reduced and the breakdown voltage in the off state can be improved.

  In addition, regarding the current capability, the total dose in the drain region is not changed from the conventional one, and it is considered that the carrier flow is ensured. Therefore, the decrease in the concentration near the surface is suppressed.

  Therefore, the present invention can realize an excellent high withstand voltage semiconductor device that can improve the off withstand voltage and suppress the decrease in current capability.

  In the present invention, it is preferable that a body contact region of the first conductivity type formed in a region different from the source region of the well region is provided.

  Moreover, in this invention, it is preferable that a semiconductor layer is a 1st conductivity type.

  In the present invention, the junction with the semiconductor layer in the medium concentration deep well region is preferably deeper than the junction between the low concentration drift region and the semiconductor layer.

  According to the high breakdown voltage semiconductor device manufacturing method of the present invention, the intermediate concentration deep well region and the low concentration drift region are formed by implanting impurity ions, respectively, and the implantation energy of the intermediate concentration deep well region is reduced to a low concentration. Since it is set higher than the implantation energy of the drift region, the surface concentration of the medium concentration deep well region can be made lower than the surface concentration of the low concentration drift region. Thereby, the same effect as that of the high voltage semiconductor device of the present invention can be obtained.

  Hereinafter, a high voltage semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a schematic cross-sectional view of a high voltage NMOS transistor according to an embodiment of the present invention.

  As shown in FIG. 1A, a high-voltage semiconductor device formed on an SOI substrate having a semiconductor layer 3 formed on a support substrate 1 via a buried insulating film 2, formed on the semiconductor layer 3. The first conductivity type well region 4, the first conductivity type body contact region 7 selectively formed in the well region 4, and the second conductivity type source region 6 selectively formed in the well region 4. A high-concentration drain region 5 of the second conductivity type formed in the semiconductor layer 3 so as to be separated from the well region 4, and a buried insulating film 2 formed on the semiconductor layer 3 from the end of the well region 4 to the drain region 5 side. A low-concentration drift region 10 of the second conductivity type that does not reach the end, a medium-concentration deep well region 11 formed in a predetermined region including the drain region 5, and an end of the low-concentration drift region 10 from the end of the source region 6 During the gate break MOS transistor having a gate electrode 9 formed through the film 8 is formed. In this configuration, the surface concentration of the N-type deep well concentration diffusion layer 11 is set to be equal to or lower than the surface concentration of the N-type drift region 10.

In this case, a low-concentration P-type semiconductor layer 3 having a film thickness of 3.5 μm is laminated on the support substrate 1 with a buried insulating film 2 interposed therebetween. In the P-type semiconductor layer 3, a P-type well region 4 and an N-type drift region 10 are formed at intervals. Further, an N ⁺ type source region 6 and a P ⁺ type contact diffusion region 7 are formed on the surface of the P type well region 4, and an N ⁺ type drain region 5 is formed in the N type drift 10 region. Further, an N-type deep well concentration diffusion layer 11 is formed in a region including the N ⁺ -type drain region 5. Here, the impurity concentration of the N-type deep well concentration diffusion layer 11 is set to an intermediate level between the impurity concentrations of the N ⁺ -type drain region 5 and the N-type drift region 10, and the implantation energy is higher than that of the N-type drift region 10. Is set. Further, the concentration of the N-type drift region 10 is 4 × 10 ¹⁷ [cm ⁻³ ] and does not reach the buried insulating film 2. On the other hand, the N ⁺ -type drain region 5 has a surface concentration of 1 × 10 ²⁰ [cm ⁻³ ] and a diffusion depth of about 0.1 μm.

A field oxide film 14 having a thickness of 0.5 μm is formed on the surface of the N-type drift region 10. Between the end of the N ⁺ type source region 6 and the end of the N type drift region 10, an N ⁺ type Poly-Si film gate electrode 9 is formed via a gate insulating film 8. A source electrode 12 is formed on the N ⁺ -type source region 6 and the P ⁺ -type contact diffusion region 7, while a drain electrode 13 is formed on the N ⁺ -type drain region 5.

FIG. 1B shows the relationship between the depth from the surface of the N ⁺ -type drain region 5, the N-type deep well concentration diffusion layer 11, and the N-type drift region 10 and the impurity concentration in the embodiment of the present invention.

  In this structure, when the N-type deep well concentration diffusion layer 11 and the N-type drift region 10 are formed by implanting impurity ions, the implantation energy of the N-type deep well concentration diffusion layer 11 is changed to the N-type drift region 10. Set higher than the injection energy. That is, the impurity concentration peak of the N-type deep well concentration diffusion layer 11 is set deeper than the concentration peak of the N-type drift region 10 so that the concentration decreases toward the SOI substrate surface. The surface concentration of the concentration diffusion layer 11 is set to be equal to or lower than the surface concentration of the N-type drift region 10.

  The difference from the conventional structure shown in FIG. 2B is that the surface concentration of the N-type deep well concentration diffusion layer 11 is set to be higher than that of the N-type drift region 10, but the embodiment of the present invention is the same. The setting is less than or equal to. That is, the surface concentration of the N type deep well concentration diffusion layer 11 is thinner than that of the conventional structure.

  FIG. 3 shows electric field intensity distribution diagrams of the conventional example (a) and the embodiment (b) of the present invention. The electric field intensity distribution of the X-X 'position described in each sectional view of FIGS. In the embodiment of the present invention, when a high breakdown voltage is applied to the drain, the concentration in the vicinity of the surface where the potential distribution is dense is reduced, thereby promoting the extension of the depletion layer in the vicinity of the surface. For this reason, the gradient of the potential distribution at the edge of the deep well region is reduced, the electric field in the vicinity of the surface can be reduced, and the breakdown voltage in the off state can be improved.

  Moreover, about the current capability of embodiment of this invention, the fall by having reduced the density | concentration of the surface vicinity compared with a prior art example is suppressed. This is presumably because the total dose in the drain region has not changed from the conventional one, and the carrier flow is secured. Further, the withstand voltage characteristic in the on state is not different from the conventional example and there is no problem.

  As described above, the embodiment of the present invention is an excellent high withstand voltage semiconductor device that can improve the off withstand voltage and suppress the decrease in current capability.

  In the embodiment of the present invention, the example of the lateral NMOS transistor has been described. However, the present invention is not limited to this, and the drain diffusion layer is reversed in conductivity type and used for a lateral PMOS transistor or a lateral IGBT. Is also okay.

  The high withstand voltage semiconductor device and the manufacturing method thereof according to the present invention can improve the off withstand voltage and suppress the decrease in current capability, and are useful for a high withstand voltage semiconductor device using an SOI substrate.

(A) is a schematic cross-sectional view of a high voltage NMOS transistor according to an embodiment of the present invention, and (b) is a schematic diagram of a concentration profile of the present invention. (A) is a schematic sectional view of a conventional high breakdown voltage NMOS transistor, and (b) is a schematic diagram of a concentration profile of a conventional high breakdown voltage NMOS transistor. It is an electric field intensity distribution figure of a prior art example (a) and embodiment (b) of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Embedded insulating layer 3 P type semiconductor layer 4 P well region 5 N ⁺ type drain region 6 N ⁺ type source region 7 P ⁺ type contact diffusion region 8 Gate insulating film 9 Gate electrode 10 N type drift region 11 N type Deep well concentration diffusion layer 12 Source electrode 13 Drain electrode 14 Field oxide film

Claims (5)

A high withstand voltage semiconductor device formed on an SOI substrate having a semiconductor layer formed on a supporting substrate through a buried insulating film,
A first conductivity type well region formed in the semiconductor layer;
A second conductivity type high-concentration source region selectively formed in the well region;
A second conductivity type high-concentration drain region formed in the semiconductor layer apart from the well region;
A low concentration drift region of a second conductivity type formed in the semiconductor layer from the end of the well region to the drain region side and not reaching the buried insulating film;
A second conductivity type medium concentration deep well region formed in a predetermined region including the drain region;
A gate electrode formed through a gate insulating film between the source region end and the low concentration drift region end;
The high breakdown voltage semiconductor device according to claim 1, wherein a surface concentration of the medium concentration deep well region is set to be equal to or lower than a surface concentration of the low concentration drift region.   2. The high withstand voltage semiconductor device according to claim 1, further comprising a body contact region of a first conductivity type formed in a region different from the source region of the well region.   The high breakdown voltage semiconductor device according to claim 1, wherein the semiconductor layer is of a first conductivity type.   4. The high breakdown voltage semiconductor device according to claim 1, wherein a junction between the medium concentration deep well region and the semiconductor layer is deeper than a junction between the low concentration drift region and the semiconductor layer.   2. The method of manufacturing a high breakdown voltage semiconductor device according to claim 1, comprising a step of forming the intermediate concentration deep well region and the low concentration drift region by implanting impurity ions, respectively. A method of manufacturing a high breakdown voltage semiconductor device, wherein the implantation energy is set higher than the implantation energy of the low concentration drift region.

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