JP2008079041A - Clock adjusting apparatus and clock adjusting method of high-speed serial bus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock adjusting apparatus and a clock adjusting method of a high-speed serial bus which determines the best clocking point during an operation without stopping the operation and also obtains a clock margin. <P>SOLUTION: A clock adjusting portion 100 has a best-point determining means to determine the best point among clock points in a high-speed serial data, a determining point setting means to set one or two or more from among the clocking points to the determining point for determining an effective range to receive the high-speed serial data correctly during the operation, a comparison means to compare input data of the best point with the input data of the deciding point, a point updating means to update the determining point based on the compared results, and a holding means to hold the effective range based on the updated determining point. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock adjustment device and a clock adjustment method for a high-speed serial bus capable of performing high-speed data communication.

  Conventionally, data communication includes a parallel communication method using a plurality of data lines and a serial communication method using a single data line. Among these, in the serial communication system, since the semiconductor manufacturing technology has been miniaturized and the operating frequency has been improved, high-speed transmission can be realized.

  PCI Express, serial ATA, and the like are standards that can realize a transmission rate of 1 Gbps (Bits per second) or more in the serial communication system.

  Incidentally, some high-speed serial buses that transmit data at high speed by a serial communication method include a clock adjusting device that determines a clock point on the data receiving side. The clock adjusting device has a function (calibration) for determining the best point among clock points on the input (transmission) side by outputting a predetermined data pattern.

In addition, the clock adjustment device operates at a single fixed clock point during actual operation. However, the clock point is always fixed for debugging and margin evaluation, and the clock point is moved by register settings. Have had.
JP 2004-46395 A

  However, the conventional clock adjusting device does not review the clock point during the subsequent actual operation when the clock point is determined by performing calibration in the high-speed serial data.

  For this reason, in conventional clock adjustment devices, the best clock point may deviate from the determined clock point due to fluctuation factors such as temperature and voltage fluctuations during operation, silicon aging and data pattern combinations. It was. If the best clock point is deviated, the frequency of data communication errors increases, so it is necessary to perform calibration again to determine the clock point, but for that purpose, the operation of the clock adjustment device had to be stopped. .

  Further, the conventional clock adjusting device cannot grasp how much the clock margin is allowed to fluctuate.

  In this regard, for example, Patent Document 1 discloses a clock adjustment technique, but this technique tunes the delay amount of the clock signal at a predetermined timing, and this technique solves the problem of the present invention. I couldn't.

  Accordingly, the present invention has been made to solve the above-described problems, and can determine the best clock point during operation without stopping the operation, and can also determine the clock margin and can adjust the clock margin of the high-speed serial bus. An object of the present invention is to provide a clock adjustment method.

  In order to solve the above-mentioned problems, the present invention provides a clock adjusting device for adjusting a clock of input data in a high-speed serial bus, comprising: a best point determining means for determining a best point among clock points in input data; 1 or 2 or more of them is set as a decision point for determining an effective range in which input data can be correctly received during operation, and a best point input determined by the best point determination unit Comparing means for comparing the data with the input data of the decision point set by the decision point setting means, point updating means for updating the decision point based on the comparison result by the comparison means, and updating by the point update means Retain effective range based on determined decision points Wherein the clock adjustment apparatus and a stage.

  The present invention is also a clock adjustment method for adjusting a clock of input data in a high-speed serial bus, wherein the best point of clock points in input data is determined, and one or more of the clock points are input. It is set as a decision point for determining an effective range in which data can be correctly received during operation, the input data of the determined best point is compared with the input data of the set decision point, and the comparison result is A clock adjustment method is provided that updates the determination point based on the updated determination point and maintains an effective range based on the updated determination point.

  As described above in detail, according to the present invention, the best clock point during operation can be determined without stopping the operation, and the clock adjustment device and clock adjustment method for a high-speed serial bus capable of grasping the clock margin. Is obtained.

  Embodiments of the present invention will be described below. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a block diagram showing a main configuration of a transmission / reception processing module 300 in which a clock adjustment device according to an embodiment of the present invention is incorporated. The transmission / reception processing module 300 includes a coding module 250 and a media attachment module 260. The transmission / reception processing module 300 is applied to high-speed data communication between an LSI (chip) and a memory.

  The coding module 250 includes a decoder 160, an ELASTIC buffer 190, a CRC unit 200, and a code processing unit 210.

  The decoder 160 receives data output from the clock adjustment unit 100 incorporated in the media attachment module 260, performs decoding processing, and outputs the decoded data to the ELASTIC buffer 190. The ELASTIC buffer 190 outputs the decoded data output from the decoder 160 according to the processing speed of the transmitting device. The CRC 200 adds a CRC code to the decoded data stored in the ELASTIC buffer 190. The code processing unit 210 adds an error code to transmission data (TXDATA) output from the transmission side device, performs encoding processing (encoding processing), and outputs the encoded data to the media attachment module 260.

  The media attachment module 260 includes a clock adjustment unit 100, a reception buffer 110, and a transmission unit 270.

  The clock adjustment unit 100 determines the best clock point (best clock point) during operation by performing clock point adjustment described later during operation on the high-speed serial data input from the reception buffer 110, and determines the determined best clock point. Accordingly, the high-speed serial data input from the reception buffer 110 is converted into parallel data and output.

The reception buffer 110 stores high-speed serial data (RX ₊ , RX ₋ ) output from the reception-side device, and outputs the stored high-speed serial data according to the processing speed of the clock adjustment unit 100. The transmission unit 270 sequentially outputs data (TX ₊ , TX ₋ ) output from the coding module 250.

  Next, the clock adjustment unit 100 will be described with reference to FIG. FIG. 2 is a block diagram illustrating an example of the internal configuration of the clock adjustment unit 100. The clock adjustment unit 100 includes a clock generation unit 120, flip-flops 131, 132, and 133, converters 141, 142, and 143, and comparators 151 and 152. The operation of the clock adjustment unit 100 is controlled by the controller 90 shown in FIG.

  The clock adjusting unit 100 receives the high-speed serial data input from the reception buffer 110 by the flip-flop 132 and outputs it according to the clock CLK2, and converts the high-speed serial data output from the flip-flop 132 into parallel data by the converter 142. The data is converted and output to the decoder 160.

  The clock adjustment unit 100 has a configuration in which flip-flops 131 and 133 and converters 141 and 143 are added to the data processing line including the flip-flop 132 and the converter 142, and further, comparators 151 and 152 are added. have. With these added configurations, the clock point during operation can be adjusted.

  The clock generation unit 120 includes a PLL circuit 121 and a register 122. The PLL circuit 121 generates a clock CLK2 output to the flip-flop 132 and the converter 142, and clocks CLK1 and CLK3 having frequencies different from those of the clock CLK2 and outputs them to the flip-flops 131 and 133 and the converters 141 and 143, respectively. The register 122 stores data such as FP (fail-pass) points and PF (pass-fail) points, which will be described later, detected by the initial calibration, and functions as various storage means (described in detail later). is doing.

  The flip-flops 131 and 133 hold clocks CLK1 and CLK3, respectively, and output high-speed serial data input from the reception buffer 110 according to the clocks CLK1 and CLK3. Converters 141 and 143 convert the high-speed serial data output from flip-flops 131 and 133, respectively, into parallel data and output the parallel data.

  The comparator 151 compares the parallel data converted by the converters 141 and 142, and outputs the comparison result to the register 122. The comparator 152 is converted by the converters 142 and 143, compares the parallel data output from each, and outputs the comparison result to the register 122.

  FIG. 3 is a diagram schematically showing the internal configuration of the register 122. A plurality of register units 1220 are provided in the register 122 according to the bit width of the parallel data (n + 1 from 0 to n in the figure). The register 122 includes an automatic setting register 1230, an all shift register 1231, and a narrowest point register 1232.

  Each register unit 1220 has an initial FP register 12200, an initial PF register 12201, and an initial CCP register 12202, as shown in FIG. Further, each register unit 1220 includes an automatic detection FP register 12203, an automatic detection PF register 12204, and a CCP setting register 12205.

  The initial FP register 12200 is a register that reads an FP point detected by the initial calibration. The initial PF register 12201 is a register for reading out the PF point detected by the initial calibration.

  The initial CCP register 12202 is a register for reading a center clock point (referred to as CCP, which will be described later in detail) set in the initial calibration. The initial CCP register 12202 is read-only. When the CCP is shifted, the value of the initial CCP register 12202 is changed at a safe timing by writing to the CCP setting register 12205.

  The automatic detection FP register 12203 stores FP points detected during operation, and has a function as a determination point storage unit. The value of the automatic detection FP register 12203 indicates the current FP point when the FP point is moved during the operation. In addition, the automatic detection FP register 12203 can be set so that the value is changed only when the FP point moves in the reduction direction of the effective range described later. By doing so, it is possible to read from the automatic detection FP register 12203 the results of FP points with the narrowest effective range during operation.

  The automatic detection PF register 12204 stores PF points detected during operation, and has a function as a determination point storage unit. The value of the automatic detection PF register 12204 indicates the current PF point when the PF point is moved during operation. The automatic detection PF register 12204 can be set so that the value is changed only when the PF point moves in the reduction direction of the effective range. By doing in this way, it is possible to read from the automatic detection PF register 12204 the record of the PF point with the narrowest effective range during operation.

  The CCP setting register 12205 is read and written when the CCP is changed during operation. The CCP setting register 12205 is updated when the high-speed serial data is interrupted.

  In the automatic setting register 1230, data (automatic change availability data) indicating whether or not the best point is changed during operation is set by the controller 90 as setting means. The controller 90 sets automatic change permission / inhibition data in accordance with a user instruction. If data indicating that automatic change is possible is set in the automatic setting register 1230, the controller 90 performs a decision point update process and changes the best point during operation.

  The all shift register 1231 is a shift value storage means, and data (shift data) is set in the (n + 1) bit parallel data to shift the CCPs simultaneously in the plus or minus direction. If shift data is set here, the controller 90 as a shift means shifts each bit of the parallel data based on the set shift data. The narrowest point register 1232 is set with the FP point and the PF point when the effective range during operation is the narrowest.

  Here, FIG. 4 is a diagram showing an example of an eye pattern of high-speed serial data (also referred to as a clock point range in which high-speed serial data can be correctly received during operation, also referred to as an effective range) together with the FP point and the PF point. In the present embodiment, it is assumed that a plurality of clock points can be arbitrarily set in one cycle of high-speed serial data. In FIG. 4, 15 clock points are set from 1 to 15 in one cycle, but a number of clock points different from 15 may be set.

  FIG. 4 shows a point where the clock point indicated by “4” is switched from Fail (an area with a possibility of error) to Pass (an area with no possibility of an error), which is an FP point. In addition, the clock point indicated by “12” indicates a point at which the clock is switched from Pass to Fail, and this is the PF point. The FP point and the PF point are decision points for determining an effective range that varies during actual operation.

  Since the intermediate point between the FP point and the PF point has the same margin to the FP point and the PF point and is the best clock point for correctly receiving high-speed serial data, this is the center clock point (also called CCP) in this embodiment. Say).

  Next, FIG. 5 is a flowchart showing an operation procedure of a decision point update process for automatically updating the automatic detection FP register 12203 and the automatic detection PF register 12204 during operation.

  This flowchart is executed in accordance with the control of the controller 90. For convenience of illustration, an operation procedure when the FP code described later is "1" and an operation procedure when "0" is shown is shown as one figure. ing.

  FIG. 5 shows the case where the FP code is set to “1” in step 1 described below and the FP point is searched. However, when searching for the PF point, the process proceeds from step 2 to step 9. ing. The search for the FP point and the search for the PF point are switched under the control of the controller 90.

  Then, the determination point update process is started when the first calibration is completed. After the start of processing, the process proceeds to step 1 where the index data i indicating the processing target register unit among the n + 1 register units is set to “0”, and the initial detection FP register 12200 is set in the automatic detection FP register 12203 for the register unit 1220. The initial PF register 12201 is set in the automatic detection PF register 12204. Further, data is transmitted in either of two search modes (search mode for searching for FP points based on the comparison result of parallel data by the comparator 151 and search mode for searching for PF points based on the comparison result of the parallel data by the comparator 152). “1” is set in the FP code indicating whether or not the comparison is performed.

  Next, the process proceeds to step 2, and it is determined whether or not the FP point search is performed. In that case, the process proceeds to step 3, and otherwise (when the PF point search is performed), the process proceeds to step 9.

  When the process proceeds to step 3, the process waits until the parallel data preparation is completed, and in step 4, when the FP code is “1” for the first comparison data (data 1) (in search mode 1). When the parallel data of the converter 141 is set, otherwise (search mode 2), the parallel data of the converter 143 is set. Further, the parallel data of the converter 142 is set in the second comparison data (data2).

  In the subsequent step 5, it is determined whether or not data1 and data2 match. If they match, the process proceeds to step 6. If not, step 10 is executed and the process returns to step 3.

  In step 6, it is determined whether or not the index data i exceeds a threshold value (a value corresponding to the bit width is set). If it exceeds, the process proceeds to step 8; otherwise, the process proceeds to step 7. . In step 7, “1” is added to the index data i. Thereafter, the processing returns to step 3 and the above processing is repeated.

  In step 8, when the FP code is “1” (in the search mode 1), the controller 90 as the reading means reads the PF point set in the automatic detection PF register 12204, and the PF point is moved back by one. The shifted clock point is set in the automatic detection PF register 12204.

  In other cases (search mode 2), the FP point set in the automatic detection FP register 12203 is read, and the clock point obtained by shifting the FP point to the previous position is set in the automatic detection FP register 12203. Further, “0” is set in the index data i. Thereafter, the process returns to step 3.

  In this way, the clock adjustment unit 100 executes Step 8 when it is confirmed that data1 and data2 match for all the bits and high-speed serial data can be received correctly. The clock adjustment unit 100 executes step 8 so that the controller 90 as the point update means updates the FP point and the PF point, and extends the range (effective range) in which high-speed serial data can be received correctly.

  Then, when the processing proceeds from step 2 to step 9, “0” is set in the FP code and the search mode is changed to search mode 2.

  In step 10, when the FP code is “1” (in the search mode 1), the PF point set in the automatic detection PF register 12204 is read, and the clock point obtained by shifting the PF point to the previous one is obtained. It is set in the automatic detection PF register 12204.

  In other cases (search mode 2), the FP point set in the automatic detection FP register 12203 is read, and a clock point shifted by one FP point is set in the automatic detection FP register 12203.

  Thus, when data1 and data2 contain mismatched bits and it is confirmed that high-speed serial data cannot be received correctly, step 10 is executed, and the FP point and the PF point are updated by the controller 90 as a point update means. The effective range has been reduced. Thereafter, the process returns to step 3.

  As described above, in this determination point update process, steps 3 to 7 are repeated to search for a mismatch point where data1 deviates from data2 before the index data i exceeds the threshold value.

  Then, when the index data i exceeds the threshold without finding a mismatch point, step 8 is executed to update the automatic detection FP register 12203 and the automatic detection FP register 12204 in a direction in which the effective range is expanded.

  When data1 and data2 do not match, step 10 is executed to update the automatic detection FP register 12203 and the automatic detection FP register 12204 in the direction in which the effective range is reduced.

  As described above, in the clock adjustment unit 100, the controller 90 operates as an updating unit, and updates the automatic detection FP register 12203 and the automatic detection PF register 12204 based on the comparison results of the comparators 151 and 152 (steps 8 and 10). By performing this update, the controller 90 as the holding means holds the effective range.

  Here, FIG. 6 is a diagram schematically showing changes in the range of eye patterns when high-speed serial data is received. For example, when the clock point is determined by the initial calibration, it is assumed that the range from the clock point “4” to “12” is an effective range as indicated by the line indicated by “A”.

  However, during actual operation, the effective range (eye pattern) as shown by the lines indicated by “B1”, “B2”, and “B3” according to changes in temperature and voltage, aging of silicon, and combinations of data patterns. Often shifts. Here, the line indicated by “B1” indicates a case where the time axis is shifted backward, the line indicated by “B2” indicates the case where the time axis is shifted forward, and is indicated by “B3”. These lines show a case where the time range is shifted forward and the effective range is slightly narrowed.

  When each of the lines indicated by “B1”, “B2”, and “B3” is used, the CCP set for the first time can effectively receive high-speed serial data, but the range of clocks allowed to fluctuate (clock margin) Therefore, if the effective range deviates more than shown, a reception error may occur.

  On the other hand, in any case of each line indicated by “B1”, “B2”, and “B3”, the effective range is only shifted forward or backward with respect to the time axis. Therefore, when the above update process is performed during actual operation and the FP point and the PF point are constantly updated, the controller 90 as the calculation means calculates an intermediate value based on the updated FP point and the PF point, and creates a new value. CCP (new CCP) can be determined.

  Then, since the new CCP becomes the best point reflecting the fluctuation during the actual operation, the controller 90 as the best point changing means can change the CCP to the new CCP, so that the clock margin can always be secured. High-speed serial data can be stably received without errors. In addition, it is possible to grasp how much clock margin is present from the FP point, the PF point, and the CCP.

(Modification)
FIG. 7 is a block diagram illustrating an example of the internal configuration of another clock adjustment unit 101. The clock adjustment unit 101 is configured by providing a single clock output system from the clock generation unit 120 and providing a plurality of delay elements 170 instead of providing a plurality of output systems.

  In the clock adjustment unit 101, the high-speed serial data input from the reception buffer 110 is inserted with data delays by a plurality of delay elements 170, and the data with arbitrary delay data inserted is flip-flops 131 and 132 according to CLK1. , 133 are configured to output. The register 122 is independent of the clock generation unit 120 (however, although it may be provided in the clock generation unit 120 due to the structure), the register 122 selects which data is selected from the high-speed serial data into which the delay data is inserted. Determine.

  In this clock adjustment unit 101, the clock is limited to one system, and it is not necessary to provide a plurality of clocks unlike the clock adjustment unit 100. Therefore, manufacture is easier than the clock adjustment unit 100.

  Note that the clock adjustment unit 100 may maintain the effective range by not updating one of the FP point and the PF point and updating only the other.

  Further, the controller 90 can be operated as a reset means for resetting the register 122. Thus, the FP point set in the register 122 can be taken again.

  The above description is the description of the embodiment of the present invention, and does not limit the apparatus and method of the present invention, and various modifications can be easily implemented. In addition, an apparatus or method configured by appropriately combining components, functions, features, or method steps in each embodiment is also included in the present invention.

It is a block diagram which shows the main structures of the transmission / reception processing module in which the clock adjustment apparatus which concerns on embodiment of this invention was integrated. It is a block diagram which shows an example of an internal structure of a clock adjustment part. It is the figure which showed the internal structure of the register typically. It is a figure which shows an example of the eye pattern of high-speed serial data with FP point and PF point. It is a flowchart which shows the operation | movement procedure of the point update process for determination. It is the figure which showed typically the change of the range of the eye pattern at the time of high-speed serial data reception. It is a block which shows an example of an internal structure of another high-speed serial bus adjustment part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 90 ... Controller, 100, 101 ... Clock adjustment part 120 ... Clock generation part, 122 ... Register 151, 152 ... Comparator, 1220 ... Register unit 1230 ... Automatic setting register, 1231 ... All shift register 1232 ... Narrowest point register, 12200 ... Initial FP register 12201 ... Initial PF register, 12202 ... Initial CCP register 12203 ... Automatic detection FP register, 12204 ... Automatic detection PF register 12205 ... CCP setting register

Claims (8)

A clock adjustment device for adjusting a clock of input data in a high-speed serial bus,
A best point determining means for determining a best point among clock points in the input data;
Decision point setting means for setting one or more of the clock points to a decision point for determining an effective range in which the input data can be correctly received during operation;
A comparison means for comparing the input data of the best point determined by the best point determination means with the input data of the determination point set by the determination point setting means;
Point update means for updating the determination point based on the comparison result by the comparison means;
A clock adjusting apparatus comprising: holding means for holding the effective range based on the determination point updated by the point update means. Calculating means for calculating a center value of the effective range;
2. The clock adjusting apparatus according to claim 1, further comprising: best point changing means for changing the best point determined by the best point determining means during operation based on a calculation result of the calculating means. Storage means for storing the determination points set by the determination point setting means;
3. The clock adjusting apparatus according to claim 1, further comprising reading means for reading out the determination point stored in the storage means.   4. The clock adjustment device according to claim 1, further comprising setting means for setting whether or not the best point is changed during operation by the best point changing means. The input data is composed of multiple bits,
A shift value storing means for storing a shift value for shifting each bit of the input data;
The clock adjustment device according to any one of claims 1 to 4, wherein the best point is shifted in accordance with the shift value stored in the shift value storage means. The update means is configured to update the determination point in a direction to narrow the effective range, and not to update the determination point in a direction to widen the effective range,
6. The clock adjustment apparatus according to claim 1, further comprising a narrowest point storage unit that stores the determination point when the effective range is the narrowest as the narrowest point.   7. The clock adjusting apparatus according to claim 6, further comprising reset means for resetting the narrowest point storage means. A clock adjustment method for adjusting a clock of input data in a high-speed serial bus,
Determining the best of the clock points in the input data;
One or more of the clock points are set as decision points for determining an effective range in which the input data can be correctly received during operation,
Comparing the input data of the determined best point with the input data of the set decision point;
Updating the decision point based on the comparison result;
A clock adjustment method, wherein the effective range is held based on the updated determination point.

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