JP2007215300A - Power supply - Google Patents

Abstract

A power supply device capable of sufficiently suppressing inrush current is provided.
An output transistor having a main conductive path connected between a DC voltage source and a smoothing capacitor, the conductivity of which varies depending on a voltage supplied to a control electrode, a control circuit for outputting a control signal for power on / off, An output voltage detection unit that detects a change in the charging voltage when the smoothing capacitor is charged and outputs a detection signal when the charging voltage becomes close to the input voltage supplied from the DC voltage source, and a control for power on / off The voltage of the control electrode of the output transistor is controlled stepwise in response to the signal and the detection signal, the output transistor is controlled to an intermediate continuity by the control signal instructing to turn on the power, and the continuity of the output transistor is controlled by the detection signal And a bias circuit that controls to further increase the frequency.
[Selection] Figure 1

Description

  The present invention relates to a power supply apparatus including an inrush current suppressing circuit that suppresses an inrush current during an initial operation of a power supply.

  In general, various electric circuits are operated by being supplied with a predetermined power supply voltage. However, an excessive current may flow during an initial operation when the power is turned on. This excessive current is called inrush current, and the overcurrent protection function of the supply source power supply may shut down, cause a voltage drop, and may damage the integrated circuit and other components constituting the electric circuit.

  In order to suppress such inrush current, Patent Document 1 discloses an output transistor that supplies current from a power supply to an output terminal, a differential amplifier that controls current supply of the output transistor based on a reference voltage, and an initial operation of the power supply circuit. A power supply circuit is described that includes inrush current suppression means that sometimes gradually increase the amount of current supplied to the output transistor.

  However, the inrush current suppression means of Patent Document 1 is a method of charging a capacitor via a charging switch and gradually discharging the capacitor to control the gate potential of the suppression transistor. It can only be used in situations where the capacitor is being charged. Also, the voltage between the gate and source of the FET constituting the output transistor (VGS) is gradually increased when the power is turned on to gradually control the on-resistance of the FET, but the on-resistance is not gradually reduced, Since the FET rises suddenly, it is difficult to control.

On the other hand, in general, there is a method of delaying the rise of an FET to which a low resistance is connected by connecting a low resistance in parallel to one of the FETs in a two-stage configuration. 2 had to be used, resulting in a high cost.
JP 2000-89840 A

  Since the power supply circuit of Patent Document 1 is a method of controlling the suppression transistor using the discharge of the capacitor, there is a problem that it cannot be used unless the capacitor is originally charged by some power supply. In addition, there is a method of delaying the rise of one of the FETs with a two-stage configuration, but there is a problem that the cost increases.

  An object of this invention is to provide the power supply device which can fully suppress an inrush current in view of the said situation.

  According to a first aspect of the present invention, there is provided a power supply device comprising: a main conductive path connected between a DC voltage source and a smoothing capacitor; an output transistor whose conductivity varies depending on a voltage supplied to a control electrode; When the smoothing capacitor is charged via the output transistor through a control circuit that outputs a signal, a change in the charging voltage is detected, and when the charging voltage becomes close to the input voltage supplied from the DC voltage source An output voltage detection unit for outputting a detection signal, the control signal for power on / off, and the control signal for controlling the voltage of the control electrode of the output transistor stepwise in response to the detection signal and instructing power on To control the output transistor to an intermediate conductivity, and to further increase the conductivity of the output transistor according to the detection signal. Characterized by comprising a circuit.

  According to the present invention, the inrush current can be surely suppressed by controlling the output transistor step by step when the power is turned on and switching the on-resistance from the high resistance state to the low resistance state.

[Example 1]
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a power supply circuit of the present invention, and FIG. 2 is a waveform diagram for explaining operations.

  First, the circuit configuration of FIG. 1 will be described. Reference numeral 11 denotes a DC voltage source that supplies the input voltage Vin, for example, a 24V DC power source. The input voltage Vin from the DC voltage source 11 is supplied to the smoothing capacitor 13 via the source / drain (main conductive path) of the P-channel FET 12 which is an output transistor, and an output voltage Vout is obtained at the output terminal 14. A load 15 that is operated by the output voltage Vout is connected to the output terminal 14.

  Reference numeral 16 denotes a control circuit such as a CPU, which outputs a control signal S1 for controlling on / off of power supply to the load 15. The on / off control signal S1 is supplied to the base of the transistor Q1. The collector of the transistor Q1 is connected to the DC voltage source 11 via a resistor R1, and the emitter is connected to a reference potential point (ground).

  The collector of the transistor Q1 is connected to the base of the transistor Q2, and the emitter of the transistor Q2 is connected to the reference potential point. The collector of the transistor Q2 is connected to the base of the transistor Q3.

  A voltage dividing circuit in which a Zener diode ZD1 and resistors R4 and R5 are connected in series is connected between the DC voltage source 11 and a reference potential point, and a voltage dividing circuit including resistors R2 and R3 is connected in parallel with the Zener diode ZD1. Yes. The emitter and collector of the transistor Q3 are connected in parallel to the resistor R2, and the connection point between the resistors R2 and R3 is connected to the gate (control electrode) of the output transistor 12 via the resistor R7.

  The connection point between the resistors R4 and R5 is connected to the inverting input terminal (−) of the comparator 17, the non-inverting input terminal (+) of the comparator 17 is connected to the first reference voltage source 19, and its output terminal is the transistor Q5. Connected to the base. The transistor Q5 has an emitter connected to the reference potential point, a base connected to the DC voltage source 11 via the resistor R11, and a collector connected to the base of the transistor Q3.

  Further, a series circuit of a Zener diode ZD2 and a resistor R8 is connected in parallel with the smoothing capacitor 13, and the connection point of the Zener diode ZD2 and the resistor R8 is a non-inverting input of the comparator 18 through a parallel circuit of the diode D1 and the resistor R9. Connected to terminal (+). The non-inverting input terminal (+) of the comparator 18 is connected to the reference potential point via the capacitor C1, the inverting input terminal (−) is connected to the second reference voltage source 20, and the output terminal is connected to the control circuit 16. To supply the signal S2.

  Further, the output of the comparator 18 is connected to the base of the transistor Q4, and the base of the transistor Q4 is further connected to the voltage source Vcc via the resistor R10. The collector-emitter current path of the transistor Q4 is connected between the voltage dividing points of the resistors R2 and R3 and the reference potential point.

  The transistors Q2, Q3, Q4, and Q5 and the resistors R2, R3, and R6 constitute a bias circuit that controls the voltage of the gate electrode of the output transistor 12, and the comparator 17 detects a change in the input voltage Vin to detect the transistor Q5. , Q3 are controlled. The comparator 18 detects a change in the output voltage Vout and controls the transistor Q4.

  Next, the operation of the power supply apparatus of the present invention will be described with reference to the waveform diagram of FIG. 2A shows the waveform of the input voltage Vin supplied from the DC voltage source 11, FIG. 2B shows the output waveform of the comparator 17, and FIG. 2C shows the ON / OFF control signal S1 from the control circuit 16. Waveform is shown. Further, (d) shows the gate-source voltage Vgs of the output transistor 12, (e) shows the waveform of the + terminal of the comparator 18, and (f) shows the waveform of the output signal S2 of the comparator 18. Further, (g) shows the voltage waveform Vout of the output terminal 14, and (h) shows the current waveform of the output terminal 14. Further, Vref2 in the waveform (e) indicates the reference voltage level of the comparator 18.

  First, when the DC power supply is activated, the input voltage Vin (24V) is supplied from the DC voltage source 11 as shown in FIG. As a result, a voltage is supplied to the base of the transistor Q2 via the resistor R1, Q2 is forcibly turned on, and the transistor Q3 is also turned on. For this reason, the resistor R2 is short-circuited by the transistor Q3, and the potential difference between the gate and source of the FET 12 is eliminated. As a result, the FET 12 is turned off, exhibits a low on-resistance and is turned off, and the power supply remains cut off.

  Next, the control circuit (CPU) 16 starts operating, and the on / off signal S1 shown in (c) is set to the high level H in order to supply 24V to the load side. The transistor Q1 is turned on by the high level signal S1, and the transistors Q2 and Q3 are turned off. As a result, the gate-source voltage Vgs of the FET 12 becomes a value (Vgs1) obtained by dividing the Zener voltage of the Zener diode ZD1 by the resistors R2 and R3 as shown in (d).

  This value Vgs1 is a value at which the FET 12 operates in the non-saturated region, and the on-resistance becomes high. As a result, the FET 12 starts to flow current to the output terminal 14 little by little. The flowing current is charged in the smoothing capacitor 13 on the load side relatively slowly. As a result, the voltage of the smoothing capacitor 13 gradually increases as indicated by (g).

  When the voltage of the smoothing capacitor 13 exceeds the Zener voltage of the Zener diode ZD2, a current flows through the resistor R8, and the capacitor C1 is charged through the resistor R9 by the voltage across the resistor R8 as shown by (e). Is done. When the charge voltage of the capacitor C1 exceeds the reference voltage Vref2 of the comparator 18, the output of the comparator 18 changes from low to high as shown by (f), the transistor Q4 is turned on, the resistor R6 is pulled down, and the FET 12 The gate-source voltage Vgs becomes a potential difference (Vgs2) for saturating the FET 12, and the FET 12 is completely turned on.

  On the other hand, the smoothing capacitor 13 continues to be charged from the time when it is clamped by the Zener diode ZD2 until the output of the comparator 18 is inverted, and approaches 24V as much as possible. In other words, the time constant R9 · C1 of the resistor R9 and the capacitor C1 delays the generation of the signal S2 at the output terminal of the comparator 18, and then the FET 12 is completely turned on. .

  Inrush current is likely to occur during charging of the smoothing capacitor 13, but according to the embodiment of FIG. 1, the on-resistance of the FET 12 is increased during charging of the smoothing capacitor 13, and the voltage of the smoothing capacitor 13 is close to the power supply voltage. Since the FET 12 is completely turned on after waiting for this, the inrush current can be made substantially zero.

  Further, the output signal S2 of the comparator 18 becomes a signal indicating that the charging of the smoothing capacitor 13 is completed, and the control circuit 16 can control the load 15 using this as a trigger.

  Further, when the input voltage Vin becomes abnormally low, the comparator 17 outputs a signal of a high level H (broken line in FIG. 2B) to its output terminal to turn on the transistors Q5 and Q3. The FET 12 is turned off. That is, if the specified voltage that does not affect the subsequent stage even if the input voltage is reduced is Von and the lower limit value of the reference voltage Vref1 is Vmin, the input voltage can be reduced by setting the lower limit value Vmin> the specified voltage Von. When the voltage of Vin becomes abnormally low, the output terminal of the comparator 17 becomes high level, the transistors Q5 and Q3 are turned on, the FET 12 can be turned off, and heat generation and ignition can be prevented.

  In the configuration of FIG. 1, the same operation is performed when the power supply is controlled by turning on / off the DC voltage source 11 with the on / off control signal S1 held at a high level. That is, even if the supply of the DC voltage source 11 is controlled by an element such as an interlock switch or a relay, an inrush current can be prevented.

  Further, the Zener diode ZD1 has an effect of preventing the Vgs of the FET 12 from varying even if the input voltage Vin varies to some extent. The resistors R4 and R5 are detected when the comparator 17 detects the input voltage Vin. There is a role to adjust to an easy level. The resistor R8 is adjusted so as to suppress the Zener current of the Zener diode ZD2 within a certain range, and the diode D1 has a role of quickly discharging the charge of the capacitor C1, speeding up the response of the circuit, and preventing malfunction.

  When the control signal S1 is not output even when the DC power supply Vin is turned on, the FET 12 is turned off. When the power supply voltage is abnormally low, the FET 12 is turned off by the output of the comparator 17.

  As described above, in the present invention, the inrush current can be reliably suppressed by delaying the two-stage on control for sequentially switching the FET 12 from the high on-resistance state to the low on-resistance state when the power is turned on and the charging voltage detection. Further, since only one high-current FET is used, cost reduction can be expected.

  The embodiment of the present invention is not limited to the above-described example, and other modifications can be made without departing from the scope of the claims.

The circuit diagram which shows one Embodiment of the power supply device of this invention. The wave form diagram which shows the signal waveform of each part for demonstrating operation | movement of the embodiment.

Explanation of symbols

11 ... DC voltage source 12 ... Output transistor (FET)
DESCRIPTION OF SYMBOLS 13 ... Smoothing capacitor 14 ... Output terminal 15 ... Load 16 ... Control circuit 17, 18 ... Comparator 19, 20 ... Reference voltage source Q1-Q5 ... Transistor ZD1, ZD2 ... Zener diode R9, C1 ... Time constant circuit

Claims (7)

An output transistor in which the main conductive path is connected between the DC voltage source and the smoothing capacitor, and the conductivity changes according to the voltage supplied to the control electrode;
A control circuit for outputting a control signal for power on / off;
Output voltage detection that detects a change in charging voltage when the smoothing capacitor is charged via the output transistor, and outputs a detection signal when the charging voltage is close to the input voltage supplied from the DC voltage source And
In response to the control signal for power on / off and the detection signal, the voltage of the control electrode of the output transistor is controlled in stages, and the output transistor is set to an intermediate conductivity by the control signal instructing power on. A bias circuit that controls and controls to further increase the conductivity of the output transistor according to the detection signal;
A power supply device comprising:   The power supply apparatus according to claim 1, wherein the output transistor is an FET.   2. The power supply device according to claim 1, wherein the bias circuit turns off the output transistor when the control signal for power on / off is not output even when an input voltage is supplied from the DC voltage source.   The output voltage detection unit includes a first Zener diode that conducts when the voltage of the smoothing capacitor exceeds a predetermined level, a capacitor that is charged with a predetermined time constant via the first Zener diode, 2. A first comparator that compares a voltage of a capacitor with a first reference voltage having a predetermined voltage value, and the detection signal is obtained at an output terminal of the first comparator. Power supply. The bias circuit divides an input voltage supplied from the DC voltage source and supplies the divided voltage to the control electrode of the output transistor, and between the voltage dividing point of the voltage dividing circuit and the DC voltage source A first transistor connected; and a second transistor connected between a control electrode of the output transistor and a reference potential point;
When the power is turned on, the first transistor is turned on by the input voltage, the first transistor is turned off by the control signal instructing to turn on the power, and the first transistor is turned on by a detection signal from the output voltage detector. 2. The power supply device according to claim 1, wherein the transistor is turned on. Furthermore, an input voltage detector that detects an input voltage supplied from the DC voltage source and outputs a detection signal when the input voltage drops below a predetermined level,
2. The power supply device according to claim 1, wherein the output transistor is turned off by a detection signal from the input voltage detection unit.   The input voltage detection unit compares a first voltage obtained by dividing the input voltage with a voltage dividing circuit including a second Zener diode and a second reference voltage having a predetermined voltage value. 7. The power supply apparatus according to claim 6, wherein a detection signal is obtained from an output terminal of the comparator.

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