JP2007250960A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device constituted of a plurality of semiconductor chips, for which an operation speed is accelerated. <P>SOLUTION: Three semiconductor chips 1, 3 and 5 are mounted on the main surface 10x of a wiring board 10. A plurality of electrode pads 2a for signals arranged along the first side 1a of the semiconductor chip 1 are disposed by holding the electrode pad 2b of other functions therebetween so as not to be adjacent to each other. The plurality of electrode pads 2a for the signals are arranged at an array pitch wider than the plurality of electrode pads 2 including them. As the electrode pad 2b, an electrode pad is used for power supply. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a plurality of semiconductor chips are mounted on a wiring board.

  As a semiconductor device, for example, a semiconductor device called a SiP (System in Package) type is known. In a SiP type semiconductor device, a plurality of semiconductor chips having different functions are mounted on a wiring board to construct one circuit system. As for the SiP type semiconductor device, devices having various structures have been proposed and commercialized. For example, in Japanese Patent Laid-Open No. 2003-204030, a semiconductor chip on which a logic operation circuit is mounted and a semiconductor chip on which a DRAM (Dynamic Random Access Memory) is mounted on a wiring board are planar. In particular, a SiP type semiconductor device mounted in parallel is disclosed. Japanese Patent Application Laid-Open No. 2004-228323 discloses a SiP type semiconductor device in which a semiconductor chip on which a logic operation circuit is mounted and a semiconductor chip on which a DRAM is mounted are three-dimensionally stacked and mounted on a wiring board. ing.

JP 2003-204030 A JP 2004-228323 A

As a result of examining the SiP type semiconductor device, the present inventor has found the following problems.
8 to 10 are diagrams related to a conventional SiP type semiconductor device.
FIG. 8 is a schematic plan view showing a connection state between semiconductor chips,
FIG. 9 is a diagram showing the internal structure of the wiring board ((a) is a schematic perspective view, (b) is a schematic cross-sectional view),
FIG. 10 is a schematic perspective view for explaining the return current.

8 to 10,
Reference numeral 41 denotes a semiconductor chip (logic chip) on which a logic operation circuit is mounted,
Reference numeral 41a denotes a first side,
Reference numeral 42 denotes a signal electrode pad disposed on the main surface of the logic chip 41;
Reference numeral 43 denotes a semiconductor chip (DRAM chip) on which a DRAM circuit is mounted,
Reference numeral 43a denotes a first side,
Reference numeral 44 denotes a signal electrode pad disposed on the main surface of the DRAM chip 43;
Reference numeral 50 denotes a wiring board,
Reference numeral 51 denotes a signal wiring formed on the first conductive layer (wiring layer) of the wiring board 50;
Reference numerals 51a and 51b denote GND wirings formed in the first conductive layer of the wiring board 50,
Reference numeral 52 denotes a GND plane formed in the second conductive layer (wiring layer) of the wiring board 50;
Reference numeral 52a denotes a through hole formed in the GND plane 52.
Reference numeral 53 denotes a signal wiring formed on the third conductive layer (wiring layer) of the wiring board 50;
Reference numeral 54 denotes a through-hole wiring (via) for electrically connecting the signal wiring 51 and the signal wiring 53 through the through hole 52a.
Reference numeral 55a denotes a through-hole wiring (via) that electrically connects the GND wiring 51a and the GND plane 52;
Reference numeral 55b denotes a through-hole wiring (via) that electrically connects the GND wiring 51b and the GND plane 52.

In FIG. 8, the electrode pads of each semiconductor chip are shown through.
(1) As shown in FIG. 8, in the logic chip 41 and the DRAM chip 43, the first sides (41 a, 43 a) face each other, and the respective main surfaces face the main surface of the wiring substrate 50. In this state, it is mounted on the main surface of the wiring board 50.

  On the main surface of the DRAM chip 43, a plurality of signal electrode pads 44 are arranged adjacent to each other along the first side 43a. On the main surface of the logic chip 41, a plurality of signal electrode pads 42 electrically connected to the plurality of signal electrode pads 44 of the DRAM chip 43 are adjacent to each other along the first side 41a. Is arranged. Electrical connection between the plurality of signal electrode pads 44 of the DRAM chip 43 and the plurality of signal electrode pads 42 of the logic chip 41 is formed in the first conductive layer (wiring layer) of the wiring substrate 50. The plurality of signal lines 51 are used.

  In the SiP type semiconductor device, the existing DRAM chip 43 is used in order to reduce the cost, and the logic chip 41 is newly designed according to the application. In the design of the logic chip 41, in order to shorten the signal transmission path in the wiring substrate 50, the logic chip 41 is electrically connected to the plurality of signal electrode pads 44 arranged along the first side 43a of the DRAM chip 43. A plurality of signal electrode pads 42 are arranged along the first side 41 a of the logic chip 41.

  However, the pad arrangement pitch of the logic chip 41 is narrower than the pad arrangement pitch of the DRAM chip 43, and the plurality of signal electrode pads 42 of the logic chip 41 are arranged adjacent to each other. Yes. In the case of the logic chip 41, the signal processing is controlled as an interface between the mounting board and the DRAM chip 43, and therefore, in addition to the plurality of signal electrode pads 42 electrically connected to the DRAM chip, the mounting board A plurality of electrode pads electrically connected to each other. As a result, the number of electrode pads of the logic chip 41 is larger than that of the DRAM chip 43, and therefore, the pad arrangement pitch is arranged narrower than that of the DRAM chip. Therefore, a plurality of signal wirings 51 that electrically connect the plurality of signal electrode pads 42 of the DRAM chip 43 and the plurality of signal electrode pads 42 of the logic chip 41 are provided from the logic chip 41 side. A plurality of signal electrode pads 42 of the DRAM chip 43 and a plurality of signal electrode pads 42 of the logic chip 41 are electrically connected to each other, spreading in a fan shape (radially) toward the DRAM chip 43 side. It is difficult to ensure the equal length of the signal wiring 51. Since the equal length of the signal wiring 51 affects the operation speed of the semiconductor device, it is necessary to ensure the equal length of the signal wiring 51 as much as possible.

(2) When two DRAM chips 43 are mounted, the plurality of signal electrode pads 42 of the logic chip 41 are electrically connected to the plurality of signal electrode pads of other DRAM chips, respectively. As shown in FIG. 9B, the third DRAM signal wiring 53 of the wiring substrate 50 and the signal wiring 53 and the first layer signal are electrically connected to other DRAM chips. This is performed using a through-hole wiring 54 for electrically connecting the wiring 51 for use. In the second conductive layer (wiring layer) of the wiring board 50, in order to suppress interference between a signal flowing through the first signal wiring 51 and a signal flowing through the third signal wiring 53. A GND plane 52 is formed. As shown in FIGS. 9A and 9B, the GND plane 52 is formed with a through hole 52a through which the through hole wiring 54 passes, and the through hole wiring passing through the through hole 52a. 54, the upper signal wiring 51 and the lower signal wiring 53 are electrically connected.

  The through-hole wiring 54 is arranged close to the logic chip 41 side in order to ensure the equal length of the signal wiring to the DRAM chip 43 and other DRAM chips. Since the signal electrode pads 42 of the logic chip 41 are arranged at a narrower arrangement pitch than the signal electrode pads 44 of the DRAM chip 43, the arrangement pitch of the plurality of signal wirings 51 is narrower on the logic chip side. It has become. For this reason, although the through-hole 52a is originally formed independently for every through-hole wiring 54, as shown to FIG. 9 ((a), (b)), several through-holes 52a will be connected and it will penetrate. The GND plane 52 does not exist between the holes 52a.

  On the other hand, the electrical signal output from the signal electrode pad 42 of the logic chip 41 is transmitted to the signal electrode pad 44 of the DRAM chip 43 through the signal wiring 51 as shown in FIG. At this time, if an electric signal flows only in one direction, noise is likely to occur in the electric signal path. Therefore, in order to suppress such noise, it is possible to cancel a noise source that is likely to occur in the electric signal path by flowing a return current that feeds back the electric signal in the reverse direction at the same timing. The return current flows from the GND electrode pad of the DRAM chip 43 to the GND of the logic chip 41 through the GND wiring 51a, the through-hole wiring 55a, the GND plane 52, the through-hole wiring 55b, and the GND wiring 51b. Flows to the electrode pad.

  When a plurality of through holes 52a connected to each other are arranged in the current path through which the return current flows so as to cross the direction in which the return current flows, the return current flows by bypassing these through holes. As a result, the return current cannot be returned, causing noise. Since this causes a decrease in the reliability of the semiconductor device, it is necessary to devise a method for preventing the plurality of through holes 52a from being connected even if the number of wirings increases with the increase in functionality and multifunction. .

An object of the present invention is to provide a technique capable of increasing the operating speed of a semiconductor device.
Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

(1);
A wiring board;
First and second semiconductor chips mounted on the main surface of the wiring board in such a manner that each side faces each other at a predetermined interval and each main surface faces the main surface of the wiring board;
A plurality of first electrode pads disposed along one side of the first semiconductor chip on a main surface of the first semiconductor chip;
A plurality of second electrode pads disposed on a main surface of the second semiconductor chip along a side of the second semiconductor chip at an array pitch wider than the plurality of first electrode pads;
The plurality of second electrode pads include a plurality of second signal electrode pads arranged adjacent to each other,
The plurality of first electrode pads are a plurality of first signals electrically connected to the plurality of second signal electrode pads via a plurality of wirings formed on the main surface of the wiring board. Including electrode pads for
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other.

(2);
A wiring board;
A first semiconductor chip formed in a rectangular shape having a first side and a second side intersecting with the first side, wherein the main surface faces the main surface of the wiring board. A first semiconductor chip mounted on the main surface of the substrate;
A second semiconductor chip mounted on the main surface of the wiring board with a first side facing the first side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A third semiconductor chip mounted on the main surface of the wiring board with a first side facing the second side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A plurality of first electrode pads including a plurality of first signal electrode pads, the first electrode pads being disposed on a main surface of the first semiconductor chip along a first side of the first semiconductor chip. A plurality of first electrode pads;
A plurality of second electrode pads including a plurality of second signal electrode pads, wherein the first electrode is formed on a main surface of the second semiconductor chip along a first side of the second semiconductor chip; A plurality of second electrode pads arranged at a wider array pitch than the electrode pads of
A plurality of third electrode pads including a plurality of third signal electrode pads, wherein the plurality of third electrode pads are formed on the main surface of the third semiconductor chip along the first side of the third semiconductor chip. A plurality of third electrode pads arranged at a wider array pitch than the first electrode pads;
A plurality of first wirings formed on the main surface of the wiring substrate and extending along the X direction, each one end of which is electrically connected to the plurality of first signal electrode pads; A plurality of first wires in which the other end side opposite to each one end side is electrically connected to the plurality of second signal electrode pads;
A plurality of second wirings formed on the main surface of the wiring board and having one end side electrically connected to the third signal electrode pad;
A conductive plate formed below the first wiring of the wiring board;
A plurality of first through holes formed in the conductive plate;
A plurality of second through holes formed in the conductive plate;
A plurality of third wirings formed below the conductive plate of the wiring board and extending along the Y direction;
A plurality of first through-hole wirings each electrically connecting the plurality of first wirings and one end side of the plurality of second wirings through the plurality of first through holes;
A plurality of second throughs each electrically connecting the other end side of the plurality of second wires and the other end side of the plurality of third wires through the plurality of second through holes, respectively. Hall wiring and
The plurality of second and third signal electrode pads are arranged adjacent to each other,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, the wiring density of the wiring board can be improved.
According to the present invention, the reliability of a semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

  In the first embodiment, an example in which the present invention is applied to a SiP type semiconductor device in which a plurality of semiconductor chips are mounted in parallel on a wiring board will be described.

1 to 6 are diagrams related to a SiP type semiconductor device that is Embodiment 1 of the present invention.
1A and 1B are diagrams illustrating a schematic configuration of a semiconductor device (FIG. 1A is a schematic plan view in which a part of a resin sealing body is omitted, and FIG. 1B is a schematic cross-sectional view taken along the line aa in FIG. ),
FIG. 2 is a schematic plan view showing a connection state between semiconductor chips,
FIG. 3 is a schematic cross-sectional view showing a connection state between semiconductor chips,
FIG. 4 is a schematic plan view showing a part of a wiring pattern formed in the first conductive layer of the wiring board;
FIG. 5 is a schematic plan view showing a GND plane (conductive plate) formed in the second conductive layer (wiring layer) of the wiring board;
FIG. 6 is a schematic plan view showing a part of the wiring pattern formed in the third conductive layer (wiring layer) of the wiring board.

  In FIG. 2, the electrode pads of each semiconductor chip are shown through. FIG. 4 also shows the electrode pads of each semiconductor chip.

  As shown in FIGS. 1 (a) and 1 (b), the SiP type semiconductor device according to the first embodiment has three semiconductor chips (1, 3, 5) on the main surface 10x of the wiring substrate 10 also called an interposer. A plurality of ball-shaped solder bumps 22 are arranged as external connection terminals on the back surface 10y on the opposite side of the main surface 10x of the wiring board 10 that is mounted. The three semiconductor chips (1, 3, 5) are resin-sealed by a resin sealing body 21 formed on the main surface 10x of the wiring board 10.

  The wiring substrate 10 has a square shape that intersects the thickness direction. The semiconductor chip 1 has a planar shape intersecting the thickness direction, two sides (first side 1a and second side 1b) located on opposite sides, and the two sides and opposite sides. It has a rectangular shape having two sides (third side 1c and fourth side 1d) located at. The semiconductor chip 3 has two sides (a first side 3a and a second side 3b) that are opposite to each other in a planar shape that intersects the thickness direction, and the two sides are opposite to each other. It has a rectangular shape having two sides (third and fourth sides) located in the area. The semiconductor chip 5 has two sides (5a, 5b) that are opposite to each other in a plane shape that intersects the thickness direction, and two sides that are opposite to each other (second sides) 3 and the fourth side).

  For example, a logic operation circuit is mounted as an integrated circuit on the main surface side of the semiconductor chip 1, and a DRAM circuit having the same function is mounted as an integrated circuit on the semiconductor chips 3 and 5.

  On the main surface of the semiconductor chip 1, as shown in FIG. 2, a plurality of electrode pads 2 are arranged along four sides (1a to 1d). A plurality of electrode pads 4 are arranged along two sides (3a and 3b, 5a and 5b) on the main surface of the semiconductor chip (3, 5). The plurality of electrode pads 4 of the semiconductor chip 1 are arranged at a narrower arrangement pitch than the plurality of electrode pads 4 of the semiconductor chip (3, 5).

  The semiconductor chip 1 is mounted on the main surface 10x of the wiring substrate 10 with its main surface facing the main surface 10x of the wiring substrate 10. The semiconductor chip 3 is mounted on the main surface 10x of the wiring substrate 10 with the first side 3a facing the first side 1a of the semiconductor chip 1 and the main surface facing the main surface 10x of the wiring substrate 10. ing. The semiconductor chip 5 is mounted on the main surface 10x of the wiring substrate 10 with its first side 5a facing the third side 1c of the semiconductor chip 1 and its main surface facing the main surface 10x of the wiring substrate 10. ing. The semiconductor chips 3 and 5 are arranged at positions away from the semiconductor chip 1.

  In the semiconductor chips 3 and 5, the plurality of electrode pads 4 arranged along the first side (3a, 5a) include a plurality of signal electrode pads 4a arranged adjacent to each other. In the semiconductor chip 1, a plurality of signal pads that are electrically connected to the plurality of signal electrode pads 4 a of the semiconductor chips 3 and 5 are respectively connected to the plurality of electrode pads 2 arranged along the first side 1 a. A pad 2a is included.

  In the semiconductor chip 1, the plurality of signal electrode pads 2 a included in the plurality of electrode pads 2 arranged along the first side 1 a sandwich the electrode pads 2 b having other functions so as not to be adjacent to each other. Is arranged in. That is, the plurality of signal electrode pads 2a are arranged at a wider arrangement pitch than the plurality of electrode pads 2 including them. As the electrode pad 2b, for example, a power electrode pad is used.

  For example, as shown in FIG. 3, the wiring substrate 10 has a multilayer wiring structure having a main surface 10x and a back surface 10y and a wiring layer therein. In the first embodiment, for example, six layers are provided. It has a wiring structure.

The first wiring layer counted from the main surface 10x of the wiring substrate 10 has a plurality of signal electrodes arranged along the first side 1a of the semiconductor chip 1 as shown in FIGS. A plurality of signal wirings 11 a are formed to electrically connect the pads 2 a and the plurality of signal electrode pads 4 a arranged along the first side 4 a of the semiconductor chip 3. The plurality of signal wirings 11 a extend along the X direction between the semiconductor chip 1 and the semiconductor chip 3.
In addition to the plurality of signal lines 11a, signal lines 11b, 11c, 11d and the like are also formed in the first wiring layer.

  As shown in FIGS. 3 and 5, a plane (plate) 12 that spreads in a plane is formed in the second wiring layer counted from the main surface 10 x of the wiring substrate 10. The plane 12 is provided for the purpose of suppressing interference between the electric signal flowing through the first-layer signal wiring and the electric signal flowing through the third-layer signal wiring. For example, the potential is fixed at 0V).

  As shown in FIGS. 3 and 6, a plurality of signal wirings 13 are formed in the third wiring layer counting from the main surface 10 x of the wiring substrate 10. The plurality of signal wirings 13 extend along the Y direction perpendicular to the X direction in the same plane.

  Although not shown, a plurality of signal wirings are formed in the fourth wiring layer counting from the main surface 10x of the wiring board 10, and the fifth layer counting from the main surface 10x of the wiring board 10 is provided. In this wiring layer, as shown in FIG. 3, similarly to the second-layer plane 12, a plane 15 that extends in a plane is formed. The plane 15 is fixed as a power supply potential, for example, at a reference potential or an operation potential higher than the reference potential (eg, 3.3 V).

  As shown in FIG. 3, a plurality of electrode pads 16 are formed in the sixth wiring layer counted from the main surface 10 x of the wiring substrate 10. A plurality of solder bumps 22 are electrically and mechanically connected to the plurality of electrode pads 16, respectively.

  A plurality of signal electrode pads 2a arranged along the first side 1a of the semiconductor chip 1 are respectively compatible with conductive bumps (protruding electrodes) 20 as shown in FIGS. Are electrically connected to one end sides of the plurality of signal wirings 11a. The plurality of signal electrode pads 4a arranged along the first side 3a of the semiconductor chip 3 are respectively connected to the other end side (one end side) of the corresponding plurality of signal wirings 11a with the conductive bumps 20 interposed therebetween. Are electrically connected to the other side. That is, the plurality of signal electrode pads 2 a arranged along the first side 1 a of the semiconductor chip 1 are connected to the semiconductor via the plurality of signal wirings 11 a formed on the first wiring layer of the wiring substrate 10. Each of the signal electrode pads 4a arranged along the first side 3a of the chip 3 is electrically connected.

  As shown in FIG. 2, the plurality of electrode pads 2 arranged along the third side 1 c of the semiconductor chip 1 are electrically connected to the signal electrode pads 4 a arranged on the first side 3 a of the semiconductor chip 3. The signal electrode pad 2a connected to is included. As shown in FIG. 4, the electrode pad is used for a signal disposed on the first side 3 a of the semiconductor chip 3 via a signal wiring 11 d formed in the first wiring layer of the wiring substrate 10. It is electrically connected to the electrode pad 4a.

  In the wiring board 10, the plurality of signal wirings 13 in the third layer are connected to the plurality of first layer wirings through the through-hole wirings 17 a, as shown in FIGS. 3, 4, and 6. Each is electrically connected to an intermediate portion of the signal wiring 11a. Further, the plurality of signal wirings 13 in the third layer are electrically connected to one end sides of the plurality of signal wirings 11b in the first layer through the through-hole wirings 17b, respectively. ing. As shown in FIGS. 3 and 4, the other end side of the plurality of signal wirings 11 b in the first layer is disposed along the first side 5 a of the semiconductor chip 5 with the conductive bumps 20 interposed therebetween. The plurality of signal electrode pads 4a are electrically connected to each other.

  That is, the plurality of signal electrode pads 2 a arranged along the first side 1 a of the semiconductor chip 1 are arranged along the first side 3 a of the semiconductor chip 3 through the wiring of the wiring substrate 10. The plurality of signal electrode pads 4 a are electrically connected to each other, and are further electrically connected to the plurality of signal electrode pads 4 a arranged along the first side 5 a of the semiconductor chip 5.

  As shown in FIGS. 3 and 5, the second-layer plane 12 has a plurality of through holes 12a corresponding to the number of the through hole wirings 17a through which the through hole wirings 17a pass. The upper-layer signal wiring 11a and the lower-layer signal wiring 13 are electrically connected by the through-hole wiring 17a passing through 12a. Further, a plurality of through holes 12b for passing through-hole wirings 17b are formed in the second layer plane 12 in accordance with the number of through-hole wirings 17b. By the through-hole wirings 17b passing through the through-holes 12b, The upper signal wiring 17b and the lower signal wiring 13 are electrically connected.

  The plurality of electrode pads (2, 4) of each semiconductor chip (1, 3, 5) include a ground electrode pad whose potential is fixed to the reference potential among the power supply potentials. These electrode pads for ground are ground wiring formed in the first wiring layer and through-hole wiring for electrically connecting the ground wiring and the second plane 12 in the wiring substrate 10. And electrically connected to the plane 12.

  The electric signal output from the signal electrode pad 2 a of the semiconductor chip 1 is transmitted to the signal electrode pad 4 a of the semiconductor chip 3 through the signal wiring 11 a of the first layer of the wiring substrate 10. A return current flows along with the electrical signal at this time. The return current flows from the ground electrode pad of the semiconductor chip 3 to the ground electrode pad of the semiconductor chip 1 through the ground electrode pad, the through-hole wiring, the plane 12, the through-hole wiring, and the ground electrode pad.

  In the first embodiment, the plurality of signal electrode pads 2a arranged along the first side 1a of the semiconductor chip 1 are arranged with the electrode pads 4b having other functions interposed therebetween so as not to be adjacent to each other. ing. With such a configuration, a plurality of signal electrode pads 2 a disposed along the first side 1 a of the semiconductor chip 1 and a plurality of signals disposed along the first side 3 a of the semiconductor chip 3. Since a plurality of signal wirings 11a that are electrically connected to the signal electrode pads 4a can be gradually or eliminated from spreading in a fan shape (radially) from the semiconductor chip 1 side toward the semiconductor chip 3 side, Thus, the equal length of the signal wiring 11a can be easily secured, and the operation speed of the SiP type semiconductor device can be increased.

  Further, the arrangement pitch of the plurality of signal wirings 11a on the semiconductor chip 1 side is widened, and in order to ensure the equal length of the signal wirings to the two semiconductor chips (3, 5), the signal wiring for the first layer is used. Even if the through-hole wiring 17a for electrical connection between the wiring 11a and the third-layer signal wiring 13 is arranged close to the semiconductor chip 1, the through-hole for passing the through-hole wiring is connected. Such a problem can be suppressed. Accordingly, the return current flowing through the plane in accordance with the electrical signal transmitted from the signal electrode pad 2a of the semiconductor chip 1 to the signal electrode pad 4a of the semiconductor chip 3 through the signal wiring 11a is connected to the plurality of through holes 12a. Therefore, it is possible to avoid the occurrence of problems such as detouring, and to suppress the generation of noise due to the return current not returning at the same timing, so that the reliability of the SiP type semiconductor device can be improved.

  The plurality of signal electrode pads (2a, 4a) include a plurality of data signal electrode pads and a plurality of address signal electrode pads. The data signal needs to be transmitted faster than the address signal. Accordingly, among the plurality of signal electrode pads 4a arranged along the first side 1a of the semiconductor chip 1, the plurality of data signal electrode pads are not adjacent to each other, and the electrode pads having other functions are interposed therebetween. It is desirable to place them between them. In this case, an address signal electrode pad may be interposed therebetween. There may be one or a plurality of electrode pads having other functions sandwiched therebetween.

  In the second embodiment, an example in which the present invention is applied to a SiP type semiconductor device in which a plurality of semiconductor chips are three-dimensionally stacked and mounted on a wiring board will be described.

  7A and 7B are diagrams (a) a schematic plan view and (b) a schematic cross-sectional view showing a schematic configuration of a SiP type semiconductor device that is Embodiment 2 of the present invention.

  As shown in FIGS. 7A and 7B, the SiP type semiconductor device according to the second embodiment is mounted with two semiconductor chips (1, 3) stacked three-dimensionally on the main surface of the wiring board 10. (Stack implementation). The lower semiconductor chip 1 is mounted on the main surface of the wiring substrate 10 with its main surface facing the main surface of the wiring substrate 10 as in the first embodiment. Unlike the first embodiment, the upper semiconductor chip 3 is bonded and fixed to the back surface of the semiconductor chip 1 with the back surface opposite to the main surface facing the back surface of the semiconductor chip 1. The plurality of electrode pads 4 of the semiconductor chip 3 are electrically connected to the plurality of electrode pads 31 formed on the first wiring layer of the wiring substrate 10 via the plurality of bonding wires 30, respectively.

  In the case of such stack mounting, other electrodes are arranged so that the plurality of signal electrode pads 2a of the lower semiconductor chip 1 are not adjacent to each other in accordance with the interval between the plurality of signal electrode pads 4a of the upper semiconductor chip 3. Since the plurality of signal electrode pads 2a and the plurality of electrode pads 31 are electrically connected to each other, it is possible to easily ensure the equal length of the plurality of signal wirings by sandwiching the pads therebetween. Also in the SiP type semiconductor device of Example 2, the operation speed can be increased.

  In the first and second embodiments, the electrical connection between the semiconductor chip on which the logic operation circuit is mounted and the semiconductor chip on which the DRAM circuit is mounted has been described. However, the present invention is limited to this. For example, the present invention can also be applied to electrical connection between two semiconductor chips on which a logic operation circuit is mounted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

The figure which shows schematic structure of the SiP type semiconductor device which is Example 1 of this invention ((a) is a schematic plan view which abbreviate | omitted a part of resin sealing body, (b) is the aa line | wire of (a). FIG. FIG. 2 is a schematic plan view showing a connection state between semiconductor chips in the SiP type semiconductor device of FIG. 1. FIG. 2 is a schematic cross-sectional view showing a connection state between semiconductor chips in the SiP type semiconductor device of FIG. 1. FIG. 2 is a schematic plan view showing a part of a wiring pattern formed in a first conductive layer of a wiring board in the SiP type semiconductor device of FIG. 1. FIG. 2 is a schematic plan view showing a GND plane (conductive plate) formed in a second conductive layer of the wiring board in the SiP type semiconductor device of FIG. 1. 2 is a schematic plan view showing a part of a wiring pattern formed in a third conductive layer of a wiring board in the SiP type semiconductor device of FIG. It is a figure ((a) is a typical top view, (b) is a typical sectional view) which shows schematic structure of the SiP type semiconductor device which is Example 2 of this invention. In the conventional SiP type semiconductor device, it is a schematic plan view which shows the connection state between each semiconductor chip. In the SiP type semiconductor device of FIG. 8, it is a figure ((a) is a typical perspective view, (b) is a typical sectional view) which shows the internal structure of a wiring board. FIG. 9 is a schematic perspective view for explaining a return current in the SiP type semiconductor device of FIG. 8.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 3, 5 ... Semiconductor chip, 2, 4 ... Electrode pad, 2a, 4a ... Signal electrode pad, 10 ... Wiring board, 11a, 11b, 13 ... Wiring, 12, 15 ... Plane (plate), 12a ... Through Hole: 16 ... Electrode pad, 17a, 17b ... Through-hole wiring, 20 ... Bump, 21 ... Resin sealing body, 22 ... Solder bump, 30 ... Bonding wire, 31 ... Electrode pad.

Claims (16)

A wiring board;
First and second semiconductor chips mounted on the main surface of the wiring board in such a manner that each side faces each other at a predetermined interval and each main surface faces the main surface of the wiring board;
A plurality of first electrode pads disposed along one side of the first semiconductor chip on a main surface of the first semiconductor chip;
A plurality of second electrode pads disposed on a main surface of the second semiconductor chip along a side of the second semiconductor chip at an array pitch wider than the plurality of first electrode pads;
The plurality of second electrode pads include a plurality of second signal electrode pads arranged adjacent to each other,
The plurality of first electrode pads are a plurality of first signals electrically connected to the plurality of second signal electrode pads via a plurality of wirings formed on the main surface of the wiring board. Including electrode pads for
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with a wider arrangement pitch than the plurality of first electrode pads. The semiconductor device according to claim 1,
The plurality of wirings are arranged between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 1,
The plurality of first signal electrode pads are connected to one end sides of the plurality of wirings via bumps, respectively.
The plurality of second signal electrode pads are connected to the other end side opposite to one end side of the plurality of wirings via bumps, respectively. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first and second signal electrode pads are data signal electrode pads. The semiconductor device according to claim 1,
The plurality of first and second signal electrode pads are data signal electrode pads;
2. The semiconductor device according to claim 1, wherein the other function electrode pad is an address signal electrode pad. The semiconductor device according to claim 1,
The first semiconductor chip is a chip on which a logic operation circuit is mounted,
The semiconductor device, wherein the second semiconductor chip is a chip on which a DRAM is mounted. A wiring board;
A first semiconductor chip formed in a rectangular shape having a first side and a second side intersecting with the first side, wherein the main surface faces the main surface of the wiring board. A first semiconductor chip mounted on the main surface of the substrate;
A second semiconductor chip mounted on the main surface of the wiring board with a first side facing the first side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A third semiconductor chip mounted on the main surface of the wiring board with a first side facing the second side of the first semiconductor chip and a main surface facing the main surface of the wiring board;
A plurality of first electrode pads including a plurality of first signal electrode pads, the first electrode pads being disposed on a main surface of the first semiconductor chip along a first side of the first semiconductor chip. A plurality of first electrode pads;
A plurality of second electrode pads including a plurality of second signal electrode pads, wherein the first electrode is formed on a main surface of the second semiconductor chip along a first side of the second semiconductor chip; A plurality of second electrode pads arranged at a wider array pitch than the electrode pads of
A plurality of third electrode pads including a plurality of third signal electrode pads, wherein the plurality of third electrode pads are formed on the main surface of the third semiconductor chip along the first side of the third semiconductor chip. A plurality of third electrode pads arranged at a wider array pitch than the first electrode pads;
A plurality of first wirings formed on the main surface of the wiring substrate and extending along the X direction, each one end of which is electrically connected to the plurality of first signal electrode pads; A plurality of first wires in which the other end side opposite to each one end side is electrically connected to the plurality of second signal electrode pads;
A plurality of second wirings formed on the main surface of the wiring board and having one end side electrically connected to the third signal electrode pad;
A conductive plate formed below the first wiring of the wiring board;
A plurality of first through holes formed in the conductive plate;
A plurality of second through holes formed in the conductive plate;
A plurality of third wirings formed below the conductive plate of the wiring board and extending along the Y direction;
A plurality of first through-hole wirings each electrically connecting the plurality of first wirings and one end side of the plurality of second wirings through the plurality of first through holes;
A plurality of second throughs each electrically connecting the other end side of the plurality of second wires and the other end side of the plurality of third wires through the plurality of second through holes, respectively. Hall wiring and
The plurality of second and third signal electrode pads are arranged adjacent to each other,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with electrode pads of other functions interposed therebetween so as not to be adjacent to each other. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first signal electrode pads are arranged with a wider arrangement pitch than the plurality of first electrode pads. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first wirings are arranged between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of second wirings are disposed outside the plurality of first wirings. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first through-hole wirings are arranged between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 8,
The plurality of first signal electrode pads are connected to one end side of the plurality of first wirings via bumps, respectively.
The plurality of second signal electrode pads are connected to the other ends of the plurality of first wirings via bumps, respectively.
The plurality of third signal electrode pads are connected to one end sides of the plurality of second wirings through bumps, respectively. The semiconductor device according to claim 8,
The semiconductor device, wherein the plurality of first, second, and third signal electrode pads are data signal electrode pads. The semiconductor device according to claim 8,
The plurality of first, second, and third signal electrode pads are data signal electrode pads;
2. The semiconductor device according to claim 1, wherein the other function electrode pad is an address signal electrode pad. The semiconductor device according to claim 8,
The first semiconductor chip is a chip on which a logic operation circuit is mounted,
2. The semiconductor device according to claim 1, wherein the second and third semiconductor chips are chips on which a DRAM is mounted.

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