JP2005166763A - Semiconductor circuit, its manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a TFT from being electrostatically damaged in the signal line drive circuit of a liquid crystal display panel. <P>SOLUTION: In a semiconductor circuit, the gate electrode of the second TFT 52 having the semiconductor layer 52a provided on a glass substrate is connected to the second separated wiring 48 for constituting second gate wiring. The second separated wiring 48 is electrically isolated from the first separated wiring 46 for constituting the second gate wiring. The semiconductor layer 52a of the second TFT 52, the first separated wiring 46, and the second separated wiring 48 are covered with an interlayer insulating film. The source region and the drain region in the semiconductor layer 52a are respectively electrically connected to the power source supply line 43 and output wiring 44 formed on the interlayer insulating film. The second separated wiring 48 has a length from the semiconductor layer 52a becoming 150-300 μm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor circuit having a thin film transistor used in a display panel such as a liquid crystal display device, a manufacturing method thereof, and a semiconductor device constituted by a plurality of semiconductor circuits.

  A display panel of a liquid crystal display device includes an active matrix substrate in which a plurality of pixel electrodes are provided in a matrix, and a color filter substrate that is disposed to face the active matrix substrate with a liquid crystal layer interposed therebetween. A plurality of pixel electrodes are provided in a matrix on the active matrix substrate, and a thin film transistor (TFT) is connected to each pixel electrode. Each thin film transistor is connected to a scanning signal line along the row direction and is also connected to a data signal line along the column direction. Each scanning signal line is controlled by a scanning signal line driving circuit, and a data signal output from the data signal line driving circuit is applied to each data signal line.

  In a scanning signal line driving circuit for controlling each scanning signal line, a number of wirings and a number of thin film transistors are provided in an output buffer circuit or the like in order to give a control signal to each scanning signal line. Similarly, in a data signal line driver circuit that outputs a data signal to each data signal line, a shift register circuit or the like is provided with a large number of wirings and a large number of TFTs.

  The scanning signal line driving circuit and the data signal line driving circuit are usually provided in a limited space at the side edges orthogonal to each other in the liquid crystal display panel. The size, arrangement, etc. are greatly restricted.

  The TFT used for the scanning signal line driving circuit and the data signal line driving circuit is different from the TFT connected to the pixel electrode formed on the order of several hundreds on one scanning signal line, and the signal connected to the gate electrode. Only a few are connected to the line at most. Therefore, the TFT capacitance per signal line connected to the gate electrode in the drive circuit is smaller than the capacitance of the TFT connected to the pixel electrode. In addition, the TFT used in each drive circuit is formed independently of other capacitors without being connected to a liquid crystal capacitor, an auxiliary capacitor, or the like, like a TFT connected to a pixel electrode. When a large charge is charged, there is a risk of electrostatic breakdown due to the accumulation of the charge.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2000-36604), when peripheral TFTs such as a scanning signal line driver circuit and a data signal line driver circuit are formed with a TFT connected to a bus line having a large capacity, the TFT In order to prevent electrostatic breakdown of the TFT, after forming the gate electrode of the TFT and the interlayer insulating film, a bus wiring is formed on the interlayer insulating film, and the bus wiring and the gate electrode are formed by contact holes provided in the interlayer insulating film. Is disclosed.

As described above, by forming the bus wiring and the gate electrode having a large capacity with the interlayer insulating film interposed therebetween, there is no possibility that the charge charged to the bus wiring when patterning the bus wiring is charged to the TFT. The electrostatic breakdown of the TFT is prevented.
JP 2000-36604 A

  In a TFT provided in a scanning signal line driver circuit, a data signal line driver circuit, or the like, the arrangement of the TFT is restricted, so that the gate wiring itself connected to the gate electrode may be long. As described above, when the gate wiring becomes long, when the gate wiring is patterned by dry etching or the like in a state where the gate wiring is electrically connected to the TFT, charges are charged in the long gate wiring, and the charges are transferred to the gate wiring. There is a possibility that the TFT is electrostatically broken by being charged to the TFT connected to the TFT.

  In this case, since the gate wiring connected to the gate electrode is formed on the gate insulating film, there is a problem that it is not easy to form separately above and below the interlayer insulating film as in Patent Document 1. That is, a large number of wirings such as bus wirings are formed on the interlayer insulating film, and it is almost impossible to form gate wirings on the interlayer insulating film without being electrically connected to these bus wirings. Is possible.

  Further, when a plurality of TFTs are formed by one semiconductor layer, there is a large difference in the amount of charge charged to each gate wiring when patterning the gate wiring connected to the gate electrode of each TFT. Further, a high voltage is applied to the semiconductor layer by each gate wiring, and there is a possibility that the semiconductor layer constituting each TFT is destroyed.

  The present invention solves such a problem, and an object of the present invention is to provide a semiconductor circuit, a manufacturing method thereof, and a semiconductor device in which a TFT can be formed without electrostatic breakdown.

  The semiconductor circuit of the present invention includes an insulating substrate, a TFT having a semiconductor layer provided on the insulating substrate, a gate wiring connected to the gate electrode of the TFT, and a semiconductor layer and gate wiring of the TFT. A semiconductor circuit having an interlayer insulating film to be covered, and a wiring formed on the interlayer insulating film and electrically connected to the source region and the drain region in the semiconductor layer of the TFT via contact holes, The gate wiring is electrically separated at a predetermined distance from the semiconductor layer of the TFT, and the mutually separated gate wiring portions are a pair of contacts provided in the interlayer insulating film. They are electrically connected to each other by a hole and a connecting portion provided on the interlayer insulating film.

  The gate wiring is separated at a position 150 to 300 μm away from the semiconductor layer of the TFT.

  The gate wiring is separated at a position 150 to 200 μm away from the semiconductor layer of the TFT.

  The semiconductor circuit of the present invention includes an insulating substrate, a pair of TFTs formed by a semiconductor layer provided on the insulating substrate, and a pair of gate wirings respectively connected to the gate electrodes of the TFTs. An interlayer insulating film covering the semiconductor layer and each gate wiring, and formed on the interlayer insulating film, and electrically connected to the source region and drain region of each TFT in the semiconductor layer via contact holes, respectively. Each of the gate wirings is electrically separated at a position away from the semiconductor layer by a predetermined distance, and the difference between the distances is within a predetermined range. It is characterized by becoming.

  The difference in the distance is 50 to 200 μm or less.

  The difference in the distance is 50 to 100 μm or less.

Each of the gate wirings is electrically connected to a connecting portion provided on the interlayer insulating film via a contact hole formed in the interlayer insulating film, and the connecting portion is formed on the interlayer insulating film. The method for manufacturing a semiconductor circuit of the present invention, which is connected to a wiring provided on the gate insulating film through a contact hole, includes a step of forming a semiconductor layer constituting a TFT on an insulating substrate, Covering the semiconductor layer with a gate insulating film; forming a gate wiring connected to the gate electrode of the TFT on the gate insulating film in a separated state; and the semiconductor layer and gate of the TFT A step of forming an interlayer insulating film covering the wiring; and the first and second contact holes corresponding to the source region and the drain region in the semiconductor layer of the TFT, and the gate Forming a third contact hole and a fourth contact hole corresponding to each separated portion of the wiring, and forming the source region and the drain region on the interlayer insulating film by the first contact hole and the second contact hole. Forming wirings that are electrically connected to each other, and forming connection portions that electrically connect the separated portions of the gate wiring by the third and fourth contact holes, respectively. Include.

  The gate wiring is separated from the semiconductor layer of the TFT by a distance of 150 to 300 μm.

  The gate wiring is separated from the semiconductor layer of the TFT by a distance of 150 to 200 μm.

The method for manufacturing a semiconductor circuit of the present invention includes a step of forming a semiconductor layer on an insulating substrate, a step of covering the semiconductor layer with a gate insulating film, and a gate of a pair of TFTs on the gate insulating film. Covering the semiconductor layer and the gate wiring, and a step of forming the electrode and the gate wiring connected to each gate electrode with a predetermined length so that the difference between the lengths is within a predetermined range Forming an interlayer insulating film; forming a first contact hole and a second contact hole corresponding to a source region and a drain region of each TFT in the semiconductor layer in the interlayer insulating film; and Forming wirings respectively connected to the source region and the drain region by the first and second contact holes;
Is included.

  The difference between the lengths of the gate wirings is 50 to 200 μm or less.

  The difference between the lengths of the gate lines is 50 to 100 μm or less.

  At least one of the gate wirings is connected to a connecting portion provided on the interlayer insulating film through a contact hole formed in the interlayer insulating film, and the connecting portion is formed in the interlayer insulating film. The contact hole is connected to the wiring provided on the gate insulating film.

  Furthermore, the semiconductor device of the present invention is provided with a plurality of the semiconductor circuits.

  An arithmetic circuit is constituted by the plurality of semiconductor circuits.

  A driving part of a liquid crystal panel is constituted by the plurality of semiconductor circuits.

  In the semiconductor circuit, the manufacturing method thereof, and the semiconductor device of the present invention, when the TFT is manufactured, the gate wiring connected to the semiconductor layer of the TFT is separated to a predetermined length. There is no fear that the portion is charged with charges that cause electrostatic breakdown of the semiconductor layer of the TFT, and the semiconductor layer of the TFT can be prevented from electrostatic breakdown.

  Even when at least a pair of semiconductor layers are formed by one semiconductor layer, the difference in length of the gate wiring connected to the semiconductor layer of each TFT is within a predetermined range. There is no possibility that a high voltage is applied to the semiconductor layer due to the electric charge charged in the wiring, and this can also prevent electrostatic breakdown of the semiconductor layer of the TFT.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is a schematic configuration diagram of a liquid crystal display panel provided with a semiconductor circuit of the present invention. The liquid crystal display panel shown in FIG. 1 has an active matrix substrate in which a plurality of pixel electrodes are provided in a matrix, and a color filter substrate disposed opposite to the active matrix substrate with a liquid crystal layer interposed therebetween.

  In the liquid crystal display panel, a display unit 10 in which a plurality of pixels (PIX) 11 are provided in a matrix is provided in a region excluding the side edges orthogonal to each other in the liquid crystal display panel. In the active matrix substrate of the liquid crystal display panel, a data signal line driving circuit 20 is provided on one side edge other than the display unit 10, and a scanning signal line driving circuit 30 is provided on the other side edge. Yes.

  In the display unit 11 of the liquid crystal display panel, scanning signal lines (GL1, GL2,..., GLk) 12 are arranged on the active matrix substrate along the pixels 11 arranged in the row direction, respectively. Each data signal line (SL1, SL2,..., SLk) 13 is arranged along each pixel electrode 11 arranged in the column direction.

  FIG. 2 is a circuit diagram showing a configuration of each pixel (PIX (i, j)) 11 in the liquid crystal display panel. Each scanning signal line (GLj) 12 and each data signal line (SLj) 13 are connected to a thin film transistor TFT which is a switching element. Each pixel (PIX (i, j)) in the display panel has a pixel capacitor CP formed by a liquid crystal capacitor CL and an auxiliary capacitor CS. The liquid crystal capacitor CL is formed by each pixel electrode provided on the active matrix substrate, a counter electrode provided on the color filter substrate, and a liquid crystal layer provided therebetween. Each pixel capacitor CP is controlled by each thin film transistor TFT.

  As shown in FIG. 1, each scanning signal line 12 is controlled by a scanning signal drive circuit 30. The scanning signal line driving circuit 30 includes a first circuit unit 31 that constitutes a level shifter / control circuit, a second circuit unit 32 that constitutes a bidirectional shift register, and a third circuit unit 33 that constitutes an output buffer circuit. Are provided individually. The scanning signal line driving circuit 30 is controlled by various signals (gate side control signal GEN, gate side start signal SPG, gate side clock signal CKG, switching signal U / D, etc.) output from the controller 40.

  Each data signal line 13 is controlled by a data signal driving circuit 20. The data signal line driving circuit 30 includes a first circuit unit 21 that constitutes a level shifter / control circuit, a second circuit unit 22 that constitutes a bidirectional shift register, and a third circuit unit 23 that constitutes a sampling unit. Is provided. The first circuit portion 21 constituting the level shifter / control circuit and the like and the second circuit portion 22 constituting the bidirectional shift register are integrally formed, and the output of the second circuit portion 22 is connected to the signal wiring (S1). , S2,..., Sk) 24, and is supplied to the third circuit unit 23 constituting the sampling unit. The data signal line driving circuit 20 is controlled by various signals (switching signal L / R, data side clock signal CKS, data side start signal SPS, data signal DAT, etc.) output from the controller 40.

  FIG. 3 is a circuit diagram showing a partial configuration of the scanning signal line driving circuit 30. The bidirectional shift register provided in the second circuit section 32 of the scanning signal line driving circuit 30 has a plurality of flip-flop circuits 32a connected in series, and the first input terminal D of each flip-flop circuit 32a is connected to the first flip-flop circuit 32a. Analog switches (A1 to A6) 32b are connected to each other. The start signal SP is input to the first analog switch 32b connected to the flip-flop 32a located on the signal input end side of the bidirectional shift register 32 via the level shifter 31b.

  Each first analog switch 32 b is controlled by a switching signal U / D output via the first level shifter 31 a of the first circuit unit 31. The output of each flip-flop circuit 32 a is input to a NAND circuit 33 a that is an arithmetic circuit that constitutes the output buffer circuit of the third circuit unit 33.

  The outputs of the flip-flops 32a arranged evenly from the signal input end side of the bidirectional shift register are odd numbers adjacent to the signal input end side of the bidirectional shift register via the second analog switches (B1 to B6) 32c. It is given to the input terminal D of the second flip-flop 32a. The start signal SPG is input to the input terminal D of the flip-flop circuit 32a located farthest from the signal input end side of the bidirectional shift register via the second level shifter 31b and the second analog switch 32c. Has been.

  A switching signal U / D is given to each second analog switch 32c via a first level shifter 31a and an inverter 31e.

  A clock signal CK input to the scanning signal line driving circuit 30 is supplied to the terminal CK of each flip-flop 32a through the third level shifter 31c.

  By configuring the first circuit unit 31 and the second circuit unit 32 of the scanning signal line driving circuit 30 in this way, the start signal SP is based on the switching signal U / D in synchronization with the clock signal CK. Are output to the NAND circuits 33a of the buffer circuit 33 in order.

  A control signal GEN output from the controller 40 is supplied to each NAND circuit 33a of the buffer circuit 33 via the level shifter 31d. Each NAND circuit 33a outputs a control signal input via the level shifter 31d in synchronization with the output from each flip-flop 32a. The output of each NAND circuit 33a is output to each scanning signal line (GL1, GL2,...) 13 via an inverter circuit 33b configured by, for example, three inverters.

  FIG. 4 is a schematic plan view showing a specific configuration of a part of the buffer circuit 33 in the scanning signal line driving circuit 30. The scanning signal line drive circuit 30 is formed on a glass substrate 40a (see FIG. 5) which is an insulating substrate constituting an active matrix substrate, and has a line width for supplying a constant signal or voltage to the entire circuit. The four first signal wirings 41a which are thickened have a first signal wiring group 41 provided in a parallel state close to each other. In addition, one second signal wiring 42 is provided in parallel with each first signal wiring 41a with an appropriate interval from the signal wiring group 41. Each first signal wiring 41a and second signal wiring 42 of the first signal wiring group 41 are respectively formed on an interlayer insulating film 61 (see FIG. 5) provided on the glass substrate 40a.

  A power supply line 43 is provided in parallel to the second signal wiring 42 so as to be close to the second signal wiring 42 on the side opposite to the first signal wiring group 41. The power supply line 43 is provided below an interlayer insulating film 61 (see FIG. 5) provided on the glass substrate 40a. Further, a ground line 44 is provided in parallel with the power supply line 43 with an appropriate interval from the power supply line 43. The ground line 44 is also provided below the interlayer insulating film 61 (see FIG. 5).

  A first TFT (thin film transistor) 51 is connected to the first signal wiring 41 a located on one side of the signal wiring group 41.

  FIG. 5 is a cross-sectional view showing the configuration of the first TFT 51. The first TFT 51 has an island-shaped semiconductor layer 51a made of, for example, polycrystalline silicon on a glass substrate 40a that is an insulating substrate. The semiconductor layer 51a is formed smaller than the semiconductor layer of each thin film transistor TFT connected to each pixel electrode 11 in the display unit 11, and therefore the capacity thereof is smaller than the capacity of the semiconductor layer of each thin film transistor TFT. Yes.

As shown in FIG. 4, the semiconductor layer 51a is formed in a linear island shape orthogonal to the first signal wiring 41a, and one side portion of the semiconductor layer 51a is formed on the first signal wiring 41a. positioned. The side portion of the semiconductor layer 51a located on the first signal wiring 41a and the other side portion are a source region 51b and a drain region 51c doped with impurities, respectively, and the source region 51b and the gate region 51c. A central portion between the two is a gate region 51d. The semiconductor layer 51a is covered with, for example, a gate insulating film 51e made of SiO ₂ , and a gate region in the central portion between the source region 51b and the drain region 51c in the semiconductor layer 51a is formed on the gate insulating film 51e. Corresponding to 51d, a gate electrode formed by the tip of the first gate wiring 51f is provided. The first gate line 51f is formed in parallel with the first signal line 41a.

The first gate wiring 51f and the gate insulating film 51e are covered with an interlayer insulating film 61 made of SiO ₂ , and the interlayer insulating film 61 includes a first region corresponding to the source region 51b and the drain region 51c of the semiconductor layer 51a. A first contact hole 61a and a second contact hole 61b are formed. The source region 51b and the drain region 51c are exposed in the first contact hole 61a and the second contact hole 61b.

  The first signal wiring 41a and the second signal wiring 42 of the first signal wiring group 41 are provided on the interlayer insulating film 61, and the first signal wiring 41a adjacent to the first gate wiring 51f It is electrically connected to the source region 51b of the semiconductor layer 51a through one contact hole 61a. On the interlayer insulating film 61, a first connection portion 45 formed in a linear island shape parallel to the first gate wiring 51f is provided, and the first connection portion 45 is formed of the interlayer insulating film. The semiconductor layer 51a is electrically connected to the drain region 51c through a second contact hole 61b provided in the semiconductor layer 51a.

  As shown in FIG. 4, the first connection portion 45 connected to the drain region 51 c of the first TFT 51 via the second contact hole 61 b is connected to the interlayer via the third contact hole 61 c provided in the interlayer insulating film 61. It is electrically connected to one end of the first isolation wiring 46 that constitutes the second gate wiring formed below the insulating film 61. The first separation wiring 46 is formed on the gate insulating film 51e provided so as to cover the glass substrate 40a so as to be orthogonal to each signal wiring 41a of the first signal wiring group 41, and the other end portion. Is located in a region between the first signal wiring group 41 and the second signal wiring 42.

  In the vicinity of the end of the first isolation wiring 46 located in the region between the first signal wiring group 41 and the second signal wiring 42, a second isolation wiring that forms a second gate wiring together with the first isolation wiring 46 One end of 48 is disposed in an electrically separated state. The end of the first isolation wiring 46 adjacent to the end of the second isolation wiring 48 is in the shape of an island formed on the interlayer insulating film 61 through the fourth contact hole 61 d formed in the interlayer insulating film 61. The second connection portion 47 is electrically connected to one end portion. The second connection portion 47 is formed in a straight island shape parallel to the second signal wiring 42 corresponding to the region between the first signal wiring group 41 and the second signal wiring 42. The other end of the second connection portion 47 is connected to the end of the second isolation wiring 48 provided below the interlayer insulating film 61 through a fifth contact hole 61 e provided in the interlayer insulating film 61. ing. The second separation wiring 48 is provided so as to be orthogonal to the second signal wiring 42 and the power supply line 43.

  The second separation wiring 48 is provided with a branch portion 48 a that branches in parallel to the power supply line 43 in the vicinity of the power supply line 43 between the power supply line 43 and the ground line 44. The second separation wiring 48 extends to the vicinity of the ground line 44, and an end portion 44 b near the ground line 44 extends so as to be parallel to the ground line 44.

  The power supply line 43 is connected to the second TFT 52 constituting the NAND gate 33a. The second TFT 52 is composed of an n-type MOS transistor. The specific configuration of the second TFT 52 is the same as that of the first TFT 51 shown in FIG. 5, and an island-like semiconductor layer 52 a made of polycrystalline silicon Si is provided on the glass substrate 40 a with the power supply line 43. Is provided in a straight line along a direction perpendicular to the line. A source region of the semiconductor layer 52 a is connected to a power supply line 43 provided on the interlayer insulating film 61 through a sixth contact hole 61 f provided in the interlayer insulating film 61.

  The gate electrode of the second TFT 52 is configured by a tip end portion of a branch portion 48a provided in the second separation wiring 48 that constitutes the second gate wiring. The drain region of the semiconductor layer 52 a in the second TFT 52 is electrically connected to the end portion 49 a of the output wiring 49 provided on the interlayer insulating film 61 through the seventh contact hole 61 g formed in the interlayer insulating film 61. ing. The output wiring 49 is arranged in parallel with the power supply line 43 except for the end portion 49a, and the end portion 49a is in parallel with the second separation wiring 48 in the vicinity of the second separation wiring 48. It extends to the power supply line 43 side. A tip portion of the end portion 49a of the output wiring 49 adjacent to the power supply line 43 is connected to the drain region of the semiconductor layer 52a in the second TFT 52 through the seventh contact hole 61g.

  In the vicinity of the semiconductor layer 52a in the second TFT 52, the semiconductor layer 53a of the third TFT 53 constituting the NAND circuit 33a is formed in a linear island shape so as to form a straight line with the semiconductor layer 52a. In the third TFT 53, the semiconductor layer 53a is formed of a p-type MOS transistor having a conductivity type opposite to that of the semiconductor layer 52a of the second TFT 52, but has the same configuration as the first TFT 51 shown in FIG. The drain region of the semiconductor layer 53 a is connected to an output wiring 49 provided on the interlayer insulating film 61 through an eighth contact hole 61 f provided in the interlayer insulating film 61.

  The gate wiring of the third TFT 53 is configured by an end portion 48 b in the vicinity of the ground line 48 b in the second separation wiring 48. The source region of the semiconductor layer 53 a in the second TFT 53 is connected to the ground line 44 provided on the interlayer insulating film 61 through a ninth contact hole 61 i formed in the interlayer insulating film 61.

  The circuit configuration shown in FIG. 4 constitutes a part of a NAND gate 33a provided in the buffer amplifier 33 in the scanning signal line drive circuit 30, and a high level control signal is applied to the first gate wiring 51f of the first TFT 51, for example. Is applied, the first TFT 51 is turned on, and the high level signal of the first signal wiring 41a connected to the first TFT 51 in the first signal wiring group 41 passes through the source region 51b of the semiconductor layer 51a to the drain region 51c. In addition, the first isolation below the interlayer insulating film 61 via the first connection portion 45 provided on the interlayer insulating film 61 and the second contact hole 61b via the first contact hole 61a. The wiring 46 is given.

  The high level signal applied to the first isolation wiring 46 is provided to the third contact hole 61 d provided in the interlayer insulating film 61, the second connection portion 47 provided on the interlayer insulating film 61, and the interlayer insulating film 61. The second isolation wiring 48 provided below the interlayer insulating film 61 is provided through the fourth contact hole 61e. By supplying a high level signal to the second separation wiring 48, a high level signal is also applied to the branch portion 48 a connected to the gate electrode of the second TFT 52 and the end portion 48 b adjacent to the ground line 44. A high level signal is given to the gate wiring of the 3 TFT 53. In this case, since the second TFT 52 is composed of an n-type MOS transistor and the third transistor 53 is composed of a p-type MOS transistor, for example, the second TFT 52 is turned on and the third TFT 53 is turned off. As a result, the high level signal of the power supply line 43 is output to the output wiring 49 via the second TFT 52.

  On the other hand, when a low level control signal is applied to the first gate line 51f of the first TFT 51, the first TFT 51 is turned off, and a low level signal is applied to the first separation line 46 and the second separation line 48. Thus, the second TFT 52 is turned off and the third TFT is turned on. As a result, the low level signal of the ground line 44 is output to the output wiring 44 via the third TFT 53.

Such a circuit configuration is manufactured as follows. First, on the glass substrate 40a which is an insulating substrate, each semiconductor layer 51a, 52a, 53a constituting the first TFT 51, the second TFT 52, and the third TFT 53 is placed at a predetermined position by polysilicon which is crystallized by laser by 85 nm. Form to a certain thickness and shape. Next, a gate insulating film 51e made of SiO ₂ is laminated to a thickness of about 100 nm by the LPCVD method over the entire surface of the glass substrate 40a.

  In such a state, a thin film of Ta, Cr, or the like is deposited on the gate insulating film 51e by a sputtering method to a thickness of 200 nm, and then patterned into a predetermined shape by, for example, dry etching, so that the first TFT 51 One gate wiring 51f, first separation wiring 46, and second separation wiring 48 are formed.

  In this case, the second isolation wiring 48 that constitutes the second gate wiring is in a state of being electrically separated from the first isolation wiring 46 that also constitutes the second gate wiring. Even when the second separation wiring 48 is charged during the etching of 48, the amount of charge to be charged is small, and there is no possibility that the second TFT 52 and the third TFT 53 are electrostatically damaged.

Next, after the source region and the drain region are formed in each of the semiconductor layers 51a to 53a by ion implantation into the semiconductor layers 51a to 53a, activation annealing of the semiconductor layers 51a to 53a is performed. Thereafter, for example, SiO ₂ is deposited to a thickness of about 500 nm over the entire glass substrate 40a by the CVD method to form the interlayer insulating film 61. Then, first to ninth contact holes 61a to 61i are formed in predetermined positions in the formed interlayer insulating film 61, respectively.

  In such a state, Al is formed on the interlayer insulating film 61 by sputtering, and Al is filled in each of the first to ninth contact holes 61a to 61i formed in the interlayer insulating film 61. .

  After that, Al deposited on the interlayer insulating film 61 is patterned into a predetermined shape, whereby the first connection portion 45 that connects the first isolation wiring 46 and the drain region of the first TFT, the first isolation wiring 46 and the second A second connection portion 47 for connecting to the separation wiring 48, each signal wiring 41a of the first signal wiring group 41, a second signal wiring 42, a power supply line 43, an output wiring 49, and a ground line 44 are formed. Thereby, the circuit configuration shown in FIG. 4 is formed.

  In the NAND circuit 33a of the scanning signal line driving circuit 30, the second TFT 52 and the third TFT 53 for outputting the control signal are located at positions away from the first TFT 51 to which the control signal is input due to restrictions on the circuit pattern. Accordingly, the second gate wiring connecting the second TFT 52, the third TFT 53, and the first TFT 51 is lengthened. However, in the present embodiment, the second gate wiring formed longer on the gate insulating film 51e with respect to the second TFT 52 and the third TFT 53 having a small capacitance is separated from the first isolation wiring 46 and the second isolation on the gate insulating film 51e. The first separation wiring 46 and the second separation wiring 48 are electrically separated from the wiring 48 and are connected by the second connection portion 47 on the interlayer insulating film 61. Thereby, when patterning the second separation wiring 48 connected to the second TFT 52 and the third TFT 53, the amount of charge charged in the second separation wiring 48 is reduced. As a result, each of the gate capacitances is small, and there is no possibility that the second TFT 52 and the third TFT 53 connected only to the second separation wiring 48 without being connected to other capacitances are electrostatically damaged.

  The length of the second separation wiring 48 connected to the second TFT 52 and the third TFT 53 is set so that the second TFT 52 and the third TFT 53 are not electrostatically damaged by the charge charged during dry etching. That is, the length is set such that the semiconductor layer 52a of the second TFT 52 and the semiconductor layer 53a of the third TFT 53 having a small capacitance are not electrostatically damaged by the amount of charge charged over the entire second isolation wiring 48. The length of the second separation wiring 48, that is, the distance from the semiconductor layer 52 a of the second TFT 52 and the semiconductor layer 53 a of the third TFT 53 to the separation portion of the second separation wiring 48 and the first separation wiring 46 is the second separation wiring. Although it varies depending on the material of 48 itself, the etching conditions of the etching apparatus, etc., it is 150 to 350 μm, preferably 150 to 200 μm.

  As long as the second separation wiring 48 has such a length that can prevent electrostatic breakdown of the second TFT 52 and the third TFT 53, the connection between the second separation wiring 48 and the first separation wiring 46 is performed. The position of a certain second connection portion 47 is not particularly limited. However, the area of the scanning signal line driving circuit 30 is increased by disposing the second connection portion 47 between the first signal wiring group 41 and the second signal wiring 42 as in the above embodiment. Can be prevented.

  FIG. 6 is a schematic plan view showing another example of a specific configuration of a part of the NAND gate 33a in the scanning signal line driving circuit 30. FIG. In this circuit configuration, a fourth TFT 54 which is an N-type MOS transistor using the semiconductor layer 52a of the second TFT 52 constituting the NAND circuit 33a is formed, and further, a P connected to the output wiring 49 and the ground line 44 is formed. A fifth TFT 55 which is a type MOS transistor is provided.

  In the gate region of the semiconductor layer 52a in the fourth TFT 54, one end portion of the third third gate wiring 56 is opposed as a gate electrode through a gate insulating film. The third gate wiring 56 is provided below the interlayer insulating film 61. One end of the third gate wiring 56 facing the semiconductor layer 52a is parallel to the branch portion 48a of the second separation wiring 48 constituting the second gate wiring of the second TFT 52 and the third TFT 53, and the other The end portion is disposed between the ground line 44 and the output wiring 49 in parallel with the ground line 44 and the output wiring 49. A central portion connecting the end portions of the third gate wiring 56 is arranged in a state orthogonal to the output wiring 56.

  The fifth TFT 55 connected to the ground line 44 and the output wiring 49 has a semiconductor layer 55 a formed in a linear island shape extending between the ground line 44 and the output wiring 49. The configuration of the fifth TFT is the same as that of the first TFT 51 shown in FIG. The source region of the semiconductor layer 55a in the fifth TFT 55 is electrically connected to the ground line 44 on the interlayer insulating film 61 through a tenth contact hole 61j provided in the interlayer insulating film 61. The drain region is electrically connected to the output wiring 49 on the interlayer insulating film 61 through an eleventh contact hole 61 k provided in the interlayer insulating film 61. In the fifth TFT 55, the gate region of the semiconductor layer 55a is opposed to the end portion of the third gate wiring 56 as a gate electrode through a gate insulating film.

  The end portion of the third gate wiring 56 facing the gate region of the semiconductor layer 55a of the fifth TFT 55 is located at a position close to the semiconductor layer 55a via the twelfth contact hole 61m provided in the interlayer insulating film 61. It is connected to one end of the third connecting portion 56 on the film 61. The third connection portion 56 is formed in an island shape that forms a straight line parallel to the ground line 44, and the other end thereof is interlayer insulating via a thirteenth contact hole 61 n provided in the interlayer insulating film 61. The third connection wiring 57 on the film 61 is electrically connected to one end. The third connection wiring 57 is disposed so as to be orthogonal to the output wiring 49, the power supply line 43, the second signal wiring 42, and each signal wiring 41 a of the first signal wiring group 41.

  The second separation wiring 48 constituting the second gate wiring of the second TFT 52 and the third TFT 53 and the third gate wiring 56 of the fourth TFT 54 and the fifth TFT 55 are respectively set so that the difference in length is within a predetermined range. The length of is set.

  In the circuit configuration of such a configuration, when the second isolation wiring 48 becomes high level, the second TFT 52 that is an N-type MOS transistor is turned on and the third TFT 53 that is a P-type MOS transistor is turned off. Since the layer 52a is provided with the fourth TFT 54 which is an N-type MOS transistor, a high level signal is given to the third connection wiring 58, the third gate wiring 56 becomes high level, and the fourth TFT 54 is turned on. A current flows through the source region and the drain region of the semiconductor layer 52a. That is, a high level signal is output to the output wiring 49 only when the second separation wiring 48 and the third connection wiring 58 (and hence the third gate wiring 56) are both at a high level.

  On the other hand, when the third TFT 53 is turned on when the second separation wiring 48 becomes low level, or when the third connection wiring 58 (and hence the third gate wiring 56) becomes low level, the fifth TFT 55 changes. When turned on, a low level signal is output to the output wiring 49.

  The circuit configuration shown in FIG. 6 is also manufactured in the same manner as the circuit configuration shown in FIG. 4. The third gate wiring 56 and the third connection wiring 58 are similar to the second isolation wiring 48 and the first isolation wiring 46, for example. , Ta, Cr or the like. Similarly to the second connection portion 47, the third connection portion 57 is formed of, for example, Al, and at the same time when the second separation wiring 48 and the first separation wiring 46 are connected by the second connection portion 47, The third gate line 56 and the third connection line 58 are connected by the fourth connection part 57.

  In this case, each length is set so that the difference between the length of the second separation wiring 48 constituting the gate wiring of the second TFT 52 and the length of the third gate wiring 56 of the fourth TFT 54 falls within a predetermined range. ing. Thereby, when the second isolation wiring 48 and the third gate wiring 56 are patterned by dry etching, the difference in the amount of charge charged in the second isolation wiring 48 and the third gate wiring 56 is reduced, and the second TFT 52 and There is no possibility that a high voltage is applied to the semiconductor layer 52a constituting the fourth TFT 54 by the second separation wiring 48 and the third gate wiring 56, and thus electrostatic breakdown of the semiconductor layer 52a is prevented.

  The difference between the length of the second isolation wiring 48 and the length of the third gate wiring 56 is set in a range in which the semiconductor layer 52a is not likely to be electrostatically damaged, but the second isolation wiring 48 and the third gate wiring 56 It varies depending on the material, the etching conditions of the etching apparatus, and the like. The difference between the length of the second separation wiring 48 and the length of the third gate wiring 56 is 50 to 200 μm or less, preferably 50 to 100 μm or less.

  In the above embodiment, the TFT provided in the scanning signal line driving circuit in the liquid crystal display panel has been described. However, the present invention is not limited to this, and for example, in the case of a TFT provided in the data signal line driving circuit. It can also be applied to other semiconductor circuits.

  In the above embodiment, a TFT formed on a glass substrate has been described. However, the present invention can also be applied to a TFT formed on an insulating substrate in which an insulating film is provided on a plastic substrate.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  In a semiconductor circuit having a thin film transistor used for a display panel such as a liquid crystal display device and a manufacturing method thereof, electrostatic breakdown of the TFT can be prevented.

It is a schematic diagram which shows schematic structure of the liquid crystal display panel provided with the semiconductor circuit of this invention. It is a schematic diagram which shows the structure of 1 pixel of the liquid crystal display panel. It is a circuit diagram which shows the structure of the scanning signal line drive circuit provided in the liquid crystal display panel. It is a top view which shows an example of the principal part of the scanning signal line drive circuit. It is sectional drawing of the thin-film transistor used for the scanning signal line drive circuit. It is a top view which shows the other example of the principal part of the scanning signal line drive circuit.

Explanation of symbols

20 data signal drive circuit 30 scan signal drive circuit 45 first connection portion 46 first separation wiring 47 second connection portion 48 second separation wiring 51 to 55 TFT
51a Semiconductor layer 51b Source region 51c Drain region 51f 1st gate wiring 57 3rd connection part 61 Interlayer insulation film 61a-61k, 61m, 61n Contact hole

Claims (17)

An insulating substrate; a TFT having a semiconductor layer provided on the insulating substrate; a gate wiring connected to the gate electrode of the TFT; an interlayer insulating film covering the semiconductor layer and the gate wiring of the TFT; A semiconductor circuit having a wiring formed on an interlayer insulating film and electrically connected to a source region and a drain region in a semiconductor layer of the TFT via contact holes,
The gate wiring is electrically separated at a predetermined distance from the semiconductor layer of the TFT, and the mutually separated gate wiring portions are a pair of contacts provided in the interlayer insulating film. A semiconductor circuit, wherein the semiconductor circuit is electrically connected to each other by a hole and a connecting portion provided on the interlayer insulating film.   The semiconductor circuit according to claim 1, wherein the gate wiring is separated at a position 150 to 300 μm away from the semiconductor layer of the TFT.   The semiconductor circuit according to claim 2, wherein the gate wiring is separated at a position 150 to 200 μm away from the semiconductor layer of the TFT. An insulating substrate; a pair of TFTs formed by a semiconductor layer provided on the insulating substrate; a pair of gate wirings respectively connected to the gate electrodes of the TFTs; the semiconductor layer and the gate wirings And a wiring formed on the interlayer insulating film and electrically connected to a source region and a drain region of each TFT in the semiconductor layer through contact holes, respectively. And
Each of the gate wirings is electrically separated at a position away from the semiconductor layer by a predetermined distance, and the difference between the distances is within a predetermined range. .   The semiconductor circuit according to claim 4, wherein the difference in distance is 50 to 200 μm or less.   The semiconductor circuit according to claim 5, wherein the difference in distance is 50 to 100 μm or less.   Each of the gate wirings is electrically connected to a connecting portion provided on the interlayer insulating film via a contact hole formed in the interlayer insulating film, and the connecting portion is formed on the interlayer insulating film. The semiconductor circuit according to claim 4, wherein the semiconductor circuit is connected to a wiring provided on the gate insulating film through a contact hole. Forming a semiconductor layer constituting the TFT on an insulating substrate;
Covering the semiconductor layer with a gate insulating film;
Forming a gate wiring connected to the gate electrode of the TFT in a separated state on the gate insulating film;
Forming an interlayer insulating film covering the semiconductor layer and gate wiring of the TFT;
The interlayer insulating film includes first and second contact holes corresponding to a source region and a drain region in the semiconductor layer of the TFT, and third and fourth contact holes corresponding to the separated portions in the gate wiring. Forming each of
On the interlayer insulating film, wirings electrically connected to the source region and the drain region by the first and second contact holes are formed, respectively, and by the third and fourth contact holes, Forming a connection portion for electrically connecting the separated portions of the gate wiring;
A method for manufacturing a semiconductor circuit comprising:   The method of manufacturing a semiconductor circuit according to claim 8, wherein the gate wiring is separated from the semiconductor layer of the TFT by a distance of 150 to 300 μm.   The method for manufacturing a semiconductor circuit according to claim 9, wherein the gate wiring is separated from the semiconductor layer of the TFT by a distance of 150 to 200 μm. Forming a semiconductor layer on an insulating substrate;
Covering the semiconductor layer with a gate insulating film;
Forming a gate electrode of a pair of TFTs and a gate wiring connected to each gate electrode on the gate insulating film so as to have a predetermined length and a difference between the lengths within a predetermined range; When,
Forming an interlayer insulating film covering the semiconductor layer and the gate wiring;
Forming in the interlayer insulating film first and second contact holes corresponding to the source region and drain region of each TFT in the semiconductor layer,
Forming wirings connected to the source region and the drain region by the first and second contact holes, respectively, on the interlayer insulating film;
A method for manufacturing a semiconductor circuit comprising:   The method of manufacturing a semiconductor circuit according to claim 11, wherein the difference in length of each gate wiring is 50 to 200 μm or less.   The method for manufacturing a semiconductor circuit according to claim 12, wherein the difference in length of each gate wiring is 50 to 100 μm or less.   At least one of the gate wirings is connected to a connecting portion provided on the interlayer insulating film through a contact hole formed in the interlayer insulating film, and the connecting portion is formed in the interlayer insulating film. The method of manufacturing a semiconductor circuit according to claim 11, wherein the semiconductor circuit is connected to a wiring provided on the gate insulating film through a contact hole.   A semiconductor device provided with a plurality of semiconductor circuits according to claim 1.   The semiconductor device according to claim 15, wherein an arithmetic circuit is configured by the plurality of semiconductor circuits. The semiconductor device according to claim 15, wherein a driving unit of a liquid crystal panel is configured by the plurality of semiconductor circuits.

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