JP2002135071A - Clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate setting of a clamp voltage which restricts a leakage current by reducing the leakage current at a higher voltage than a clamp voltage Vc. SOLUTION: A current flows from a current source to a first transistor constituting a current mirror circuit, so that the current is mirrored to flow to a second transistor. By a clamp circuit for clamping a voltage at an output terminal connected to the second transistor to a predetermined voltage, a current flowing in the second transistor is reduced to 1/n, and a positive feedback circuit comprising the current mirror circuit for mirroring to a side of the first transistor is provided. When the output terminal is deviated from the clamp voltage, a current flowing through the second transistor to a side of the output terminal is increased abruptly by the positive feedback circuit, thereby setting the output terminal at the clamping voltage. Due to the characteristics, the leakage current flowing to a terminal side to be clamped can be reduced more than usual at a higher voltage than a clamp voltage Vc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clamp circuit for clamping an input terminal of a circuit to a predetermined voltage, for example.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a configuration example of a conventional clamp circuit. The current output from the current source 32 connected to the power supply 31 becomes the base-emitter current of the transistor Q2 and the collector current of the transistor Q1,
It flows to the GND side. Transistor Q1 and transistor Q
3 constitute a current mirror circuit, the same current as the current flowing through the transistor Q1 is applied to the transistor Q3.
From the output terminal 33 to the input terminal 3 of the circuit A, for example.
4 is input. The transistor Q2 is the transistor Q
1 and Q3 are supplied. Note that the circuit A has an internal resistance R.

Here, if the clamp voltage of the input terminal 34 (that is, the same as the clamp voltage of the output terminal 33) is Vc, at that time, the clamp current Ic flows from the output terminal 33 to the input terminal 34 through the transistor Q3. At this time, when the base potential of the transistor Q1 and the base potential of the transistor Q3 are the same, the same current
1 and Q3, but when the input terminal 34 becomes lower than the clamp voltage, the base potential of the transistor Q3 increases, thereby maintaining the same base potential as the base potential of the transistor Q1.
Supplies a current larger than the clamp current Ic from the output terminal 33 to the input terminal 34 side, and clamps the input terminal 34 to a predetermined potential.

By the way, I1 is the current supplied from the current source 32, Io1 is the output current from the output terminal 33, A is the junction area of the transistor Q1, and Is is the transistor Q1.
Assuming that the saturation current per unit area, VBE is the base-emitter voltage of the transistor Q1, Vo1 is the terminal voltage of the output terminal 33, and VT is the thermal voltage of the transistor Q1.
Equation (1) described below holds.

Io1 = AIs · exp (VBE (Q1)
Vo1 / VT) VBE = VTln (I1 / AIs is substituted into the above equation, Io1 = AIsexp (((VTln (I1 /
AIs) · Vo1) / VT) / VT) By transforming this, Io1 = I1 / exp (Vo1 / VT) (1) When this equation (1) is represented in a graph, it is shown in (1) of FIG. It can be seen that the output terminal current Io1 rises relatively slowly with respect to the change in the output terminal voltage Vo1. However, the horizontal axis of FIG. 2 indicates the output terminal voltage Vo1, and the vertical axis indicates the output terminal current Io1.

[0006]

As described above, in the conventional clamp circuit, the output terminal current Io1 rises relatively slowly with respect to the change of the output terminal voltage Vo1, so that the voltage higher than the clamp voltage Vc (for example, 0 V). Even on the right side of FIG. 2, since a considerable amount of leak current flows, it is difficult to set a clamp voltage that suppresses the leak current, and in some cases, there is a problem that a clamp circuit as designed cannot be made.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to reduce the leakage current to the terminal when the terminal voltage to be clamped is higher than the clamp voltage Vc. Therefore, it is an object of the present invention to provide a clamp circuit which can easily set a clamp voltage while suppressing a leak current.

[0008]

In order to achieve the above object, a feature of the present invention is that a current is supplied from a current source to a first transistor constituting a current mirror circuit, whereby the current is mirrored. To a second transistor, and clamps the voltage of the output terminal connected to the second transistor to a predetermined voltage so that the base potentials of the first and second transistors are always the same. In the above, a positive feedback circuit including a current mirror circuit that reduces the current flowing through the second transistor to 1 / n and flows the current to the first transistor in a mirror manner is provided.

A second feature of the present invention is that a current limiting resistor is inserted between a common base of the first transistor and the second transistor to connect a base between the first transistor and the second transistor. The connection is made by the current limiting resistor.

According to a third aspect of the present invention, the first and second transistors constituting the current mirror circuit, the third transistor for supplying a base current to the first and second transistors, and the first and second transistors are provided. A current limiting resistor connecting between the bases of the second transistor, a fourth transistor connected in series with the second transistor, and supplying a power supply current to the second transistor; a fifth transistor configured to form an n-times current mirror circuit and to supply a current 1 / n times the current flowing to the fourth transistor to the first transistor side;
It comprises a current source for supplying a current to the first transistor, and an output terminal connected to the second transistor, and clamps the output terminal to a predetermined voltage.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the clamp circuit of the present invention. The clamp circuit according to the present embodiment includes a clamp unit 1 that clamps the output terminal 13 to a predetermined voltage, and a feedback unit 2 that positively feeds the output current of the output terminal 13 of the clamp unit 1 back to the clamp unit 1.

The clamp unit 1 includes a power supply 11, a current source 12, transistors Q4 and Q8 constituting a current mirror circuit, a current limiting resistor R1, a transistor Q5 for supplying a base current to the transistors Q4 and Q8, an input terminal 14 for clamping, and the like. It has an output terminal 13 to be connected.

The feedback section 2 comprises a current mirror circuit having a magnification of n and comprising transistors Q6 and Q7.

Next, the operation of this embodiment will be described.
The current from the current source 12 connected to the power supply 11 becomes the base current of the transistor Q5 and the collector current of the transistor Q4. Transistors Q4 and Q8 are transistors Q
5 supplies a base current to form a current mirror circuit, and a current flowing through the transistor Q4 is mirrored and flows through the transistor Q8. Here, assuming that the clamp voltage of the output terminal 13 is Vc (for example, 0 V),
Is Vc, the base potentials of the transistors Q4 and Q8 are the same.

Here, the output terminal 13 is connected to the clamp voltage Vc.
As the voltage further decreases, the current flowing from the transistor Q8 to the output terminal increases accordingly. This transistor Q
8 flows through the transistor Q7 constituting the feedback unit 2.
, The current flowing through the transistor Q7 also increases. Since the current flowing through the transistor Q7 is mirrored to 1 / n and flows through the transistor Q6, the current of the transistor Q6 also increases. When the current flowing through the transistor Q6 increases, the transistors Q5 and Q
4, a positive feedback loop of the current is formed, and the current flowing from the output terminal 13 to the input terminal 14 through the transistor Q8 rapidly until the base potentials of the transistors Q4 and Q8 become the same. Increases, and the output terminal 13, that is, the input terminal 14 is connected to the clamp voltage V.
c. The resistor R1 limits the current so that the current does not increase infinitely by the positive feedback loop, and sets the rising characteristic of the current output from the output terminal 13.

By the way, I1 is the current of the current source 12, Io
2 is the output current from the output terminal 13, A is the transistor Q
4, the area of the junction of Q8, Is is the transistor Q4, Q8
8, the saturation current per unit area, VBE is the transistor Q4, the base-emitter voltage of Q8, and Vo2 is the output terminal 1.
Assuming that the terminal voltage of the terminal 3, the VT is the thermal voltage of the transistors Q4 and Q8, β is the amplification factor of the transistor Q8, R1 is the resistance of the resistor R1, and n is the magnification of the current mirror circuit composed of the transistors Q6 and Q7, is described below. Equation (2) holds.

Io2 = AIs.exp (VBE (Q4)
−R1 · Io2 / β · Vo2) By substituting the relationship of VBE = VTln ((I1 + Io2 / n) / AIs) into the above equation, Io2 = AIs · exp
(((VTln ((I1 + Io2 / n) / AIs) -I
o2 · R1 / β−Vo2) / VT) By transforming this, Io1 = I1 / (exp ((Vo2 / VT + Io2R1 / βVT) −1 / n) (2) When this equation (2) is expressed in a graph, 2 shows that the output terminal current Io2 rapidly rises in response to a change in the output terminal voltage Vo2, and the same leakage current is obtained at the same clamp voltage as in the related art. Also, the output terminal current Io2 immediately converges to 0 at a voltage higher than the clamp voltage Vc.
If a voltage higher than Vc is set as the clamp voltage, the leak current can be extremely reduced. However, the horizontal axis of FIG. 2 indicates the output terminal voltage Vo2, and the vertical axis indicates the output terminal current Io.
2 is shown.

According to the present embodiment, a positive feedback circuit is provided in the clamp circuit, and when the output terminal 13 deviates from the clamp voltage Vc, the output current from the output terminal 13 is changed as shown in FIG.
By providing the characteristic of rapidly increasing the output terminal 13 as shown by, the characteristic that the output terminal 13 is clamped to the clamp voltage Vc is provided, so that the leakage current from the output terminal 13 is slightly higher than the clamp voltage Vc. Can be made extremely small. This makes it possible to easily set the clamp voltage while suppressing the leak current.

[0019]

As described above in detail, according to the clamp circuit of the present invention, by providing the characteristic that the terminal voltage to be clamped is higher than the clamp voltage Vc and the leakage current to the terminal side is reduced. In addition, it is possible to easily set the clamp voltage while suppressing the leak current.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of a clamp circuit of the present invention.

2 is a characteristic diagram showing a relationship between an output terminal voltage and an output terminal current of the circuit shown in FIG. 1 and the circuit shown in FIG. 3;

FIG. 3 is a circuit diagram showing a configuration example of a conventional clamp circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clamp part 2 Feedback part 11 Power supply 12 Current source 13 Output terminal Q4-Q8 Transistor

Claims (3)

[Claims] 1. A current flowing from a current source to a first transistor constituting a current mirror circuit, the current is mirrored and passed to a second transistor, and an output terminal of an output terminal connected to the second transistor is mirrored. In a clamp circuit for clamping a voltage to a predetermined voltage so that the base potentials of the first and second transistors are always the same, the current flowing through the second transistor is reduced to 1 / n and the first transistor A clamp circuit, comprising: a positive feedback circuit including a current mirror circuit that mirrors and flows to a side. 2. A current limiting resistor is inserted between a common base of the first transistor and the second transistor, and a current limiting resistor connects a base between the first transistor and the second transistor. The clamp circuit according to claim 1, wherein the clamp circuit is connected. 3. A first and second transistor constituting a current mirror circuit; a third transistor for supplying a base current to the first and second transistors; and a base of the first and second transistors. A current limiting resistor connecting the second transistor, a fourth transistor connected in series with the second transistor and supplying a power supply current to the second transistor, and an n-times current mirror circuit with the fourth transistor. And the current flowing through the fourth transistor is 1 /
a fifth transistor that flows n times more current to the first transistor side, a current source that supplies a current to the first transistor, and an output terminal connected to the second transistor, A clamp circuit for clamping the output terminal to a predetermined voltage.