JP2000312486A - Controller for pwm power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller for a PWM power converter which suppresses waveform distortion of a current, even when the pulse width of a command PWM(pulse-width modulation) becomes narrower. SOLUTION: A controller detects the difference in level between a command PWM signal held by a pulse holding section 21 and a phase voltage level signal Uf by means of an error detecting section 22, and the error time is measured and stored at both turn-on time and turn-off time, by means of the counting function of a pulse correcting section 23. Then the controller corrects the turn on/off timings of the held PWM signal by the time corresponding to the stored error amount and outputs the corrected signal as a corrected PWM signal (Uc).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to pulse width modulation (P
The present invention relates to a method for generating a PWM pulse of a power converter controlled by a WM signal, and more particularly to a PWM method for compensating for a dead time.
The present invention relates to a control device for an M-modulation type power converter.

[0002]

2. Description of the Related Art In PWM control of a power converter, it is essential to add a dead time to a PWM signal in order to prevent a short circuit due to a switching delay of a switching element connected in series. However, the influence of the dead time causes a decrease in the output voltage of the power converter and causes a distortion in the load current waveform. Conventionally, there are many known methods for compensating for the influence of the dead time, such as a method of correcting a voltage command value by software and a method of correcting the output voltage of a power converter by feedback and hardware. I have. Note that the dead time compensation method using hardware includes MURAI et al; Waveform Distor
tion and Correction Circuit for PWM Inverters with
Switching Lag-Times; IEEE TRANSACTION ON INDUSTRY
APPLICATION, VOL.IA-23, NO.5, SEPTEMBER / OCTOBER 1987
There is.

[0003]

As shown in FIG. 7, in the above-mentioned prior art compensation system, the pulse width error between the command PWM signal Ur and the phase voltage level detection signal Uf is determined by a block 81 on each of the ON side and the OFF side. To be detected. The error time is measured by counting the pulse width error in a block 82 constituted by a counter, and the pulse width of the PWM signal is corrected by a time corresponding to the error time. That is, in this method, as shown in the time chart of FIG. 8, in the normal state, the on / off timing of the command PWM signal is output in accordance with the error times t1 and t2 held by the counter as in the section A, and the corrected PWM signal Uc is output. Thus, the command PWM signal width (t0) is made equal to the phase voltage level detection signal width (t0). However, when the pulse width t4 of the command PWM signal Ur is shorter than the error time t3 as in the section B, the error time cannot be completely corrected, and the remaining time (t3-t4) is reflected in the next section C. become. That is, in the section B, a pulse missing phenomenon occurs in the corrected PWM signal Uc, and in the period C in which the next correction pulse is generated, the phase difference from the fall of the command PWM signal to the fall of the corrected PWM signal is reduced. Since this is different from the normal state, there is a problem that the waveform of the current flowing through the motor is disturbed.

An object of the present invention is to provide a correction PWM signal which does not cause a pulse omission phenomenon and has a phase difference similar to that in a normal state even when the pulse width of a command PWM signal is shorter than the stored error time. Accordingly, it is an object of the present invention to provide a PWM modulation type power converter control device in which current waveform distortion is suppressed.

[0005]

In order to achieve the above object, there is provided pulse holding means for holding a command PWM signal at an input stage, and an error detecting means which receives the held PWM signal and a phase voltage level detection signal as inputs. , The time at which the two signal levels are different is detected as an error. This error time is measured by a counting function, and constitutes a pulse correction means for outputting a corrected PWM signal obtained by correcting ON and OFF of the held PWM signal by the obtained error time. The pulse holding unit accepts the input of the command PWM signal only when the level of the command PWM signal and the level of the corrected PWM signal match,
In the case of a mismatch, the input of the command PWM signal is prohibited, so that even if the command PWM signal having a short width is input, the correction PWM signal is output.
Until the M signal changes, the held PWM signal does not change, so that pulse omission is prevented.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a power converter control device using the present invention will be described below. FIG. 2 is an overall configuration diagram of a motor control system using the present invention. The PWM signal generating unit 1 also has an arithmetic function of a microcomputer or the like, and outputs a voltage command value by performing a control calculation of the rotation speed and current of the motor 5 and converts the voltage command value to a PWM
The signal is M-modulated and command PWM signals Ur, Vr, Wr for each phase are output as a pulse train. The PWM pulse correction unit 2 feeds back the command PWM signals Ur, Vr, Wr and the phase voltage level signals Uf, Vf, Wf provided from the phase voltage level detection unit 6 for each phase, and detects an error between these two signals. In addition to correcting the pulse width of the command PWM signal, the PWM signals Up, Un, Vp, Vn, and W for three phases in a complementary relationship with a dead time added from the corrected PWM signal.
Outputs p and Wn. The amplifier 3 amplifies each of the PWM signals to turn on / off the six switching elements U, V, W, X, Y, and Z of the power converter 4 and a predetermined voltage. This is applied to the motor 5. The phase voltage level detector 6 receives the voltage output from the power converter 4 as an input, and the output potential of the power converter 4 becomes P
It detects whether the potential is the side potential or the N-side potential, and feeds it back to the PWM pulse correction unit 2. Next, P
The schematic configuration of the WM pulse correction unit 2 will be described with reference to FIG.
The PWM pulse correction unit 2 shows three-phase PWM pulse correction, but since each phase has the same configuration, the following U
The phase PWM pulse correction circuit will be described. First, the pulse holding unit 21 holds the command PWM signal Ur input as a pulse train, and the held PWM signal and the corrected PWM signal (Uc) output from the pulse correction unit 23 have the same signal level. The command PWM signal is held only in the state. In other words, immediately after the command PWM signal changes, the signal level of the held PWM signal and the signal level of the corrected PWM signal (Uc) do not match, so that the command PWM signal is not accepted. Thereafter, when the level of the correction PWM signal changes, the command PWM signal is again ready to be accepted. The error detection unit 22 includes the pulse holding unit 21
Receives as input the held PWM signal output as a pulse train and the phase voltage level signal Uf of the pulse train, and detects an error between the signals at the ON point and the OFF point of each signal. The pulse correction unit 23, which receives the error signal and the held PWM signal, measures and stores an error for each of ON / OFF by a counting function, and holds the pulse for a time corresponding to the stored error amount.
The on / off timing of the WM signal is corrected and output as a corrected PWM signal (Uc). This corrected PWM
The dead time generator 24 that receives the signal (Uc) as an input
Complementary PWM signals Up and Un whose ON is delayed by a preset dead time are output. The suppress signal controls the output and stop of the complementary PWM signals Up and Un, and is used as a signal for initializing the pulse holding unit 21 and the pulse correction unit 23 at the time of stop.
Next, FIG. 3 shows a specific example of the circuit of the phase voltage level detection unit 6. Since all three phases have the same configuration, the U-phase phase voltage level detection circuit will be described below. The U-phase converter 4u has an upper arm U and a lower arm X connected in series between DC potentials P and N, and its output voltage is a P potential when the upper arm U is on and an N potential when the lower arm is on. become. For the detection of the phase voltage level, a voltage obtained by dividing the DC voltage between PN by the resistors 61 and 62 and a voltage obtained by dividing the output voltage by the resistors 63 and 64 are inputted to the comparator 65. As a result, the output of the comparator 65 becomes high level when the output voltage is at the P potential,
When the output voltage is at the N potential, a low level is output. Next, an example of a specific circuit of the PWM pulse correction unit 2 is shown in FIG. 4, and the circuit operation will be described with reference to a time chart of FIG. First, while the output is stopped while the suppress signal in FIG. 5 is at the high level, the flip-flop 215 operates to hold the command PWM signal Ur in the pulse holding unit 21 when the command PWM signal Ur is at the high level. Flip-flop 2
On the other hand, when the command PWM signal Ur is at a low level, the flip-flop 215 is cleared by the AND circuit 211, so that the held PWM signal (Um) as an output is initialized to the same signal level as the command PWM signal Ur. Is becoming Also, the counter 21 of the pulse correction unit 23
3 stops the counter by loading the command PWM signal level as data when the suppress signal is at a high level, and also outputs a corrected PWM signal, which is an inverted signal of the most significant bit (MSB) of the count value, with the command PWM signal Ur. Initialized to the same signal level. Further, the dead time generator 24 generates complementary PWM signals Up and Un in which a dead time is provided to the corrected PWM signal (Uc), and the output is turned off by the AND circuits 244 and 245 during stop. When the suppress signal changes from the high level to the low level to be activated, the exclusive OR circuit 221 in the error detection unit 22 detects an error in the signal level between the held PWM signal (Um) and the phase voltage level signal Uf. , Error detection signal (Ue)
To enable the EN terminal of the counter 231.
As a result, the counter 231 counts the clock according to the held PWM signal level input to the counting direction terminal U / D only during the period t1 when the error signal disappears. Then, the command P
When the error detection signal (Ue) is input when the WM signal Ur changes to low level, the counter 231 counts down. Since the MSB of the counter changes when the count value of the counter 231 crosses zero, the corrected PWM signal (Uc) changes. The differentiating circuit 241 of the dead time generator 24 outputs the corrected PWM signal (U
When c) captures a change, a pulse-like load signal is output to the counter 242. The counter 242 loads the dead time value set by the load signal, sets the carry signal (Ca) to a low level, starts counting, and sets the carry signal to a high level when the counting of the dead time ends, and counts. Stop operation.
Therefore, the counters 24 are provided by the AND circuits 244 and 245.
2 during the low level of the carry signal, the PWM signal U
Since both the p and Un signals are turned off, a dead time can be secured. After the counting operation of the counter 242 is completed and the dead time is secured, when the PWM signals Up and Un are output and the voltage level detection signal Uf changes, the error signal Ue also disappears, and the operation of the pulse correction counter 231 stops. Thereafter, by repeating the same operation, the correction operation of the command PWM signal is performed. Next, an operation when the pulse width of the command PWM signal Ur is reduced will be described with reference to FIG. Such a state is an example in which the pulse width t1 of the command PWM signal which becomes low level at the point in time Pa becomes shorter than the stored error time t2, as shown at the point Pa in FIG. First, when the command PWM signal Ur goes low at the point of Pa, the held PWM signal (Um) also goes low, an error signal (Ue) is output, and the counter 231 starts counting down. At this point hold P
Since the level of the WM signal is different from the level of the corrected PWM signal, the output of the exclusive OR circuit 213 becomes high level, and the OR circuit 214 causes the flip-flop 21
5 is stopped. Even at the time point Pb when the command PWM signal changes to the high level, the counter 231 is just before the zero cross point, and the corrected PWM signal (Uc) maintains the high level. Therefore, the flip-flop 215
, The change of the command PWM signal Ur is not accepted, and the error signal Ue is continuously output. When the count value of the counter 231 crosses zero, the correction P
When the WM signal (Uc) changes to the low level, the clock of the flip-flop 215 is supplied, and the holding PWM is held.
The signal (Um) also changes to a low level. As a result, the error signal (Ue) disappears and the counter 231 stops. On the other hand, the dead time generator 24 starts operating in response to the corrected PWM signal (Uc) changed at the point Pc, turns off the complementary PWM signal Up, and changes the level of the voltage level detection signal Uf to the low level at the point Pd. Therefore, the error detection signal (Ue) is output at the point of time Pd, and the counter 231 starts the counting operation. The counter 231 changes the corrected PWM signal (Uc) when the count value crosses zero,
As a result, the operation of the dead time generation circuit 23 started is completed, and the time until Pe at which the level of the voltage level detection signal Uf changes is stored. Therefore, even when the pulse width of the command PWM signal is shortened,
The time delay from the falling point of the command PWM signal to the falling point of the phase voltage (falling point of the voltage level detection signal Uf) is the same time (TL) as in the normal operation, which may disturb the phase relationship between the phases. Can output a PWM signal. In this example, the corrected PWM changed at the time point Pc.
Before the dead time securing operation started by the signal (Uc) ends, the level of the corrected PWM signal (Uc) changes again.
Will reload the data, and the dead time securing operation will be restarted from that point. On the other hand, when the level of the corrected PWM signal (Uc) changes again after the end of the dead time securing operation, the dead time generating section 24 performs the same operation as in the normal operation. In FIG. 6, the operation when the command PWM signal Ur is low and the pulse width is short has been described. However, the same operation is performed when the command PWM signal Ur is high and the pulse width is short. Things.

[0007]

According to the present invention, the input command PWM
The signal is held, and the output corrected PWM signal is the command PWM.
Since the level change of the held PWM signal is prohibited until the signal becomes the same level as the signal, even if the command PWM signal of a narrow width is input, the pulse is not generated in the corrected PWM signal.
Since the phase relationship is not disturbed, there is an effect that distortion of the current waveform can be suppressed. In addition, when the power converter is stopped, the signal levels of both the held PWM signal and the corrected PWM signal are set to the same level as the command PWM signal, so that the PWM is stable at any timing even when the power converter is started.
There is an effect that a signal can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PWM pulse correction unit according to the present invention.

FIG. 2 is an overall configuration diagram of a motor control system using the present invention.

FIG. 3 is a level detection circuit of a phase voltage output from a power converter.

FIG. 4 is a detailed circuit diagram of the block in FIG. 1;

FIG. 5 is a time chart for explaining an operation at the time of startup in the circuit of FIG. 4;

FIG. 6 is a time chart for explaining an operation when a narrow-width command PWM signal is input in the circuit of FIG. 4;

FIG. 7 is a block diagram of a conventional PWM pulse correction device.

8 is a time chart for explaining the operation of the device shown in FIG. 7;

[Explanation of symbols]

1 ... PWM signal generator, 2 ... PWM pulse corrector, 3 ...
Amplifier, 4 power converter, 5 motor, 6 phase voltage level detector, 21 pulse holder, 22 error detector, 2
3 ... Pulse correction unit, 24 ... Dead time generation unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seiji Ishida 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Fujii 7-1-1 Higashi Narashino, Narashino City, Chiba Prefecture 1.Industrial Equipment Division, Hitachi, Ltd. (72) Inventor Hiroyuki Tomita 7-1-1, Higashi Narashino, Narashino City, Chiba Prefecture (72) Inventor, Masahiro Hiraga 7, Nagoya Higashi Narashino City, Chiba Prefecture No. 1-1 Hitachi Keiyo Engineering Co., Ltd. (72) Inventor Tomofumi Okubo 7-1-1 Higashi Narashino, Narashino-shi, Chiba F-term in the Industrial Equipment Division, Hitachi, Ltd. 5H007 AA06 BB06 CA01 CB05 CC23 DB07 DC05 EA02

Claims (2)

[Claims] 1. A command PWM signal generating means for outputting a command PWM signal for driving a power converter, an output voltage level detecting means for detecting a voltage level of an output phase voltage of the power converter, and the command PWM. PWM pulse correction for outputting a corrected PWM signal in which the pulse width of the command PWM signal is corrected so that the pulse width of the command PWM signal output by the signal generating means is equal to the width of the detected voltage level detected by the output voltage level detecting means. In the control device for a power converter provided with means, the PWM pulse correction means inhibits a level change of the command PWM signal until the level of the command PWM signal as input and the level of the corrected PWM signal as output coincide. A control device for a PWM modulation type power converter, comprising a pulse holding means. 2. The PWM pulse correcting means according to claim 1, wherein, during the output stop period of the power converter, the signal level of the output corrected PWM signal is the same as the signal level of the input command PWM signal. A control device for a PWM-modulated power converter characterized by initializing the state of the pulse holding means.