JP2000164651A - Multilayer interconnection substrate for wafer collective contact board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer interconnection substrate, etc., for a wafer collective contact board, wherein even with a chip comprising a shorted point in an internal circuit, problems such as the internal circuit of other chip being destroyed or other chip malfunctions being avoided on a multilayer interconnection substrate side. SOLUTION: In a multilayer interconnection substrate constituting a part of a wafer collective contact board used for collectively testing semiconductor devices formed on a wafer in multiple numbers, a resistor, for example, is provided on each I/O branch wiring 17 branching from an I/O common wiring. Here, the I/O branch wiring 17 is, for example, such a wiring as being comprised of a multilayer structure where Au/Ni/Cu/Cr are laminated, and Au/Ni/Cu is etched at a part of the wiring to provide Cr resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer forming a part of a wafer batch contact board used for collectively performing a test (inspection) of a large number of semiconductor devices formed on a wafer in a wafer state. The present invention relates to a multilayer wiring board for a collective contact board, a method for manufacturing the same, and the like.

[0002]

2. Description of the Related Art Inspection of a large number of semiconductor devices formed on a wafer is roughly classified into a product inspection (electrical characteristic test) using a probe card and a burn-in test which is a reliability test performed thereafter. The burn-in test is one of screening tests performed to remove a semiconductor device having an intrinsic defect or a device which causes a time- and stress-dependent failure from manufacturing variations. The burn-in test can be said to be a thermal acceleration test, while the inspection with a probe card is an electrical characteristic test of the manufactured device.

[0003] The burn-in test is an ordinary method (one chip) in which a wafer is cut into chips by dicing after a electrical characteristic test performed for each chip by a probe card, and the packaged products are subjected to a burn-in test one by one. Burn-in systems are not feasible in terms of cost. Accordingly, development and commercialization of a wafer batch contact board (burn-in board) for simultaneously performing a burn-in test of a large number of semiconductor devices formed on a wafer at once are being promoted (Japanese Patent Laid-Open No. 7-2310).
No. 19). Wafer and batch burn-in systems using wafer batch contact boards are not only highly feasible in terms of cost, but also important technologies for realizing the latest technological flows such as bare chip shipping and bare chip mounting. . The wafer batch contact board is different from the conventional probe card in required characteristics in that the wafer is inspected in a batch and used in a heating test, and the required level is high. When the wafer batch contact board is put into practical use, the product inspection (electrical characteristic test) conventionally performed by the probe card can be performed by the wafer batch.

FIG. 9 shows a specific example of a wafer batch contact board. As shown in FIG. 9, the wafer batch contact board is formed on a multilayer wiring board for a wafer batch contact board (hereinafter, referred to as a multilayer wiring board) 10 via an anisotropic conductive rubber sheet 20 via a membrane ring 3 with bumps.
It has a structure in which 0 is fixed. The membrane ring 30 with a bump serves as a contact portion that directly contacts the device under test. In the membrane ring 30 with bumps, a bump 33 is formed on one surface of a membrane 32 stretched over the ring 31 and a pad 34 is formed on the other surface.
Are formed. The bumps 33 are formed on the periphery or center line of each semiconductor device (chip) on the wafer 40 (approximately 600 to 1000 pins per chip, the number of which is the number of chips multiplied by the number of chips on the wafer 40). ), The same number of pads are formed at corresponding positions. The multilayer wiring board 10 has a wiring for applying a predetermined burn-in test signal or the like to each bump 33 isolated on the membrane 32 via a pad 34 on an insulating substrate. The multilayer wiring board 10 has a multilayer wiring structure because the wiring is complicated. The anisotropic conductive rubber sheet 20 is an elastic body (consisting of silicon resin, in which metal particles are embedded in pad electrode portions) having conductivity only in a direction perpendicular to the main surface, and is formed on the multilayer wiring board 10. (Not shown) and the pads 34 on the membrane 32 are electrically connected. The anisotropic conductive rubber sheet 20 has a convex portion formed on its surface, and the pad 3 on the membrane 32
By contacting the bumps 4, irregularities on the surface of the semiconductor wafer 40 and variations in the height of the bumps 33 are absorbed, and the pads on the semiconductor wafer and the bumps 33 on the membrane 32 are reliably connected.

[0005] Each semiconductor device (chip) is formed with a pad electrode serving as a power supply, a ground, and a signal input / output terminal (I / O terminal) of the integrated circuit (power supply pad, ground pad, I / O pad). The bump electrodes of the wafer batch contact board are formed in one-to-one correspondence and connected to all pad electrodes of the semiconductor chip. In the multilayer wiring board of the wafer batch contact board, the power supply wiring, the ground wiring, and the signal input / output wiring (I / O wiring) are shared in order to reduce the number of wirings.

[0006]

In the above-described wafer batch burn-in test or the like, since all semiconductor devices or a plurality of semiconductor devices formed on a wafer are measured simultaneously, defective semiconductor devices (particularly semiconductor devices) If there is a semiconductor device with a short circuit between the wiring in the device), the current leaking from the short circuit of the defective semiconductor device may interfere with the measurement of other semiconductor devices, or a large current may flow into the internal circuit. There is a problem that the semiconductor device may flow in and destroy other semiconductor devices. In order to avoid this problem, a technique of providing a fuse in each semiconductor device, more specifically, a technique of providing a fuse in a part of a wiring connecting a power supply pad on the semiconductor device and an internal circuit has been proposed (Japanese Patent Application Laid-Open No. 9-1990). -199672). However, as shown in FIG. 10, the power supply wiring, the ground wiring, and the I / O wiring in the multilayer wiring board are shared by the pads on the semiconductor devices in the same column or the same row (common wiring). Therefore, when a short circuit occurs between a power supply wiring (or a ground wiring) and an I / O wiring due to an internal circuit failure in a certain semiconductor device, power is supplied to the shorted I / O wiring. And excessive current flows through the I / O wiring via the I / O pad on the side of the multilayer wiring board which is electrically connected to the I / O pad in the defective semiconductor device. . At this time, in the multilayer wiring board, as described above, the I / O wiring is used as a common wiring, and the respective I / O branch wirings 17 provided from the I / O wiring corresponding to the respective semiconductor devices are provided. Are connected to the I / O pads as shown in FIG. Therefore, when an excess current flows through the I / O wiring in the multilayer wiring board, the excess current flows toward each I / O branch wiring 17 and each I / O pad connected thereto, so that this excess current flows. There is still a problem that a large current flows through all the semiconductor devices connected to the / O wiring, which may destroy the internal circuit or cause a malfunction, thereby making it impossible to perform an accurate burn-in test. is there.

The present invention has been made under the above-mentioned background, and even when a semiconductor device having a short-circuit portion exists in an internal circuit, the internal circuit of another semiconductor device is destroyed, or another semiconductor device is damaged. A first object of the present invention is to provide a multilayer wiring board for a wafer batch contact board which can avoid a problem that a semiconductor device malfunctions on the multilayer wiring board side. It is a second object of the present invention to provide a manufacturing method capable of realizing the multilayer wiring board for a wafer batch contact board with a simple process without adding a complicated process.

[0008]

Means for Solving the Problems To achieve the above object, the present invention has the following configuration.

(Structure 1) A multilayer wiring board which constitutes a part of a wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer, wherein the multilayer wiring board is A plurality of pads provided on the multilayer wiring board corresponding to the respective pads in the plurality of semiconductor devices, and the pads to which the same signal or power is input / output in the plurality of semiconductor devices are electrically common. A common line to be connected; a branch line branched from the common line to connect between the plurality of pads and the common line; and a resistance element provided on the branch line. Multi-layer wiring board for wafer batch contact board.

(Structure 2) The common wiring is a signal input / output wiring (I / O wiring), and a resistance element is provided on an I / O branch wiring branched from the I / O common wiring. 2. The multilayer wiring board for a wafer batch contact board according to Configuration 1.

(Structure 3) Structure 1 or 2, wherein a resistor is provided in the uppermost layer wiring in a wafer batch contact board having a structure in which wiring is laminated via an insulating layer.
A multilayer wiring board for a wafer batch contact board as described in the above.

(Structure 4) A multilayer wiring for a wafer batch contact board, comprising a step of processing a part of the wiring in a wafer batch contact board having a structure in which wirings are stacked via an insulating layer to provide a resistor. Substrate manufacturing method.

(Structure 5) A multilayer wiring for a wafer batch contact board, comprising a step of etching a part of the wiring in a wafer batch contact board having a structure in which wirings are stacked via an insulating layer to provide a resistance. Substrate manufacturing method.

(Structure 6) A structure comprising a step of forming a wiring having a multilayer structure in which two or more different materials are stacked, and a step of providing a resistor by etching a part of the wiring for the wiring. 6. The method for manufacturing a multilayer wiring board for a wafer batch contact board according to claim 5.

(Structure 7) A step of forming a wiring having a multilayer structure in which Au / Ni / Cu / Cr is laminated, and a step of providing a Cr resistance by etching Au / Ni / Cu in a part of the wiring for the wiring. 7. The method for manufacturing a multilayer wiring board for a wafer batch contact board according to Configuration 6, comprising:

(Structure 8) A wafer batch contact board, comprising: the multilayer wiring board for a wafer batch contact board according to any one of Structures 1 to 3; and a bumped membrane ring that serves as a contact portion for directly contacting the device under test. .

[0017]

According to the present invention, even if a semiconductor device having a short-circuit portion exists in an internal circuit, another semiconductor device can be provided by providing a resistance to a part of the wiring in the multilayer wiring board for a wafer batch contact board. Problems such as destruction of the internal circuit of the device and malfunction of other semiconductor devices can be avoided on the multilayer wiring board side.

In one embodiment of the present invention, the resistor is formed as a part of a material and a structure for forming a wiring, so that a resistor can be formed by forming a wiring and processing a part of the wiring. In another aspect of the present invention, the resistance portion is made of a metal constituting the lowermost layer of the wiring having a multilayer structure, whereby the resistance can be formed by etching, the resistance can be formed directly on the substrate, and the resistance can be closely adhered. Is also good.

[0019]

Embodiments of the present invention will be described below.

The multilayer wiring board for a wafer batch contact board of the present invention is characterized in that a resistor is provided in a part of the wiring (part of the wiring including the middle of the wiring and the end of the wiring).

Here, the wiring material / wiring structure and the method of forming the resistor are not particularly limited. For example, as shown in FIG. 1, a wiring 15 having an Au / Ni / Cu / Cr multilayer structure is used.
As shown in FIG. 2, Au / Ni / Cu is removed by etching in a part of a wiring (a part where a resistor is to be formed), and only the lowermost layer of Cr is left, and this Cr part is used as a resistance part 16. Can be. Thus, the lowermost C
When a thin film resistor is formed with r, the adhesion to Cu, that is, the adhesion between the wiring and the substrate is improved, and the resistance can be increased without adding many complicated steps to the normal steps of a multilayer wiring board. A part can be formed. Generally, the resistance value of a resistance element is determined by width, length, thickness, and specific resistance.
In semiconductor integrated circuit devices, the capacity and the degree of integration have been increasing, and the pitch of the wiring has been largely determined. Therefore, it is difficult to adjust the resistance value by the wiring width and the wiring length. is there. In such a situation, when controlling the resistance value, Cr is originally A for the purpose of adhesion strength.
It is used as the lowermost layer of a wiring having a u / Ni / Cu / Cr multilayer structure. In this case, Cr is formed of a relatively thin film of, for example, about 300 to 400 angstroms, depending on the conditions for forming Cr. Therefore, it is possible to relatively easily control the resistance value to increase the resistance value. Therefore, in one embodiment of the present invention, by using the Cr present in the lowermost layer as a resistance element, And the function as a resistance element can be simultaneously achieved. The reason for leaving only the lowermost layer of Cr is that forming a single-layer resistance of Cr forms a higher resistance than forming a two-layer resistance of Cu, which is a metal through which current flows easily, and Cr. This is because it is preferable.

The resistance value of the Cr thin film resistor can be adjusted by various methods such as a film forming method and conditions (including impurity introduction), a film thickness, and a size (width and length) of the resistance element.

The resistance value of the Cr thin film resistor can be adjusted, for example, by adjusting the film thickness by a sputtering method. This is for the following reason. First, in sputtering, when sputtering is started, an impurity gas is present in the chamber, and a thin film formed at an early stage of sputtering is oxidized and nitrided by the influence of the impurity gas. In other words, when sputtering is performed using an in-line sputtering apparatus, an impurity gas in the chamber in the initial stage of the sputtering is mixed into the film as an impurity, or any substance is present on the substrate before sputtering regardless of the use of the in-line sputtering apparatus. It is conceivable that the substance is adsorbed and mixed into the film as an impurity during sputtering.
That is, as a result, for example, it can be said that Cr formed by sputtering in this manner has a higher resistance value than the specific resistance value of bulk Cr. Therefore, if the film to be formed by sputtering is a thin film, it is considered that such impurities are often mixed in the film. Since such a Cr thin film has a high resistance value and a resistance value close to a desired value can be obtained with the thin film, it can be preferably used as it is as a resistance element. FIG. 3 is a graph showing the relationship between the thickness of the resistive element (having the same line width) and the sheet resistance. As shown in FIG. 3, the sheet resistance is inversely proportional to the film thickness. For these reasons, it is understood that the resistance value of the Cr resistor can be adjusted by adjusting the film thickness by the sputtering method.

The resistance value of the Cr thin film can be adjusted by positively mixing other components into the Cr thin film. That is, as described above, since impurities and the like are mixed in Cr according to the film forming conditions and the resistance value changes, other components are positively mixed into the Cr thin film when forming the Cr and the amount of the other components is increased. By performing sputtering while adjusting the resistance, the resistance value can be adjusted and a desired resistance value can be obtained.
That is, CO ₂ , O ₂ , N ₂ , C
Reactive sputtering is performed using a gas such as O, NO ₂ , NOCH ₄ , or sputtering in which a non-metal is added as an impurity as a target composition, that is, CrO, CrN,
By performing sputtering with a target such as CrSi,
Form CrO, CrN, CrSi, etc. and O,
By adjusting the contents of N, Si and the like, the resistance values of these resistance elements can be adjusted. When a film is formed by sputtering using Si as a composition in the target, a CrSi (chromium silicide) target and an Ar gas are used to control the resistance by controlling the amount of CrSi (the amount of Si can be adjusted). Is formed, and the resistance value of the thin film resistor can be improved.

The resistance value of the Cr thin film resistor can also be adjusted by the size (width, length) of the resistance element. FIG. 4 shows a graph of the measurement results of the resistance value and the specific resistance value when a Cr resistor having a fixed film thickness and a fixed length is formed by changing the line width. C
The thickness of the r thin film resistor is 300 Å and the length is 1
It is constant at 00 μm. As shown in FIG.
It is understood that the line width and the resistance value of the r thin film resistor are inversely proportional, and the resistance value can be adjusted by the width of the resistance element. Further, as can be seen from the fact that the wiring length is 30 ohms at a wiring length of 100 μm and the wiring length is 60 ohms at a wiring length of 200 μm, the resistance value of the resistance element can be adjusted by the length of the resistance element. Therefore, the desired resistance value (for example, 10 to 500
Ω), the dimensions (width, length, thickness) of the resistor may be determined. The higher the specific resistance, the better, and the size of the resistance element is limited depending on the material. The resistance element is
Since it cannot be formed with a wiring width on the order of mm due to restrictions on the area, the line width is set to, for example, several tens to 200 μm. The Cr thin film resistance is, for example, several μm.
wiring length of m to several mm, wiring width of 10 μm to 1 mm, 30
It can be formed with a thickness of 400 angstroms. The thickness of the Cr thin-film resistor depends on the sputtering apparatus used to form the Cr thin-film resistor, and cannot be determined unconditionally.
Various choices can be made according to the degree of vacuum and the stability of the plasma under the conditions for forming the thin film. However, from the viewpoint of the adhesion, the thickness is preferably 50 Å or more. Is preferred.

The position at which the resistor is provided is not particularly limited, but the closer to the semiconductor device (chip) to be inspected, the more effective. For example, on the uppermost layer wiring of the multilayer wiring board, and at a position adjacent to the pad electrode on the uppermost layer of the multilayer wiring board connected to the device via the membrane with bumps and the anisotropic conductive rubber (for example, FIG.
It is effective and preferable to form a resistor on each I / O branch wiring 17 branched from the I / O common wiring in (1). When the resistor is provided on the uppermost layer wiring of the multilayer substrate, a metal is deposited on the resistor after forming the resistor (for example, Cr is deposited by laser CVD). The resistance can be fine-tuned after measuring the resistance, or the width of the element can be adjusted (eg, Cr deposited by laser CVD, or Cr
This is advantageous because fine adjustment of the resistance can be performed after the resistance value is inspected by a method such as (removing). Further, forming a resistor in the uppermost layer of the multilayer wiring board is advantageous in terms of heat dissipation of heat generated by energization. For example, Cr used as a resistance element forming material is a high melting point metal and has excellent heat resistance, but a material (for example, polyimide) used as an anisotropic conductive rubber sheet that comes into contact with a multilayer wiring board in a burn-in test is Although the combustion temperature is high, when the heat is generated, the heat is also transmitted to the multilayer wiring board, so that the wiring layer of the multilayer wiring board may be broken by rising to a temperature exceeding the heat resistant temperature. Therefore, if a resistor having high heat resistance is formed in the upper layer of the wiring layer, and if it is formed in the uppermost layer of the multilayer wiring board, the heat generated in the wiring layer can be efficiently released to the outside of the board. Reliability can be improved. If a space for forming a resistor cannot be obtained in the uppermost layer of the multilayer wiring board, it may be formed in a lower layer, that is, in an inner layer wiring. However, when a resistor is provided in the lower layer of the wiring, a contact hole for drawing the resistor to the outside is necessary. In this case, the contact resistance does not matter, but the number of steps is increased due to a manufacturing method. I will. Cr
As another part forming the thin film resistance part, for example, FIG.
0, each power supply branch line 18, each ground branch line 1
9 and the like.

The resistance value of the resistor depends on the material,
By selecting and designing the size and the like of the resistance, it is possible to appropriately adjust the resistance to a desired value. Since the range of the resistance value varies depending on the power supply voltage and the like, it cannot be said unconditionally, but for example, 1 kΩ or less, preferably 500 Ω or less, more preferably 50 to 50 Ω.
200Ω. The resistance element having such a high resistance value can be widely used for a multilayer wiring board for a wafer batch contact board for applications such as a microcomputer and a memory.

Examples of wiring materials for forming resistors include W, Ti, Al, Mo,
Ta, CrSi, and the like. The range of these film thicknesses is, for example, 30 angstroms to several μm. The film thickness is determined so as to satisfy a required resistance value and from a space (area: width, length) for forming the resistor. As an alternative material for Cu as the main wiring material, A
1, Mo and the like. The range of the film thickness is, for example, 0.
It is 5 μm or more, preferably 2 to 6 μm. If molybdenum is used, to have the same sheet resistance, Cu
The film thickness must be at least three times as large as However, in the case of Mo,
Dry etching is possible. As a substitute material for Ni, a metal having a high adhesive strength in relation to each material forming the upper and lower layers can be used. The range of the film thickness of Ni is, for example, 0.1 μm or more, preferably 0.2 to 0.4 μm. As a substitute material for Au, an AuCo alloy, a hard noble metal such as platinum, platinum rhodium, rhodium, palladium and the like can be mentioned. These film thickness ranges are, for example, 3
It is not less than 00 Å, preferably not less than 0.2 μm. In the case of a multilayer wiring board, the outermost wiring surface is coated with gold or the like, but the surface of the lower layer (inner layer) may not be coated with gold or the like. However, considering the contact resistance, there is no problem even if the inner layer is further coated with gold, except for an increase in cost. Gold or the like may be post-installed on the wiring surface, or a multilayer wiring layer having gold or the like formed on the outermost surface may be formed in advance and wet-etched to form a wiring pattern. When gold or the like is coated on the wiring surface of the inner layer, gold or the like can be coated only on the bottom of the contact hole after the formation of the contact hole. When Au or the like is formed on the wiring on the outermost surface of the final multilayer wiring board, the oxidation resistance of the wiring is improved, and the reliability of the multilayer wiring board can be improved. Also, by forming an AuCo alloy or the like on the wiring on the outermost surface by electrolytic plating, the hardness can be further increased, and the strength can be increased even when used as a contactor, so that the reliability can be improved.

As an etching solution or etching method for Al, a mixed etching solution of phosphoric acid, nitric acid, acetic acid and water, a mixed etching solution of hydrofluoric acid, nitric acid and water, an anodic oxidation method,
Plasma etching using an etching gas such as CCl ₄ or BCl ₃ can be used. Examples of the W etching solution or etching method include a red blood salt (potassium ferricyanide) etching solution, and plasma etching using CF ₄ or the like as an etching gas. As an etching solution or an etching method of Mo, an etching solution such as a mixed etching solution of phosphoric acid, nitric acid and water, a fluoride solution, or CF ₄ , CCl ₄ + O ₂ , CHF ₃ , CH ₂ F ₂ or the like is used as an etching gas. Plasma etching and the like. Examples of the MoSi etching solution include a fluorine-based etching solution. Examples of the Ti etching solution or etching method include a mixed etching solution of hydrofluoric acid, nitric acid, and water, and plasma etching using CF ₄ , CBrF _4, or the like as an etching gas. T
The etching solution or etching method of a is NaO
H 2 aqueous solution and hydrogen peroxide mixed etching solution, CF ₄
Etc. as an etching gas.

As another embodiment of the wiring material / wiring structure and the resistance forming method, a single layer (Cu, Cr, M
o, Mo, Si, Ta, W, Al, oxides (ITO, S
nO ₂ ) or the thickness of the multilayer wiring (particularly, the thickness of the main wiring material layer) is reduced by etching or the like, the method of narrowing the width of the single-layer or multilayer wiring by etching or laser or the like, A method of cutting a wiring of a portion to be formed and depositing a resistive material on the cut portion to form a resistor, a method of cutting a wiring of a portion where a resistor is to be formed, and attaching a chip resistor to the cut portion. Can be

The method of manufacturing a multilayer wiring board for a wafer batch contact board according to the present invention is characterized in that the method includes a step of etching a part of the wiring to provide a resistor.

Here, it is preferable that the cross-sectional structure of the wiring be a laminated structure composed of two or more different metal materials, and that at least the metal serving as the resistor and the metal formed thereon be different. In this case, a material having a different selection ratio is selected by dry etching or wet etching, and the metal etching solution for the resistance and the metal etching solution thereover are different types, that is, the respective metal etching solutions are mutually etched. It is preferred that this is not done. For example, if Ni and Cu are etched with nitric acid such as ferric chloride and Cr is etched with another etching solution, only Cr can be suitably left. Also,
CrN (etching becomes faster if N is added), CrO
(If O is added, the etching will be slowed down.)
A structure such as CrN (metal serving as a main wiring material) / CrO (metal serving as a resistor) can be provided.

Hereinafter, embodiments will be described.

[0034] Preparation FIGS. 5 and the multilayer wiring substrate 6 is a fragmentary cross-sectional view showing an example of a manufacturing process of the multilayer wiring board. As shown in the step (1) of FIG. 5, a glass substrate 1 whose surface is polished flat (manufactured by HOYA: NA
40, a size of 320 mm square, and a thickness of 3 mm).
The u film is formed to a thickness of about 2.0 μm and the Ni film is formed to a thickness of about 0.3 μm sequentially to form the Ni / Cu / Cr multilayer wiring layer 2. Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu. Ni is provided for the purpose of preventing oxidation of Cu, enhancing the adhesion between Cu and the resist, and preventing polyimide from remaining at the bottom of the contact hole (via) due to the reaction between Cu and polyimide. ing. Note that the method for forming Ni is not limited to the sputtering method, and may be formed by an electrolytic plating method. Further, it is also possible to reduce the contact resistance by forming an Au film on the Ni film by a sputtering method, an electrolytic plating method or an electroless plating method.

Next, as shown in step (2) of FIG. 5, a predetermined photolithography step (resist coating, exposure, development, etching) is performed, and the Ni / Cu / Cr multilayer wiring layer 2 is patterned. First-layer wiring pattern 2
a is formed. Specifically, first, a resist (Microposit S1400 manufactured by Shipley Co., Ltd.) is coated to a thickness of 3 μm, baked at 90 ° C. for 30 minutes, and exposed and developed with a predetermined mask to obtain a desired resist pattern ( (Not shown). Using this resist pattern as a mask, the Ni / Cu / Cr multilayer wiring layer 2 is etched using an etching solution such as an aqueous ferric chloride solution,
Thereafter, the resist is stripped using a resist stripper, washed with water and dried to form a first-layer wiring pattern 2a.

Next, as shown in step (3) of FIG.
A polyimide insulating layer 3 is formed by applying a photosensitive polyimide precursor to a thickness of 10 μm on the wiring pattern of the layer using a spinner or the like. A contact hole 4 is formed in the polyimide insulating layer 3. More specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, exposed and developed using a predetermined mask, and is then exposed to contact holes 4.
To form After curing the photosensitive polyimide precursor completely at 350 ° C. for 4 hours in a nitrogen atmosphere, the polyimide surface is roughened by oxygen plasma treatment, and the second wiring layer formed in the next step And oxidizes and removes organic substances such as polyimide and residual developer in the contact hole 4.

Next, as shown in step (4) of FIG. 5, a Ni / Cu / Cr multilayer wiring layer 5 is formed in the same manner as in step (1).

Next, as shown in step (5) of FIG. 5, the Ni / Cu / Cr multilayer wiring layer 5 is patterned in the same manner as in step (2) to form a second wiring pattern 5a. I do.

Next, as shown in step (6) of FIG. 6, the above steps (3) to (5) are repeated in the same manner to repeat the second polyimide insulating layer 6, the contact hole 7, and the third layer. The wiring patterns 8a were sequentially formed to obtain a glass multilayer wiring board having a three-layer structure. However, the third-layer wiring pattern 8a
Is a multilayer wiring having an Au / Ni / Cu / Cr structure for the purpose of improving electrical contact with an anisotropic conductive film. Specifically, an Au film is formed on a Ni film by electroplating.
Except that the Au film was etched using an aqueous solution of iodine and potassium iodide.
A third layer wiring pattern was formed in the same manner as the first layer wiring pattern. The Ni film plays a role in enhancing the adhesion between the Au film and Cu. Although an Au film can be formed on the Ni film by electroless plating, the thickness of the Au film cannot be increased.

Formation of Resistance Section Next, a predetermined portion of the third-layer wiring pattern 8a having the Au / Ni / Cu / Cr multilayer structure is subjected to the Au / Ni / Cu / Cr multilayer pattern.
Etching is performed up to Ni / Cu to form a Cr thin film resistance portion (see FIG. 1). This step will be described in detail. As shown in step (7) of FIG.
a is coated with resist 9 and then step (8) in FIG.
As shown in (1), exposure and development are performed using a predetermined mask to form a resist pattern 9a in which the resist is removed only in the portion where the Cr thin film resistance portion is to be formed. At this time, if the resist to be used is a positive type, only the resistance forming portion is left unexposed and the resist of the resistance forming portion is removed. If the resist to be used is a negative type, only the resistance forming portion is exposed and the resistance forming portion is exposed. The resist is removed. Subsequently, as shown in step (9) of FIG. 6, the resist pattern 9a is used as a mask to etch Au / Ni / Cu up to an Au / Ni / Cu using an etching solution such as an aqueous ferric chloride solution, thereby forming a Cr thin film resistance portion. 8b is formed. In this embodiment, FIG.
I / O branch wiring 1 branched from the I / O common wiring shown in FIG.
7 was provided with a Cr thin film resistor. In this case, Cr thin film resistors were provided on all the I / O branch wirings 17 branched from all the I / O common wirings in the multilayer wiring board. The resistance value of each Cr thin film resistor is high, for example, 50-20.
It was set to 0Ω. The Cr thin film resistor was formed with a wiring length of 200 μm, a wiring width of 100 μm, and a thickness of 300 to 400 Å.

Next, as shown in step (10) of FIG.
After removing the resist, polyimide as an insulating film was applied on the substrate, and was patterned to form a protective insulating film 11, thereby obtaining a multilayer wiring board 10 for a wafer batch contact board.

Next, the anisotropic conductive rubber sheet made of silicone resin, in which metal particles are embedded in the pad electrode portions, is bonded to a predetermined portion of the multilayer wiring board 10 for a wafer batch contact board. I stuck to the position.

Preparation of Membrane Ring Next, a membrane ring with bumps, which serves as a contact portion in direct contact with the wafer, was prepared.

A method for forming a membrane ring will be described with reference to FIG. First, as shown in FIG.
A silicon rubber sheet 36 having a uniform thickness of 5 mm is placed on an aluminum plate 35 having high flatness. On the other hand,
For example, a film 37 in which copper is formed to a thickness of 18 μm on a polyimide film having a thickness of 25 μm by a sputtering method or a plating method is prepared. The material, forming method, thickness, and the like of the film 37 can be appropriately selected. For example, a thickness of 25 μm
A polyimide film having a thickness of about 12 to 50 μm or a silicon rubber sheet having a thickness of about 0.3 mm (0.1 to 0.5 mm) can be used. The film can be formed by a coating method or a commercially available film or sheet can be used. Further, after the polyimide precursor is cast on the copper foil, the polyimide precursor is heated, dried and cured to form a film having a structure in which the copper foil and the polyimide film are bonded. Alternatively, a film having a structure in which a plurality of conductive metals are sequentially formed on one surface of a film and a conductive metal layer having a laminated structure is formed on one surface of the film may be used. A thin Ni film (not shown) may be formed between the polyimide and Cu for the purpose of improving the adhesion between the two and preventing film contamination.

Next, a film 37 having a structure in which copper and a polyimide film are bonded to each other is adsorbed onto the silicon rubber sheet 36 in a state where the film 37 is uniformly spread with the copper side down. At this time, by utilizing the property that the film 37 is adsorbed to the silicon rubber sheet 36, the air layer is adsorbed while being expelled so as not to cause wrinkling or bending, so that the air layer is adsorbed in a uniformly developed state.

Next, a thermosetting adhesive 38 is thinly and uniformly applied to the bonding surface of the circular SiC ring 31 having a diameter of about 8 inches and a thickness of about 2 mm in a thickness of about 50 to 100 μm. Put on. Here, as the thermosetting adhesive 38, an adhesive that cures at a temperature 0 to 50 ° C. higher than the set temperature of the burn-in test of 80 to 150 ° C. is used. In the present embodiment, Bond High Chip HT-100L (main agent: curing agent = 4: 1) (manufactured by Konishi Co., Ltd.) was used. In addition, highly flat aluminum plate (weight about 2.5kg)
Is placed on the ring 31 as a weight (not shown).

After completion of the above-described preparation step, the temperature (80 to 150 ° C.) or higher (e.g.
The film 37 and the ring 31 are bonded by heating at (00 ° C., 2.5 hours) (FIG. 7B). At this time, since the coefficient of thermal expansion of the silicon rubber sheet 36 is larger than the coefficient of thermal expansion of the film 37, the film 37 adsorbed on the silicon rubber sheet 36 expands by the same amount as the silicon rubber sheet 36. That is, the thermal expansion of the silicon rubber sheet is greater than when the film 37 is simply heated at a temperature equal to or higher than the set temperature (80 to 150 ° C.) in the burn-in test, and the polyimide film expands more due to this stress. When the tension is large, the thermosetting adhesive 3
8 is cured, and the film 37 and the ring 31 are bonded.
Further, since the film 37 on the silicon rubber sheet 36 is adsorbed in a state where the film 37 is uniformly spread without wrinkles, deflections, or looseness, the film 37 can be bonded to the ring 31 without wrinkles, deflection, or looseness. it can. Furthermore, the silicon rubber sheet 36 has high flatness,
Since it has elasticity, the film 37 can be uniformly and uniformly bonded to the bonding surface of the ring 31. The tension of the polyimide film was 0.5 kg / cm ² . In addition,
Without thermosetting adhesive, the film shrinks,
In addition to weakening the tension, the curing time of the adhesive varies from place to place, so that the adhesive cannot be evenly and uniformly bonded to the bonding surface of the ring.

After completion of the heating and bonding step, the product is cooled to room temperature and contracted to a state before heating. Thereafter, the film 37 outside the ring 31 is cut and removed along the outer periphery of the ring 31 with a cutter to produce a membrane ring (FIG. 7C).

Next, a process of forming the bumps and the pads by processing the above-mentioned membrane ring will be described.

First, as shown in FIG. 8B, the copper foil (Cu) of the film 37 having a structure in which the copper foil and the polyimide film in the membrane ring prepared as shown in FIG. Then, Ni was added to the substrate by electroplating.
After plating 2 to 0.5 μm (preferable range is 0.1 to 3 μm), Au is formed thereon at 0.1 to 0.5 μm (preferable range is 0.5 to 2 μm), and Au / Ni / C
A u / polyimide film laminated film structure is formed.

Next, as shown in FIG. 8 (c), an excimer laser is used to
A bump hole having a diameter of about 30 μm is formed.

Next, as shown in FIG. 8D, in order to prevent the surface of the uppermost Au film from being plated, a protective film or the like such as a resist is partially replaced with a part of the Au film used as an electrode. It is applied to a thickness of about 2 to 3 μm on the entire surface except for protecting the Au film.

Next, one of the electrodes is connected to the uppermost Au film, and Ni or Ni alloy is electroplated on the polyimide film side. By this electroplating, the plating grows so as to fill the bump hole shown in FIG. 8D, and then spreads isotropically and grows almost hemispherically when it reaches the surface of the polyimide film, and Ni or Ni alloy Is formed. Subsequently, an electroplating layer made of Au having a thickness of 1 to 2 μm is formed on the surface of the bump. Thereafter, although not particularly shown, the protective film is peeled off.

Then, a new resist is applied to the entire surface of the uppermost layer of Au, and the resist other than the portion where the pad is to be formed is removed by exposure and development.
As shown in (e), a resist pattern is formed.

Next, as shown in FIG. 8F, the Au film was etched with an aqueous solution of iodine / potassium iodide.
After etching the thin Ni film and Cu film existing between u and Cu with an aqueous solution of ferric chloride and rinsing well,
The resist was peeled off, and as shown in FIG.
A pad made of u / Ni / Cu is formed. At this time, it is preferable to use a spray method for etching, since side etching is small.

Through the above steps, the membrane ring
The bumps and pads are formed, and the membrane ring with bumps is completed.

Assembly Step The multilayer wiring board with anisotropic conductive rubber sheet and the membrane ring with bumps manufactured as described above were aligned so that the pad electrodes would not come off, and then bonded to complete a wafer batch contact board.

Burn-in test After the pads on the wafer and the bumps of the membrane ring with bumps were aligned, they were fixed with a chuck, and then placed in a burn-in apparatus and tested in an operating environment at 125 ° C. As a result, even when a defective portion (short between each wiring and a power supply or a ground line) exists in any semiconductor device in the wafer, a semiconductor device formed on the wafer without any problem, for example, Microcomputer, A
SIC and memory could be measured respectively. That is, in the present embodiment, each I / O branch from the I / O common wiring
Since a resistor is provided on the / O branch wiring 17, even if a defective portion exists in any of the semiconductor devices in the wafer, the semiconductor device is naturally defective, but the simultaneous measurement is performed. Up to the semiconductor device described above, it was possible to prevent a large current from leaking from a defective portion of the semiconductor device in question, making it difficult to perform measurement or destroying a good semiconductor device.

Note that the present invention is not limited to the above-described embodiment, and can be appropriately modified within the scope of the present invention.

For example, the number of wiring layers in a multilayer wiring board for a wafer batch contact board is not limited to three layers, but can be a desired number (for example, usually two to five layers).

The glass substrate is manufactured by HOYA: NA4
It is not limited to 0, and is a material having the same thermal expansion coefficient as Si or a similar expansion coefficient to Si, and does not generate warpage due to stress.
A material that can be easily formed can be used.
Examples of such materials include ceramic substrates such as SiC, SiN, and alumina, and other glass substrates (for example, NA35, NA45, SD1, SD2 (HOY and above).
A), Pyrex, 7059 (above manufactured by Corning), etc., have almost the same coefficient of thermal expansion (coefficient of thermal expansion as 0.1).
6-5 PPM), a glass ceramics substrate, a resin substrate (in the case of a particularly small substrate), and the like. Glass substrates are inexpensive, easy to process, have high flatness due to high-precision polishing, are transparent and easy to align, and can control thermal expansion depending on the material. Also excellent in nature. In addition, if the glass is non-alkali, there is no adverse effect due to elution of alkali on the surface.

[0062]

According to the multilayer wiring board for a wafer batch contact board of the present invention, even when a semiconductor device having a short-circuit portion in an internal circuit exists, the internal circuit of another semiconductor device is destroyed, The problem that another semiconductor device malfunctions can be avoided on the multilayer wiring board side. Further, according to the method of manufacturing a multilayer wiring board for a wafer package contact board of the present invention, the above-described multilayer wiring board for a wafer package contact board of the present invention can be realized with simple steps without adding complicated steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a principal part showing a wiring having a multilayer structure formed on a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is an essential part cross-sectional view showing a resistance part in the multilayer wiring board according to one embodiment of the present invention;

FIG. 3 is a diagram illustrating a relationship between a film thickness of a Cr resistor and a sheet resistance.

FIG. 4 is a diagram illustrating a relationship between a line width of a Cr resistor and a resistance value.

FIG. 5 is a fragmentary cross-sectional view for explaining the manufacturing process of the multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view for explaining the manufacturing process of the multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view for explaining a step of forming a membrane ring in one embodiment of the present invention.

FIG. 8 is a cross-sectional view of a main part for describing a processing step of a membrane ring in one embodiment of the present invention.

FIG. 9 is a view schematically showing a wafer batch contact board.

FIG. 10 is a diagram schematically showing a wiring relationship in a multilayer wiring board.

FIG. 11 is a diagram schematically showing a wiring relationship in a multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 glass substrate 2 Ni / Cu / Cr multilayer wiring layer 2a first layer wiring pattern 3 insulating layer 4 contact hole 5 Ni / Cu / Cr multilayer wiring layer 5a second layer wiring pattern 6 insulating layer 7 contact hole 8a 3 layer Eye wiring pattern 8b Cr thin film resistance part 9 resist 9a resist pattern 10 multilayer wiring board 11 protective insulating film 15 wiring having another layer structure 16 resistance part 17 I / O branch wiring 18 power supply branch wiring 19 ground branch wiring 20 anisotropic Conductive rubber sheet 30 Membrane ring with bump 31 Ring 32 Membrane 33 Bump 34 Pad 35 Aluminum plate 36 Silicon rubber sheet 37 Film 38 Thermosetting adhesive 40 Silicon wafer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G003 AA10 AG07 AG08 AG12 AH07 2G011 AA16 AA21 AB06 AB07 AB08 AC11 AC14 4M106 AA01 BA14 CA56 DJ32 5E346 AA15 BB02 BB16 BB20 CC25 CC31 CC32 CC37 CC38 DD09 FF45 GG22 HGG31 GG32 GG32

Claims (8)

[Claims] 1. A multilayer wiring board which constitutes a part of a wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer, wherein said multilayer wiring board is A plurality of pads provided on the multilayer wiring board corresponding to each pad in a large number of semiconductor devices, and pads to which the same signal or power is input / output in the large number of semiconductor devices are electrically commonly connected. A wafer having: a common wiring; a branch wiring branched from the common wiring and connecting between the plurality of pads and the common wiring, respectively; and a resistive element provided on the branch wiring. Multilayer wiring board for batch contact board. 2. The method according to claim 1, wherein the common wiring is a signal input / output wiring (I
/ O wiring), and an I / O wiring branched from the I / O common wiring.
2. The multilayer wiring board for a wafer batch contact board according to claim 1, wherein a resistance element is provided on the / O branch wiring. 3. The multilayer wiring for a wafer batch contact board according to claim 1, wherein a resistor is provided on the uppermost wiring in the wafer batch contact board having a structure in which wirings are stacked via an insulating layer. substrate. 4. A multi-layer wiring board for a wafer batch contact board, comprising a step of processing a part of the wiring in a wafer batch contact board having a structure in which wirings are stacked via an insulating layer to provide a resistance. Production method. 5. A multilayer wiring board for a wafer batch contact board, comprising a step of etching a part of the wiring in a wafer batch contact board having a structure in which wirings are stacked via an insulating layer to provide a resistor. Production method. 6. The method according to claim 5, further comprising the steps of: forming a wiring having a multilayer structure in which two or more different materials are stacked; and providing a resistor by etching a part of the wiring for the wiring. A method for manufacturing a multilayer wiring board for a wafer batch contact board according to the above. 7. A step of forming a wiring having a multilayer structure in which Au / Ni / Cu / Cr is laminated; and forming Au / Ni / Cu in a part of the wiring for the wiring.
7. A method of manufacturing a multilayer wiring board for a wafer batch contact board according to claim 6, further comprising the step of providing a Cr resistor by etching the substrate. 8. A wafer batch contact board, comprising: the multilayer wiring board for a wafer batch contact board according to claim 1; and a membrane ring with bumps that serves as a contact portion that directly contacts the device under test.