HU190565B - Method and arrangement for realizing channel units of satellite communication systems with individual speech channel - Google Patents

Abstract

A method to centralize and restructure systemtechnical jobs of PCM-channel units of SCPC satellite-communication systems during a sampling period. The system-technical tasks of a PCM-channel unit are restructured into parallel-in-time disjunct jobs and are grouped that way that we order to each computing element a job to be run at the same time - simultaneously - and at the end of the first job to each computing element a new job is ordered to be run after the first one also simultaneously during the same sampling period, and so forth... A circuit arrangement is invented in which a computing capacity of the computing elements is provided. The computing elements are communicating with each other and with other system elements via two-way common address/data/control bus-system. The computing elements are connected to an interrupt generator by means of interrupt connections. A common memory is connected also to the common address/data/control bus. The computing elements are connected to a switches-displays block, to a modemunit and to a codec unit via two-way ports and via a blocksynchron detector - also by means of the common address/data/control bus.

Description

The present invention relates to a method for integrating, optimizing and restructuring the functions of channel units of a unique speech channel, fixed or random carrier communication systems, and a circuit arrangement for performing tasks structured according to the method.

The present invention is very advantageous for use in highly integrated and economical microprocessor based modular architecture and can be flexibly upgraded in terms of features and quality features with unique speech channel, fixed or random carrier designation.

As is known in the art, the channel units of individual speech channel systems are structured according to the block diagram of Figure 1, where each block not only defines the applied system minds but also represents the specific circuit elements of the implementation.

The operation of the state-of-the-art channel unit according to Figure 1 is as follows. From the 7-bit PCM words received from the PCMK encoder via the KE delay, two 112-bit blocks of data are formed in the shift registers SR under the control of the gates K. This is where the 16-bit BSZK1, BSZK2 synchronous codes providing block synchronization are inserted into the two bit streams that modulate the dibit channels of the PSK modem using the BSZG block sync generator. At the beginning of the data stream, the ECG source code generator inserts a 40 + 80 = 120-bit EC source code to facilitate initial setup of the PSKV receiver. Finally, the 40 + 80 = 120-bit EC source code is compiled. Finally, the 2 x (112 + 16) = 256 bit blocks thus formed and continuously received are transmitted by the PSKA transmitter to one of the designated frequencies of the 70 ± 18 MHz acid according to the channel assignment.

On the receiver side, the above operations must be performed in reverse order and the beginning of the information blocks is detected by the BSZD block synchronous detector. The parallel data signal from the PSKV receiver on dibit channels is converted by the P / S parallel serial converter into a serial data signal. With the help of the FBH Phase Uncertainty Repair, the system eliminates phase uncertainty due to the rotation of the carrier cross and the order of the dibits. Finally, the VEZ controller restores the 7-bit PCM words, which the PCMD decoder converts to an analog signal.

The disadvantage of the known solution is that the whole system engineering task is divided only into parts that are executed by each circuit unit, irrespective of the time requirement, and during one period of time, under one load.

In addition to this procedure, the components are inarially optimum in structure, and the entire system consists of suboptimals and is thus not optimal overall. In addition, the second disadvantage of a2 is that this approach only allows implementation from less integrated, less intelligent and more expensive circuit elements. A disadvantage of the solution is that the implemented system has some computer elements which, despite being intelligent, may not be fully utilized. In the inflexible structure hitherto, it is not possible to ensure the improvement of the system's service and quality, the uniform load and utilization of certain elements of the computing capacity, the validation of modern and economical modularity, unification, manufacturing, scalability and operation.

It is an object of the present invention to provide a novel method and circuit arrangement for implementing single channel, fixed or random carrier satellite communication systems, which optimize the entire system by redefining the overall system task.

The object of the present invention is to implement an optimized system using concentrated computing intelligence that is based on state-of-the-art, high-capacity, perspective, yet inexpensive and accessible circuitry, and the proposed solution provides state-of-the-art manufacturing, scalability, testability, and maintenance. The invention enables the system to be upgraded both in terms of services and quality parameters, and because of the unified and modularly expandable computing capacity, it is economical and highly reliable. In other words, this means that with the expansion of the system task, you only need to expand the system with one additional computing unit. This will greatly simplify the system's manufacturability and measurability.

The essence of the method according to the invention is to optimally structure the functions of the channel unit as a complex unit and, in view of the circuit layout for implementing the method, to allocate the computational capacity elements available for solving the whole task hereafter referred to as computational units of uniform load.

According to our method, the system engineering tasks of each channel group are divided into overlapping and disjoint subtasks and grouped by assigning tasks to be performed simultaneously to each computing base unit, and assigning new tasks to the end point of the tasks, which are parallel to each other.

-2190565 must be completed after the first set of tasks during the same sampling period.

Thus, on the one hand, we ensure optimal utilization of the circuit layout of the implementation and, on the other hand, determine the number of basic computing units required for implementation, microprocessors in the preferred embodiment, and the specific computing circuits used. They can be considered as peripherals of the structure and which ensure that sub-tasks exceeding the speed of the aforementioned basic computing unit can be solved by the proposed special computing structure; the objective and structural approach allows the basic computing units to have the same design and, thanks to this scalability, connect the measurement, production, testing and operational facilitation tools (eg display, etc.) to the system, the type of computing base unit that is the most economical choice at any given time, and increasing the number of base units allows for additional service and / or quality changes, including system engineering.

FIG. 1 is a block diagram of a channel unit of a known unique speech hack system.

Figure 2 illustrates a method of the invention in a time diagram.

Figure 3 illustrates a circuit arrangement according to the invention.

An embodiment of the method of the present invention is illustrated in the time diagram of Figure 2. Time of one sampling period:

t = 125psec = 8kHz

In the examples, the four basic units of calculation are shown in the figure as PROC1 ... PROC4.

System engineering tasks include:

Receiving a PGM signal

PCM Signal Output Frame Organization Frame Decomposition Adaptive Threshold Control Threshold Detection

SOM Detection Eliminating Phase Uncertainty

At the start of the sampling period, a first set of system engineering tasks are assigned to a computing base unit such that the first PROCl computing base unit receives 1 PCM signal; outputting 2 PCM signals with a second base unit PROC2; the third PROC3 computing base unit 3 frame organization; the frame demolition 4 is performed with the 4th computing unit PR0C4. Then, taking into account the execution time of each task, we select which task is assigned to each PROC1-PROC4 computational base unit from the second set of system engineering tasks, and thus to the first PROCl computational base unit, the adaptive threshold control. a threshold detection 6 for the second base unit of calculation PR0C2; detecting 7 SOMs for the third PR0C3 computing base unit; assigning the phase uncertainty 8 to the fourth computing unit PR0C4, and assigning the first PROCl computing unit 9 as a third task within the sampling period t, as a third task.

An embodiment of the circuit arrangement according to the invention is shown in FIG. The concentrated computing capacity of SK consists of the basic computing units PROCl ... PR0C4, which are connected to the bidirectional and common address (data) controller BUS and to each other by the line B1 ... B4, according to the task structure. THE

PROCl ... PR0C4 computing base units can be implemented for example with the Intel 8085 tip. circuits. The basic calculation unit PROCl ... PROC4 is with the IG interrupt generator and with

They are connected by interrupt wires 11 ... 14. The IG interrupt generator is essentially a timing current, which ensures that each computational base unit continues to execute task groups after it has been received where it left off. The IG interrupt generator can be implemented, for example, with an Intel 8253 tip. circuit.

The common address (data) controller BUS connects the SK concentrated computing capacity, the m memory, and the PORTI bidirectional port via the KKD switch-display block, the n ^ pORT2 bidirectional port, the PSKM modem unit, the PORT3 bidirectional port the PCMKD codec unit and the BSzD block synchronous detector.

Block synchronization means finding the beginning and end of blocks, which is equivalent to searching for a known block sync word. The implementation of the BSzD block synchronous detector of the present invention may be implemented, for example, from Texas SN7430 and SN74164 circuits. The required bi-sync word is SCPC1PSK (4) and SCPCU'CMIPSK (4) System Specification BG-9-21 E (Rev.3) 31.

March 1982. defined.

The Kl / ON point of the PSKM modem unit is the connection point for common units. The ON / OFF point of the PCMKD codec unit ¹ corresponds to the I / O of the telephone circuits.

The operation of the circuit arrangement according to the invention is as follows:

The 7-bit PCM words from the PCMKD codec to the PORT3 bidirectional gate and forward to the B9 cable are used to control the PROCl and PROC2 computing base unit.

19 (.) 565, we write 32, or 224 bits, on the B5 line and store the required 32-bit block sync code in front of it. Finally, the 256-bit block thus assembled in the memory M is transmitted by the B5 line, under the control of the PR0C3 computing base unit, to the bidirectional gate P0RT2, whereupon the PSKM modem is divided into dibit channels. The PSKM modem converts the signal to be transmitted to the common units of the unique speech channel system into the 70 ± 18 Milz band of the selected carrier using PSK modulation. In the downstream direction, the channel unit operates so that the dibits arriving from the common units on the PMJ interface wires of the PSKM modem to the PORT2 bi-directional gate via the B7 line and the common address / data / control BUS are provided to the PR0C4 computing base. The PR0C4 calculating base unit communicating with the other computing bases on the B4 wire, based on the code supplied to it from the BSzD block synchronous detector via the B8 wire, assumes the correct block synchronization determined by the PMJ interface wires arriving at its input. The decoded bits arriving at the memory M via the address / data / control BUS and the B5 line are again represented as a 224 bit block. These blocks then pass through line B2 to the calculation unit PR0C2. The PR0C2 computing unit breaks down one block into 7-bit PCM words, performs the necessary bit-level operations, and then transmits the PCM words via the B2 line to the PORT3 bidirectional port, which transmits the PCM words to the PCMKD codec decoder via the PCMJ interface wires. . From there, the analog samples are passed through the internal filter of the PCMKD codec unit to the telephone circuit, i.e. the codec unit's ON / OFF thread. The 1G interrupt generator with interrupts provides the basic computing units PR0C1 ... PR0C4

11 to 14 interrupt wires so that the computing bases do not lose the sample to be processed, i.e., input data, and the processed sample, i.e., output data, is transmitted to the outside world in time. Operation of the KKD switch-display-block block connected to the P (V) bidirectional gate by the bus (B6) connecting the address (data) control bus is possible.

Λ four computing base units work at the same time, but only one access to the common M memory at a time, giving control computing and parameter transfer between computational base units the optimal computing structure thanks to task structuring.

Claims (3)

PATENT CLAIMS 1. A method for aggregating and restructuring the channel units of a single speech channel, fixed or random carrier satellite communications system during a sampling period, comprising: assign tasks to be performed at the same time, and assign new tasks to the completion time of the tasks, which must be performed in parallel, but after the first set of tasks, during the same sampling period (2 hours) The method of claim 1, using four computing base units, characterized by assigning, at the start of the sampling period, a first set of system engineering tasks to a computing base unit such that the first computing base unit (PROC1) is receiving (1) a PCM signal; a second computing base unit (? R0C2) outputting (2) the PCM signal; frame organization (3) with the third computing base unit (PR0C3); the fourth computing base unit (PR0C4) performs the frame decomposition (4) and, taking into account the execution time of each task, chooses which task from the second set of system engineering tasks (PR0C1) is assigned to each computing base unit (PR0C1PROC4). adaptive threshold control (5) for the second computing base unit (PR0C2), threshold threshold (6); assign the SOM detection (7) to the third computational base unit (PR0C3), the phase uncertainty elimination (8) to the fourth computational base unit (PR0C4), and assign the self-test (9) to the first computational base unit (PR0C1) within the sampling period. . 3. A circuit arrangement for implementing channel units for unique speech channel satellite communication systems; consisting of computing base units, interrupt generator, memory and bidirectional gates connected thereto with BUS system, block synchronous detector, modem unit, codec unit, switch-display unit á 1, characterized in that the computing capacity (PROC1 ... PROC4) is concentrated (SK) is built, the base units (IPROC1-PRUC4) are connected to a bidirectional and common address (data) controller BUS and interconnected by wires (B1 ... B4), the base units (PROC1 ... PROC4) with the interrupt generator (SK) JG) and are interconnected by interrupt wires (J1 ... I4), the common address (data) controller BUS is connected to the common memory (M) by the wires (B5), and the common c'm (data) controller BUS is connected via wires (B6 ... B9) to the switch-display-display via the bidirectional gate (PORTI) Block -490565 (KKD), Modem Unit (PSKM) via Bidirectional Gate (P0RT2), Codec Unit (PCMKD) via Bidirectional Gateway (P0RT3), and Block Synchronous Detector (BSZD) via The 5 inputs are connected to the bidirectional gate (P0RT2) and the modem unit (PSKM) interface cables (ΡΪ-IJ), the modem unit (PSKM) Kl / BK point is also the common unit connection point, the codec unit (PCMKD, OFF) / ON is also the connection point of the telephone circuits (Figure 3).