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FR2336734A1 - Systeme de multiplication binaire a grande vitesse utilisant plusieurs circuits generateurs de multiples - Google Patents

Systeme de multiplication binaire a grande vitesse utilisant plusieurs circuits generateurs de multiples

Info

Publication number
FR2336734A1
FR2336734A1 FR7638608A FR7638608A FR2336734A1 FR 2336734 A1 FR2336734 A1 FR 2336734A1 FR 7638608 A FR7638608 A FR 7638608A FR 7638608 A FR7638608 A FR 7638608A FR 2336734 A1 FR2336734 A1 FR 2336734A1
Authority
FR
France
Prior art keywords
high speed
generator circuits
multiple generator
multiplication system
binary multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7638608A
Other languages
English (en)
Other versions
FR2336734B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of FR2336734A1 publication Critical patent/FR2336734A1/fr
Application granted granted Critical
Publication of FR2336734B1 publication Critical patent/FR2336734B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7638608A 1975-12-22 1976-12-21 Systeme de multiplication binaire a grande vitesse utilisant plusieurs circuits generateurs de multiples Granted FR2336734A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/642,844 US4041292A (en) 1975-12-22 1975-12-22 High speed binary multiplication system employing a plurality of multiple generator circuits

Publications (2)

Publication Number Publication Date
FR2336734A1 true FR2336734A1 (fr) 1977-07-22
FR2336734B1 FR2336734B1 (fr) 1983-03-18

Family

ID=24578274

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7638608A Granted FR2336734A1 (fr) 1975-12-22 1976-12-21 Systeme de multiplication binaire a grande vitesse utilisant plusieurs circuits generateurs de multiples

Country Status (7)

Country Link
US (1) US4041292A (fr)
JP (1) JPS592054B2 (fr)
BE (1) BE849736A (fr)
CA (1) CA1080850A (fr)
DE (1) DE2658248A1 (fr)
FR (1) FR2336734A1 (fr)
GB (1) GB1570791A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2397677A1 (fr) * 1977-07-15 1979-02-09 Honeywell Inf Systems Dispositif d'execution d'operations de calcul en virgule flottante, par memorisation multiple

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153938A (en) * 1977-08-18 1979-05-08 Monolithic Memories Inc. High speed combinatorial digital multiplier
US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
JPS55103642A (en) * 1979-02-01 1980-08-08 Tetsunori Nishimoto Division unit
US4228520A (en) * 1979-05-04 1980-10-14 International Business Machines Corporation High speed multiplier using carry-save/propagate pipeline with sparse carries
US4550335A (en) * 1981-02-02 1985-10-29 Rca Corporation Compatible and hierarchical digital television system standard
US4455611A (en) * 1981-05-11 1984-06-19 Rca Corporation Multiplier for multiplying n-bit number by quotient of an integer divided by an integer power of two
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4597053A (en) * 1983-07-01 1986-06-24 Codex Corporation Two-pass multiplier/accumulator circuit
US4646257A (en) * 1983-10-03 1987-02-24 Texas Instruments Incorporated Digital multiplication circuit for use in a microprocessor
CA1232072A (fr) * 1983-12-26 1988-01-26 Hideo Miyanaga Circuit de multiplication utilisant un multiplicateur et un additionneur a report
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
JPS6297033A (ja) * 1985-10-24 1987-05-06 Hitachi Ltd 乗算装置
US4769780A (en) * 1986-02-10 1988-09-06 International Business Machines Corporation High speed multiplier
US4745570A (en) * 1986-05-27 1988-05-17 International Business Machines Corporation Binary multibit multiplier
US4864529A (en) * 1986-10-09 1989-09-05 North American Philips Corporation Fast multiplier architecture
US4862405A (en) * 1987-06-30 1989-08-29 Digital Equipment Corporation Apparatus and method for expediting subtraction procedures in a carry/save adder multiplication unit
JPH03142627A (ja) * 1989-10-24 1991-06-18 Bipolar Integrated Technol Inc 集積浮動小数点乗算器アーキテクチャ
US5631859A (en) * 1994-10-27 1997-05-20 Hewlett-Packard Company Floating point arithmetic unit having logic for quad precision arithmetic
US6611856B1 (en) * 1999-12-23 2003-08-26 Intel Corporation Processing multiply-accumulate operations in a single cycle
US6742011B1 (en) * 2000-02-15 2004-05-25 Hewlett-Packard Development Company, L.P. Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry
US7177421B2 (en) * 2000-04-13 2007-02-13 Broadcom Corporation Authentication engine architecture and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372269A (en) * 1961-06-30 1968-03-05 Ibm Multiplier for simultaneously generating partial products of various bits of the multiplier

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3497685A (en) * 1965-11-03 1970-02-24 Ibm Fault location system
US3691359A (en) * 1970-07-28 1972-09-12 Singer General Precision Asynchronous binary multiplier employing carry-save addition
US3685994A (en) * 1971-05-05 1972-08-22 Rca Corp Photographic method for printing a screen structure for a cathode-ray tube
FR2175261A5 (fr) * 1972-03-06 1973-10-19 Inst Francais Du Petrole
US3761698A (en) * 1972-04-24 1973-09-25 Texas Instruments Inc Combined digital multiplication summation
US3873820A (en) * 1974-01-31 1975-03-25 Ibm Apparatus for checking partial products in iterative multiply operations
US3949209A (en) * 1975-04-04 1976-04-06 Honeywell Information Systems, Inc. Multiple-generating register

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372269A (en) * 1961-06-30 1968-03-05 Ibm Multiplier for simultaneously generating partial products of various bits of the multiplier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2397677A1 (fr) * 1977-07-15 1979-02-09 Honeywell Inf Systems Dispositif d'execution d'operations de calcul en virgule flottante, par memorisation multiple

Also Published As

Publication number Publication date
GB1570791A (en) 1980-07-09
DE2658248A1 (de) 1977-07-14
DE2658248C2 (fr) 1989-03-23
BE849736A (fr) 1977-04-15
US4041292A (en) 1977-08-09
JPS5279741A (en) 1977-07-05
FR2336734B1 (fr) 1983-03-18
JPS592054B2 (ja) 1984-01-17
CA1080850A (fr) 1980-07-01

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Legal Events

Date Code Title Description
ST Notification of lapse