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FI80352B - System foer buffertminne. - Google Patents

System foer buffertminne. Download PDF

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Publication number
FI80352B
FI80352B FI831080A FI831080A FI80352B FI 80352 B FI80352 B FI 80352B FI 831080 A FI831080 A FI 831080A FI 831080 A FI831080 A FI 831080A FI 80352 B FI80352 B FI 80352B
Authority
FI
Finland
Prior art keywords
memory
levels
level
buffer memory
address
Prior art date
Application number
FI831080A
Other languages
English (en)
Finnish (fi)
Other versions
FI80352C (sv
FI831080L (fi
FI831080A0 (fi
Inventor
James W Keeley
Edwin P Fisher
John L Curley
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of FI831080A0 publication Critical patent/FI831080A0/fi
Publication of FI831080L publication Critical patent/FI831080L/fi
Application granted granted Critical
Publication of FI80352B publication Critical patent/FI80352B/fi
Publication of FI80352C publication Critical patent/FI80352C/sv

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Claims (8)

1. En delvis begränsbar buffertminnesenhet för att använ-das i ett datorsystem och erbjuda ätkomst med stor hastig-het till i huvudminnet kvarhällna data i respons till sök-förfrägningar, medan varje förfrägan är identifierad genom den krävda datans huvudminnesadress, nSmnda adress omfattan-de en av nämnda system alstrad första och andra adressdel, varvid nämnda buffertminnesenhet omfattar: ett adresserbart dataminne (20-400) anordnat i flera niväer, varje nivä omfattande lika Stora grupper av minnesställen, medan motsvarande ställen pä alla niväer är bestämda geriöm olika,nämnda ena adressdel/ varvid varje stä.lle lagrar ett dataelement; ett adresserbart indexminne (20-84) anordnat i ett lika stort antal niväer och minnesställegrupper som nämnda dataminne, varvid varje indexminnesställe lagrar en första adressdel av huvudminnesadressen för det i motsvarande datamlnnesställe hälinä dataelementet, medan motsvarande ställen pä alla niväer i nämnda indexminne är bestämda genom olika nämnda andra äd-ressdel, kännetecknad därav, att buffertminnes-enheten omfattar; felobservationsorgan (20-860) kopplade tili nämnda indexminne, medan nämnda observationsorgan fungerar för att alstra en felsignal och indikera ett fel, som ansluter sig tili en frän nämnda indexminne utläst första adressdel; styrorgan (20-880) för operationsformen kopplade tili nämnda felobservationsorgan och operativt kopplade tili nämnda indexminne och nämnda dataminne, medan nämnda styrorgan för opera-tionssättet fungerar i respons tili första uppträdande felsignal, som observerats vid läsning av ett dataelement lagrat i en nivä i nämnda buffertminnesenhet, för att bringa nämnda buf-fertminnesenhet tili ett delvis begränsat operationstillständ, där nämnda indexminnes och dataminnes funktion är begränsad en-bart tili de niväer, pä vilka fel icke observerats. 16 80352
2. Buffertminne enligt patentkravet 1# känneteck- n a t därav, att styrorganen (896, 895) för operationsformen kopplats till ersättningsorgan, för att förhindra tillträde av ett ord till en nivä, som ersatts som icke fungerande.
3. Buffertminne enligt patentkravet 1 eller 2, kSnne- t e c k n a t därav, att felobservationsorganen (860) obser-verar paritetsfel.
4. Buffertminne enligt nägot av patentkraven ovan, k ä n -netecknat därav, att felobservation utföres pä alla niväer, men fel pä niväer där överensstämmelse icke räder, lämnas obeaktade (881).
5. Buffertminne enligt nägot av patentkraven ovan, k ä n -netecknat därav, att styrorganet för operationsfor-men är känsligt endast för fel i läsfunktionerna.
6. Buffertminne enligt nägot av patentkraven ovan, k ä n -netecknat därav, att styrorganet för operationsformen omfattar en grupp sänknivä-flip-flops (DL1, DL2), respektive i förbindelse med motsvarande nivä eller grupp av niväer och som, dä de inställts, ersätter nivan eller niväerna i förbindelse med en icke fungerande nivä.
7. Buffertminne enligt patentkravet 6, känneteck- n a t därav, att ett logiskt ELLER-organ (PEI) anslutits tili sänknivä-flip-flops för att indikera när ätminstone en nivä är icke fungerande i buffertminnet.
8. Buffertminne enligt patentkravet 6 eller 7, k ä n netecknat därav, att ett logiskt OCH-organ (898) anslutits tili sänknivä-flip-flops för att indikera när buffertminnet är fullständigt icke fungerande. Il
FI831080A 1982-03-31 1983-03-30 System för buffertminne FI80352C (sv)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/364,052 US4464717A (en) 1982-03-31 1982-03-31 Multilevel cache system with graceful degradation capability
US36405282 1982-03-31

Publications (4)

Publication Number Publication Date
FI831080A0 FI831080A0 (fi) 1983-03-30
FI831080L FI831080L (fi) 1983-10-01
FI80352B true FI80352B (fi) 1990-01-31
FI80352C FI80352C (sv) 1990-05-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FI831080A FI80352C (sv) 1982-03-31 1983-03-30 System för buffertminne

Country Status (9)

Country Link
US (1) US4464717A (sv)
EP (1) EP0090638B1 (sv)
JP (1) JPS58179982A (sv)
AU (1) AU549615B2 (sv)
BR (1) BR8301593A (sv)
CA (1) CA1184665A (sv)
DE (1) DE3382111D1 (sv)
FI (1) FI80352C (sv)
MX (1) MX154471A (sv)

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Also Published As

Publication number Publication date
FI80352C (sv) 1990-05-10
AU549615B2 (en) 1986-02-06
FI831080L (fi) 1983-10-01
DE3382111D1 (de) 1991-02-21
EP0090638A3 (en) 1987-04-08
EP0090638A2 (en) 1983-10-05
FI831080A0 (fi) 1983-03-30
MX154471A (es) 1987-08-28
AU1185583A (en) 1983-10-06
CA1184665A (en) 1985-03-26
US4464717A (en) 1984-08-07
JPS58179982A (ja) 1983-10-21
BR8301593A (pt) 1983-12-06
EP0090638B1 (en) 1991-01-16

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Owner name: HONEYWELL INFORMATION SYSTEMS INC.