[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

EP0250541A1 - Chip interface mesa - Google Patents

Chip interface mesa

Info

Publication number
EP0250541A1
EP0250541A1 EP87900403A EP87900403A EP0250541A1 EP 0250541 A1 EP0250541 A1 EP 0250541A1 EP 87900403 A EP87900403 A EP 87900403A EP 87900403 A EP87900403 A EP 87900403A EP 0250541 A1 EP0250541 A1 EP 0250541A1
Authority
EP
European Patent Office
Prior art keywords
chip
mesa
planar
conductive
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP87900403A
Other languages
German (de)
French (fr)
Inventor
Nils E. Patraw
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0250541A1 publication Critical patent/EP0250541A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention pertains to Ultra-Dense, Extremely Large Scale Integration and wafer scale synthesis of microelectronic components residing on a large number of integrated circuits.
  • the specific focus of the preferred embodiment is the planar and orthogonal space optimization of active Microelectronic circuit elements which Makes possible Multi-chip VHSIC hybrids having extraordinarily high signal processing capabilities and enormous memory capacity.
  • thermo-ionic devices to solid state diodes and transistors
  • solid state diodes and transistors The transition from thermo-ionic devices to solid state diodes and transistors was the first phase of intense efforts to miniaturize circuitry in order to construct powerful digital computers.
  • the second great phase of innovation involved the consolidation of discrete solid state devices into a compact, unitary circuit which shared a single housing.
  • components like transistors were individually encapsulated in plastic cases or resided separately in metal cans. These single elements were generally Mounted on circuit boards and each had a number of leads connected together by soldered wires.
  • the first generation of integrated circuits combined many discrete active elements together on several alternating layers of metallic and dielectric films which were deposited on an insulating substrate.
  • thin-film hybrids were the precursors of current integrated circuits which contain a solitary, but extremely powerful and densely packed, semiconductor chip or die.
  • This semiconductor chip comprises a base or substrate of material, upon which many thin layers are formed that are, in turn, coupled together by tiny, metallic interconnects or vias which pass vertically through the several horizontal layers.
  • a semiconductive material such as silicon, germanium, or gallium arsenide can be chemically altered in order to form carefully selected, minute regions having different electrical properties. These distinct regions are now fabricated with great precision, and each region may measure less than one millionth of an inch.
  • a few regions which exhibit different degrees of electrical conductivity can be grouped together in order to form a device that can help perform a mathematical calculation or store information.
  • These groups of microscopically small regions or zones within one of the many layers of one monolithic chip are the modern analogs to the discretely packaged components which preceded them twenty and thirty years ago.
  • thermocompression bonding This process combines the application of heat and stress on an integrated circuit die.
  • a very small wedge-shaped probe or tool called a bonding wedge must be viewed through a microscope and guided over a wire which is to bonded onto a conductive pad.
  • the pad is usually located at the periphery of the semiconductor chip or die, which is placed on a heating device in order to soften the metallic material comprising the pad.
  • a refinement of the bonding wedge is called a nailhead or ball bonder, in which the pressure bonding tool consists of a glass capillary tube that feeds the wire through its center to the pad. A flame melts the end of the wire that protrudes out of the open end of the capillary tube and forms a ball having a diameter about twice the thickness of the wire. The wire is then retracted in the tube and the ball is held snugly against the orifice while the tube is moved over the pad and impressed upon it with considerable force.
  • the compression deforms the ball into a flattened thermocompression bond shaped like the head of a nail.
  • the tube is then pulled back from the pad, and the flame is employed again to melt the wire which is now attached to a pad on the die.
  • the wires and the contact pads are typically made of gold or aluminum.
  • thermocompression bonding has proven useful over many years of manufacturing, this method suffers from many shortcomings. Aside from the great expense incurred in either bonding wires and pads manually or with the aid of costly automated equipment, any mechanical connection like a pressure bond is susceptible to failure caused by a multitude of environmental factors. Since any fabrication process will be less than perfect, some wirebonds will be faulty after manufacturing. Even if only one percent of the connections are inadequate, the entire electronic system which includes the chip with the bad connection may be rendered completely inoperative as a consequence. Different rates of expansion and contraction of the connected materials due to changes in temperature will tend to destroy bonds over time. The ambient environment may contain compounds which will initiate chemical processes such as oxidation that may corrode and destroy metallic connections. The installation of subcomponents, handling, or vibration encountered during use may detach these wire bridges in time.
  • the wire bonds not only consume valuable horizontal surface area on the face of the die, but also take up space above the plane of the die.
  • the looped portions of the connecting wires can extend far above the die face and preclude the stacking of several levels of chip array planes.
  • Vizzer describes a modular component printed circuit connector in United States Patent Number 3,107,319.
  • This invention uses a modular component base block which is attached to printed circuit boards having end slots for the insertion ⁇ f circuit connector elements that are retained by spring loaded terminals.
  • a flat package for semiconductors which includes an insulating ceramic substrate having a channel that receives a semiconductor wafer that is bonded to a gold surface is disclosed in United States Patent Number 3,271,507—- Elliott.
  • Gogal describes a semiconductor device including a double cavity chip carrier which comprises a multi-layer ceramic sandwich structure that has a pair of chip cavities. The inventor claims that this structure is useful for connecting two integrated circuits which have different terminal patterns.
  • Minetti reveals a method of forming circuit packages using solid solder to bond a substrate and contact members in United States Patent Number 4,332,341.
  • Minetti's ceramic chip carrier includes a ceramic body with castellations formed at the edges of the carrier surfaces. Multi-layer contact members are coupled to contact pads which are, in turn, connected to leads from an integrated circuit chip.
  • Hall et al. explain a method of fabricating circuit packages which employ macro-components mounted on supporting substrates in United States Patent Number 4,352,449. In order to maintain sufficient clearance between components and the substrate and to achieve high reliability bonds, Hall employs massive solder preforms which are applied to contact pads on either the components or the substrate. This invention also involves the bonding of lead-tin solder spheres having a diameter of twenty to forty mils to contact pads on a chip carrier.
  • Larnerd et al. describe a method for aligning and supporting microcircuit devices on substrate conductors when the conductors are attached to the substrate.
  • a shaped, flexible, insulative material placed between the devices and their corresponding conductors supports terminals which can be fused together with heat in order to attach conductors after they have been properly aligned.
  • Beavitt et al. disclose an integrated circuit package including a number of conductors bonded between a cover and a cavity formed within a base that holds a chip in United States Patent Number 3,825,801. This cavity serves as a carrier for the chip, which is held in place between conductive strips of resilient material that are secured between a base and cover of insulating material.
  • Hargis A process for producing sets of small ceramic devices such as leadless inverted chip carriers that have solderable external connections is disclosed by Hargis in United States Patent Number 3,864,810. After firing several layers of ceramic material on a base sheet, Hargis mounts a chip on the ceramic carrier by embedding or encapsulating it in an epoxy resin in order to provide leads for the chip which are more easily connected to external devices than the chip terminals themselves.
  • Perrino reveals connecting structures for integrated circuit chips which are fabricated by forming many sets of leads on a flexible tape. These leads penetrate through holes formed in the tape and terminate in contacts which are arranged in a pattern that corresponds to a pattern of contacts on an integrated circuit chip. The chips are enclosed by an epoxy encapsulant after they are bonded to the contacts.
  • Hartleroad et al. explain a method and apparatus for positioning semiconductor flip chips onto one end of a transfer probe which automatically and magnetically aligns the chips and bonds them to an overlying lead frame structure.
  • Their method for placing flip chips into one end of an elongated, groove ⁇ f a positioning apparatus and conveying them on guide rails using a magnetic force to properly locate the chips before bonding is the subject of United States Patent Number 3,937,386.
  • An electrical package for Large Scale Integrated devices which utilizes solder technology to interconnect a carrier, a circuit transposer and LSI devices is described by Honn et al. in United States Patent 4,074,342.
  • the Honn electrical package includes a carrier which has a thermal expansion coefficient similar to semiconductive material, a standard array of terminal pins, and the transposer, which they claim eliminates mechanical stress on solder joints that is caused by dissimilar thermal expansion of the various packaging materials.
  • a flat package for an integrated circuit device that has output pads comprising a supporting member for the integrated circuit device, external output terminals, and array of output conductors, and an electrically insulating encapsulation cover is illustrated in Ugon's United States Patent Number 4,264,917.
  • This invention includes contact islands arranged on a supporting wafer to provide a package for one or more integrated circuit devices having a reduced thickness and surface area.
  • None of the inventions described above solves the problem of wasted planar and orthogonal space that results from the high portion of chip assemblies that are devoted to chip interconnections such as wirebonds. None of these prior methods or apparatus provides an effective and comprehensive solution which addresses all of the complex aspects of achieving ultra-high density of active semiconductor components. Such a solution to this problem would satisfy a long felt need experience by the semiconductor and integrated circuit industries for over three decades.
  • a truly practical and reliable means for producing efficacious intra-chip and chip-to-chip interconnections without squandering a substantial portion of the die's planar and orthogonal space would constitute a fliajor advancement in the microelectronics field.
  • Manufacturers ⁇ f semiconductor dies could employ such an innovative design to produce integrated circuits capable of processing information at speeds greatly exceeding the current state of the art and and capable of storing vast quantities of data far beyond today's most densely packed designs.
  • Such an invention would ideally be suited to operate in cooperation with a wide variety of computing systems and would perform consistently and reliably over a wide range of operating conditions and system applications.
  • Extremely Large Scale Integration microcircuitry would also satisfy the rigorous demands of supercomputers and orbital defense systems.
  • An invention which enables aerospace microelectronic designers to deploy enormously powerful yet extremely compact integrated circuits in orbit for space defense systems would most certainly constitute a major technological advancement in the electronics arts.
  • the aim of the present invention is to help accomplish this major technological advancement.
  • the Patraw Chip Interface Mesa enables designers of integrated circuits to connect the integrated circuits together in order to form unitary, on-wafer chip arrays which have signal processing and memory capacities that dwarf previous previous discretely connected, multiple integrated circuit systems.
  • the present invention extends the current state of the art beyond Very Large Scale Integration (VLSI) capabilities to the higher range of Ultra-Dense, Extremely Large Scale Integration (ELSI) using the wafer scale synthesis techniques described and claimed below.
  • VLSI Very Large Scale Integration
  • ELSI Extremely Large Scale Integration
  • the chip interface mesa is fabricated from an dielectric material and has a generally rectangular shape having dimensions that are generally slightly smaller than the semiconductor die upon which it resides.
  • the mesa has a rectangular cross-section and may be epoxied to the tap of the die which bears the uppermost level of active circuitry.
  • the perimeter of the mesa is populated by vertical channels or notches which are coated with a layer of conductive material.
  • the top face of the mesa contains an array of conductive regions or external interface pads which are much larger than conventional bond pads. These external interface pads are electrically coupled to a notch on the side wall of the mesa by a thin conductive pathway. Each notch in the mesa is aligned with a conductive chip interface pad on the semiconductor chip.
  • the chip interface pads are deployed on the periphery of the top surface of the chip which is bonded to the mesa.
  • a drop of heated solder or other easily deformable conductive material is placed in each notch from above the mesa and forms an electrical link between the mesa and a chip interface pad, since the solder joins with both the pad and the vertical walls of the notch.
  • This microelectronic packaging configuration constitutes an important improvement and refinement of the Patraw Inverted Chip Carrier, which substantially eliminates long looped wirebonds by redirecting intra-chip and chip-to-chip interconnections to orthogonal space over the active circuitry of the chip.
  • the present invention eliminates wirebonds completely.
  • All undesirable wire couplers are supplanted by durable and easily formed solder droplet connections inside a notch which is in registry with a corresponding chip pad.
  • the repositioning of intra-chip and chip-to-chip interconnections into space over the active circuitry optimizes packaging space for integrated circuit assemblies and enables designers to approach the theoretical density limit for semiconductor devices due to the enormous saving of space which was once wasted by wirebonds between adjacent chips.
  • the present invention reserves nearly all of the planar space of a multi-chip array for active semiconductor circuitry, and banishes inefficient interconnection space to a volume over or orthogonal to the plane of the active circuitry.
  • This important new integrated circuit assembly design not only optimizes packaging criteria, but also permits the stacking of many parallel levels of contiguous chips with a minimum of costly inter-chip spacing. By connecting many chips together, many semiconductor dies on a wafer can be combined in order to realize full, wafer-scale reconstruction.
  • an object of the present invention to provide an apparatus for microelectronic interconnection which completely eliminates undesirable and unreliable wirebonds.
  • Still another object of the present invention is to provide a means of connecting large numbers of semiconductor dies using currently commercially available dies and existing packaging technology.
  • Yet another object of the invention is to provide chip arrays having increased system speeds due to drastic reductions in propagation delay times which results from the total elimination of interconnecting wires.
  • Another object of the present invention is to provide a method of installing many chips together on a chip carri er which may be easily tested, inspected, burned-in, and repaired.
  • Still another object of this invention is to provide a chip deployment scheme which minimizes chip-to-chip input/output requirements.
  • FIG. 1 is a side elevational perspective view of the present invention showing a mesa atop a semiconductor die.
  • the mesa has conductive mesa interface pads on its top face and has notches cut in its sidewalls that are aligned with chip interface pads on the boundaries ⁇ f the top surface of the chip.
  • FIG. 2 is a cross-sectional view of the present invention that illustrates solder droplets connecting the coated conductive walls of the mesa notches with chip interface pads.
  • FIG. 3 is a tap view of the present invention depicting an array of oversized mesa interface pads which are each connected to a notch in a sidewall of the mesa by conductive pathways.
  • FIG. 1 depicts a chip interface mesa and chip assembly 10 in a perspective view.
  • Mesa 12 is made from undoped silicon and has a top surface 14 and sidewalls 16.
  • the mesa 12 has first and second planar axes that are respectively parallel to the length and width dimensions of the mesa.
  • the transverse axis of the mesa runs perpendicular to the two planar axes and spans the height of the mesa.
  • the sidewalls 16 contain notches 18 which are vertical channels that have been abrasively ground, chemically etched, or laser drilled into mesa 12.
  • these vertical conductor means which implement chip interconnections in space which is orthogonal to rather than coplanar with the active circuitry of the chip, are V-shaped grooves extending transversely across the narrowest dimension of the mesa 12.
  • the faces of the notches 18 are coated with a layer of conductive material such as copper.
  • the best mode of the present invention employs vapor deposition techniques that are well known in the art to coat the notches 18.
  • the top of the mesa 12 contains an array of conductive mesa interface pads 22 that are joined to the conductive coating of the notches 18 by conductive pathways 20. These pads are oversized compared to size of conventional wirebond pads in order to provide a convenient means of external connection to the mesa-chip assembly 10.
  • FIG. 2 reveals a semiconductor die or chip 24 after it has been brought into alignment two to four mils below mesa 12.
  • the chip 24 and mesa 12 are aligned so that the two planar axes of each, which extend parallel to the length and width dimensions of both the mesa and chip, are substantially parallel.
  • Each notch 18 is substantially centered over a chip interface pad 28 which is, in turn, connected to the active circuitry 25 on the semiconductor substrate via conductive pathways 27 that is hidden from view by the mesa 12.
  • Conventional epoxies may be used to permanently attach mesa 12 to chip 24. Both the mechanical support and electrical couplings between chip 24 and mesa 12 are provided by solder drops 26.
  • FIG. 3 illustrates a complete mesa-chip assembly
  • the notches 18 need not be disposed perpendicular to the top planar mesa surface
  • the notches may be sloped, curved upward, or generally formed in any useful configuration, so long as they provide adequate mechanical support and electrical coupling for the mesa 12.
  • Another great advantage of the solder droplets 26 is that complex and expensive internal interconnections within chip carriers, such as those employed in the Patraw Inverted Chip Carrier, are completely avoided in the Patraw Chip Interface Mesa.
  • the Patraw Inverted Chip Carrier which is described in detail in a related copending patent application, enables a designer ordinarily skilled in the art to take a current, commercially available chip, place that chip in this new carrier, and realize an enormous increase in volume available for active circuitry of 65% for only a tiny 3% increase in planar area compared to the bare die dimensions.
  • the Patraw Chip Interface Mesa provides even greater volume to surface area ratios by completely eliminating all wirebonds. Nearly all the inter-chip spacing required in conventional manufacturing techniques is avoided by employing solder droplets in mesa receptacles that extend perpendicular to the plane of the chip's active circuitry to form the electrical interconnections between the chip and the outside world.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

L'appareil ci-décrit permet d'obtenir des connexions micro-électroniques intra-puces et de puce-à-puce dans une configuration de circuits intégrés ultradense. Un assemblage mésa à interface de puces et un assemblage de puces (10) comprend un élément mésa (12) ayant une surface plane supérieure mésa (14) et des parois latérales (16). Le périmètre de l'élément mésa (12) comprend plusieurs encoches (18) revêtues chacune d'une couche conductrice. Les encoches sont couplées électriquement à des terminaux conducteurs (22) d'interfaces mésa par l'intermédiaire de voies d'accès conductrices (20). Une puce (24) de semiconducteur ayant une surface supérieure (25) servant de support à un ensemble de circuits actifs peut être liée à la partie inférieure de l'élément mésa (12) à l'aide d'un adhésif époxy. Chaque encoche (18) est alignée sur une pastille d'interfaces conductrices correspondantes (28) placée sur la surface supérieure (25) de la puce (24). Des goutelettes de soudure (26) sont placées sur les pastilles d'interface de puces (28) et sont couplées mécaniquement et électriquement à l'élément mésa (12) par l'intermédiaire d'une couche conductrice placée sur chaque encoche (18). La présente invention permet d'éliminer totalement les fils de liaison enroulés indésirables et inutiles et permet d'obtenir une augmentation substantielle du volume disponible par zone de matrice plane pour chaque ensemble de circuits actifs.The apparatus described here makes it possible to obtain intra-microchip and chip-to-chip connections in a configuration of ultra-dense integrated circuits. A chip interface mesa assembly and a chip assembly (10) includes a mesa element (12) having a mesa top planar surface (14) and side walls (16). The perimeter of the mesa element (12) comprises several notches (18) each coated with a conductive layer. The notches are electrically coupled to conductive terminals (22) of mesa interfaces via conductive access paths (20). A semiconductor chip (24) having an upper surface (25) serving as a support for a set of active circuits can be bonded to the lower part of the mesa element (12) using an epoxy adhesive. Each notch (18) is aligned on a patch of corresponding conductive interfaces (28) placed on the upper surface (25) of the chip (24). Solder droplets (26) are placed on the chip interface pads (28) and are mechanically and electrically coupled to the mesa element (12) via a conductive layer placed on each notch (18) . The present invention makes it possible to completely eliminate unwanted and unnecessary coiled connection wires and makes it possible to obtain a substantial increase in the volume available per plane matrix zone for each set of active circuits.

Description

CHIP INTERFACE MESA
BACKGROUND OF THE INVENTION
1. Cross Reference to Related Patent Applications.
The present patent application is related to a pending patent application entitled "Inverted Chip Carrier", also invented by Nils E. Patraw and assigned to the Hughes Aircraft Company.
2. Field of the Invention.
The present invention pertains to Ultra-Dense, Extremely Large Scale Integration and wafer scale synthesis of microelectronic components residing on a large number of integrated circuits. The specific focus of the preferred embodiment is the planar and orthogonal space optimization of active Microelectronic circuit elements which Makes possible Multi-chip VHSIC hybrids having extraordinarily high signal processing capabilities and enormous memory capacity.
3. Background Information.
Over the past four decades, the electronics industry has witnessed vast improvements in the performance of electronic components. The transition from thermo-ionic devices to solid state diodes and transistors was the first phase of intense efforts to miniaturize circuitry in order to construct powerful digital computers. The second great phase of innovation involved the consolidation of discrete solid state devices into a compact, unitary circuit which shared a single housing. Before the advent of integrated circuits, components like transistors were individually encapsulated in plastic cases or resided separately in metal cans. These single elements were generally Mounted on circuit boards and each had a number of leads connected together by soldered wires. The first generation of integrated circuits combined many discrete active elements together on several alternating layers of metallic and dielectric films which were deposited on an insulating substrate. These early integrated circuits, called thin-film hybrids, were the precursors of current integrated circuits which contain a solitary, but extremely powerful and densely packed, semiconductor chip or die. This semiconductor chip comprises a base or substrate of material, upon which many thin layers are formed that are, in turn, coupled together by tiny, metallic interconnects or vias which pass vertically through the several horizontal layers. A semiconductive material such as silicon, germanium, or gallium arsenide can be chemically altered in order to form carefully selected, minute regions having different electrical properties. These distinct regions are now fabricated with great precision, and each region may measure less than one millionth of an inch. A few regions which exhibit different degrees of electrical conductivity can be grouped together in order to form a device that can help perform a mathematical calculation or store information. These groups of microscopically small regions or zones within one of the many layers of one monolithic chip are the modern analogs to the discretely packaged components which preceded them twenty and thirty years ago.
As each phase of electronic components produced improvements in calculation speed and memory capacity, the packaging of these components became more and more important. Technological advancements that solve problems concerning the fabrication or further miniaturization of semiconductor materials and devices simultaneously create a concomitant packaging problem. As circuit components shrink to increasingly smaller dimensions, the problem of accessing each component grows worse. When integrated circuits become so densely packed that a million of separate active devices occupy a space smaller than the diameter of the eraser on a common pencil, the difficulties involved in exchanging information in the form of electrical signals between that vast network of tiny circuit elements and the outside world become enormous. Another level of complication is reached when designers attempt to connect many integrated circuits together in a unitary system. Semiconductor chips which are shorter than the width of the eraser at the end of the pencil and less than two one hundreths of and inch thich are manufacturer simultaneously by the hundreds on thin circular wafers of semiconductive material that are typically about four inches wide. Recent attempts to couple all the separate chips on the wafer gave rise to the term wafer scale integration. An electronic device which could incorporate tens, hundreds, or perhaps even thousands or millions of already immensely powerful separate chips, each comprising roughly a million active components, together on one wafer would constitute a tremendous technological leap forward in the electronics arts.
Among the most serious problems encountered in designing and manufacturing integrated circuits and multiple integrated circuit arrays are the deleterious consequences of using fine filaments of wire to connect the miniscule terminals or pads which are the access points to the outside world from the internal circuitry of the integrated circuit. These fragile, very light gauge connecting wires are typically one one-thousanth of an inch in diameter. One common technique for attaching these wires or leads to the conductive external terminals of the chip is thermocompression bonding. This process combines the application of heat and stress on an integrated circuit die. A very small wedge-shaped probe or tool called a bonding wedge must be viewed through a microscope and guided over a wire which is to bonded onto a conductive pad. The pad is usually located at the periphery of the semiconductor chip or die, which is placed on a heating device in order to soften the metallic material comprising the pad. A refinement of the bonding wedge is called a nailhead or ball bonder, in which the pressure bonding tool consists of a glass capillary tube that feeds the wire through its center to the pad. A flame melts the end of the wire that protrudes out of the open end of the capillary tube and forms a ball having a diameter about twice the thickness of the wire. The wire is then retracted in the tube and the ball is held snugly against the orifice while the tube is moved over the pad and impressed upon it with considerable force. The compression deforms the ball into a flattened thermocompression bond shaped like the head of a nail. The tube is then pulled back from the pad, and the flame is employed again to melt the wire which is now attached to a pad on the die. The wires and the contact pads are typically made of gold or aluminum.
Although thermocompression bonding has proven useful over many years of manufacturing, this method suffers from many shortcomings. Aside from the great expense incurred in either bonding wires and pads manually or with the aid of costly automated equipment, any mechanical connection like a pressure bond is susceptible to failure caused by a multitude of environmental factors. Since any fabrication process will be less than perfect, some wirebonds will be faulty after manufacturing. Even if only one percent of the connections are inadequate, the entire electronic system which includes the chip with the bad connection may be rendered completely inoperative as a consequence. Different rates of expansion and contraction of the connected materials due to changes in temperature will tend to destroy bonds over time. The ambient environment may contain compounds which will initiate chemical processes such as oxidation that may corrode and destroy metallic connections. The installation of subcomponents, handling, or vibration encountered during use may detach these wire bridges in time.
In addition to the nettlesome problems of keeping a wire bond intact over the life of an electronic device, this mode of connecting portions of one chip or an array of many chips is beset by problems even if all the bonds are perfectly made and are never broken. The vast number of wire bonds needed to connect large numbers of chips result in an enormous total length of conductive pathways in the system circuit. These conductors consume electrical power since they are resistive components. Increased ambient temperature caused by this thermal heating may impair the operation of the associated integrated circuits. The wires inject unwanted inductance and capacitance into otherwise precisely balanced circuits. Crosstalk between conductors may severely impair the performance of the entire system. Time delays inherent in the long pathways reduce computation capability.
Perhaps the worst problem is the enormous space which is wasted when wires are used to connect together portions of a chip or an array of many chips. Each span of wire that connects two points which reside substantially in the same plane requires a looped, generally parabolic length of bent wire. The amount by which the wire can be bent is limited by the fragility and susceptibility of the wire to fracture. In addition, the size of the wire bonding tool mandates a minimum spacing between contact points which receive thermocompression bonds. These loops of wire impose limits on the horizontal density of the chip deployment, since a minimum space for each loop must be provided between each adjacent chip. Conventional wire bonding techniques impose die interspacing contraints of no less than twice the thickness of the die. If the die is on the order of twenty mils of an inch in height, as much as fifty mils will be wasted in order to provide adequate separation for the making the wire bonds. The pads which receive the wire bonds al so consume precious space on the die. Each pad must be large and sturdy enough to tolerate the great pressure transmitted by the wire bond tool. The wire bonds not only consume valuable horizontal surface area on the face of the die, but also take up space above the plane of the die. The looped portions of the connecting wires can extend far above the die face and preclude the stacking of several levels of chip array planes. When connecting wires consume space above or below the active die surface, the vertical or orthogonal space that extends perpendicular to the active circuitry must be reserved for protruding wires. These exposed wires are vulnerable to a host of environmental hazards including physical shock, vibration, extremes of temperature and damage during the assembly process.
Previous microcircuit connection and wafer scale integration inventions have attempted to solve the deployment and packaging problems inherent in combining and connecting millions of active circuit components using a variety of approaches. In United States Patent Number 2,850,681, Horton discloses a subminiature structure for electrical apparatus which includes a combination of a plurality αf wafers made of rigid insulating material, conductors fixed to each wafer, and connections between the electrical components on these wafers.
Vizzer describes a modular component printed circuit connector in United States Patent Number 3,107,319. This invention uses a modular component base block which is attached to printed circuit boards having end slots for the insertion αf circuit connector elements that are retained by spring loaded terminals.
A flat package for semiconductors which includes an insulating ceramic substrate having a channel that receives a semiconductor wafer that is bonded to a gold surface is disclosed in United States Patent Number 3,271,507—- Elliott.
In United States Patent Number 4,288,841, Gogal describes a semiconductor device including a double cavity chip carrier which comprises a multi-layer ceramic sandwich structure that has a pair of chip cavities. The inventor claims that this structure is useful for connecting two integrated circuits which have different terminal patterns.
Minetti reveals a method of forming circuit packages using solid solder to bond a substrate and contact members in United States Patent Number 4,332,341. Minetti's ceramic chip carrier includes a ceramic body with castellations formed at the edges of the carrier surfaces. Multi-layer contact members are coupled to contact pads which are, in turn, connected to leads from an integrated circuit chip. Hall et al. explain a method of fabricating circuit packages which employ macro-components mounted on supporting substrates in United States Patent Number 4,352,449. In order to maintain sufficient clearance between components and the substrate and to achieve high reliability bonds, Hall employs massive solder preforms which are applied to contact pads on either the components or the substrate. This invention also involves the bonding of lead-tin solder spheres having a diameter of twenty to forty mils to contact pads on a chip carrier.
In United States Patent Number 3,811,186, Larnerd et al. describe a method for aligning and supporting microcircuit devices on substrate conductors when the conductors are attached to the substrate. A shaped, flexible, insulative material placed between the devices and their corresponding conductors supports terminals which can be fused together with heat in order to attach conductors after they have been properly aligned. Beavitt et al. disclose an integrated circuit package including a number of conductors bonded between a cover and a cavity formed within a base that holds a chip in United States Patent Number 3,825,801. This cavity serves as a carrier for the chip, which is held in place between conductive strips of resilient material that are secured between a base and cover of insulating material.
A process for producing sets of small ceramic devices such as leadless inverted chip carriers that have solderable external connections is disclosed by Hargis in United States Patent Number 3,864,810. After firing several layers of ceramic material on a base sheet, Hargis mounts a chip on the ceramic carrier by embedding or encapsulating it in an epoxy resin in order to provide leads for the chip which are more easily connected to external devices than the chip terminals themselves. In United States Patent Number 3,868,724, Perrino reveals connecting structures for integrated circuit chips which are fabricated by forming many sets of leads on a flexible tape. These leads penetrate through holes formed in the tape and terminate in contacts which are arranged in a pattern that corresponds to a pattern of contacts on an integrated circuit chip. The chips are enclosed by an epoxy encapsulant after they are bonded to the contacts.
Hartleroad et al. explain a method and apparatus for positioning semiconductor flip chips onto one end of a transfer probe which automatically and magnetically aligns the chips and bonds them to an overlying lead frame structure. Their method for placing flip chips into one end of an elongated, groove αf a positioning apparatus and conveying them on guide rails using a magnetic force to properly locate the chips before bonding is the subject of United States Patent Number 3,937,386. An electrical package for Large Scale Integrated devices which utilizes solder technology to interconnect a carrier, a circuit transposer and LSI devices is described by Honn et al. in United States Patent 4,074,342. The Honn electrical package includes a carrier which has a thermal expansion coefficient similar to semiconductive material, a standard array of terminal pins, and the transposer, which they claim eliminates mechanical stress on solder joints that is caused by dissimilar thermal expansion of the various packaging materials.
Inoue discloses a semiconductor device insulation method in United States Patent Number 4,143,456. This invention employs a protective covering for a semiconductor device which includes a circuit board bearing a conductive pattern and a chip. Inoue fixes his chip with a eutectic or electrically connected adhesive to a die bonded portion of the circuit board pattern with aluminum wire. United States Patent Number 4,147,889-- Andrews et al. describe a thin, dielectric, dish-shaped chip carrier which has flexible mounting flanges having plated or bonded solderable conductive traces and paths. These traces and paths are coupled with plated or bonded heat sinks which are electrically grounded and provide structural integrity.
A flat package for an integrated circuit device that has output pads comprising a supporting member for the integrated circuit device, external output terminals, and array of output conductors, and an electrically insulating encapsulation cover is illustrated in Ugon's United States Patent Number 4,264,917. This invention includes contact islands arranged on a supporting wafer to provide a package for one or more integrated circuit devices having a reduced thickness and surface area.
None of the inventions described above solves the problem of wasted planar and orthogonal space that results from the high portion of chip assemblies that are devoted to chip interconnections such as wirebonds. None of these prior methods or apparatus provides an effective and comprehensive solution which addresses all of the complex aspects of achieving ultra-high density of active semiconductor components. Such a solution to this problem would satisfy a long felt need experience by the semiconductor and integrated circuit industries for over three decades.
A truly practical and reliable means for producing efficacious intra-chip and chip-to-chip interconnections without squandering a substantial portion of the die's planar and orthogonal space would constitute a fliajor advancement in the microelectronics field. Manufacturers αf semiconductor dies could employ such an innovative design to produce integrated circuits capable of processing information at speeds greatly exceeding the current state of the art and and capable of storing vast quantities of data far beyond today's most densely packed designs. Such an invention would ideally be suited to operate in cooperation with a wide variety of computing systems and would perform consistently and reliably over a wide range of operating conditions and system applications. Extremely Large Scale Integration microcircuitry would also satisfy the rigorous demands of supercomputers and orbital defense systems. An invention which enables aerospace microelectronic designers to deploy enormously powerful yet extremely compact integrated circuits in orbit for space defense systems would most certainly constitute a major technological advancement in the electronics arts.
SUMMARY OF THE INVENTION
The aim of the present invention is to help accomplish this major technological advancement. The Patraw Chip Interface Mesa enables designers of integrated circuits to connect the integrated circuits together in order to form unitary, on-wafer chip arrays which have signal processing and memory capacities that dwarf previous previous discretely connected, multiple integrated circuit systems. The present invention extends the current state of the art beyond Very Large Scale Integration (VLSI) capabilities to the higher range of Ultra-Dense, Extremely Large Scale Integration (ELSI) using the wafer scale synthesis techniques described and claimed below.
The chip interface mesa is fabricated from an dielectric material and has a generally rectangular shape having dimensions that are generally slightly smaller than the semiconductor die upon which it resides. The mesa has a rectangular cross-section and may be epoxied to the tap of the die which bears the uppermost level of active circuitry. The perimeter of the mesa is populated by vertical channels or notches which are coated with a layer of conductive material. The top face of the mesa contains an array of conductive regions or external interface pads which are much larger than conventional bond pads. These external interface pads are electrically coupled to a notch on the side wall of the mesa by a thin conductive pathway. Each notch in the mesa is aligned with a conductive chip interface pad on the semiconductor chip. The chip interface pads are deployed on the periphery of the top surface of the chip which is bonded to the mesa. A drop of heated solder or other easily deformable conductive material is placed in each notch from above the mesa and forms an electrical link between the mesa and a chip interface pad, since the solder joins with both the pad and the vertical walls of the notch. This microelectronic packaging configuration constitutes an important improvement and refinement of the Patraw Inverted Chip Carrier, which substantially eliminates long looped wirebonds by redirecting intra-chip and chip-to-chip interconnections to orthogonal space over the active circuitry of the chip. The present invention eliminates wirebonds completely. All undesirable wire couplers are supplanted by durable and easily formed solder droplet connections inside a notch which is in registry with a corresponding chip pad. The repositioning of intra-chip and chip-to-chip interconnections into space over the active circuitry optimizes packaging space for integrated circuit assemblies and enables designers to approach the theoretical density limit for semiconductor devices due to the enormous saving of space which was once wasted by wirebonds between adjacent chips. The present invention reserves nearly all of the planar space of a multi-chip array for active semiconductor circuitry, and banishes inefficient interconnection space to a volume over or orthogonal to the plane of the active circuitry. This important new integrated circuit assembly design not only optimizes packaging criteria, but also permits the stacking of many parallel levels of contiguous chips with a minimum of costly inter-chip spacing. By connecting many chips together, many semiconductor dies on a wafer can be combined in order to realize full, wafer-scale reconstruction.
It is, therefore, an object of the present invention to provide an apparatus for microelectronic interconnection which completely eliminates undesirable and unreliable wirebonds.
Another object of the present invention is to provide apparatus for micro-miniature electronic interconnection which maximizes the density of active, integrated circuit devices in a given volume. Another object of this invention is to provide a simple and reliable means of connecting circuits within a chip or connecting circuits within many different chips in order to make previously impossible wafer-scale synthesis designs practical and cost-effective.
Still another object of the present invention is to provide a means of connecting large numbers of semiconductor dies using currently commercially available dies and existing packaging technology.
Yet another object of the invention is to provide chip arrays having increased system speeds due to drastic reductions in propagation delay times which results from the total elimination of interconnecting wires.
It is also an object αf this invention to provide a chip carrier which enables designers to take advantage of enormous reductions in power consumption, since the elimination of a multitude of long wirebonds dispenses with a primary source of wasteful, capacitive loading.
Another object of the present invention is to provide a method of installing many chips together on a chip carri er which may be easily tested, inspected, burned-in, and repaired.
Still another object of this invention is to provide a chip deployment scheme which minimizes chip-to-chip input/output requirements.
It is a further object of this invention to provide a technique for coupling integrated circuits that inherently protects interconnections from physical damage by placing solder droplets in sheltered notches in the sidewalls αf a chip interface mesa. Yet another object of the invention claimed below is to provide apparatus for microelectronic interconnection which avoids the deleterious additional capacitance and inductance that are introduced by prior devices which incorporate many long wire connectors within integrated circuit assemblies.
It is also an object of the present invention to cut down the mass of integrated circuit systems in order to fabricate systems which can be economically placed in an orbital environment.
An appreciation of other aims and objects of the present invention and a more complete and comprehensive understanding of the this invention may be achieved by studying the following description of a preferred embodiment and by referring to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a side elevational perspective view of the present invention showing a mesa atop a semiconductor die. The mesa has conductive mesa interface pads on its top face and has notches cut in its sidewalls that are aligned with chip interface pads on the boundaries αf the top surface of the chip.
FIG. 2 is a cross-sectional view of the present invention that illustrates solder droplets connecting the coated conductive walls of the mesa notches with chip interface pads.
FIG. 3 is a tap view of the present invention depicting an array of oversized mesa interface pads which are each connected to a notch in a sidewall of the mesa by conductive pathways.
DESCRIPTION OF A PREFERRED EMBODIMENT
FIG. 1 depicts a chip interface mesa and chip assembly 10 in a perspective view. Mesa 12 is made from undoped silicon and has a top surface 14 and sidewalls 16. The mesa 12 has first and second planar axes that are respectively parallel to the length and width dimensions of the mesa. The transverse axis of the mesa runs perpendicular to the two planar axes and spans the height of the mesa. The sidewalls 16 contain notches 18 which are vertical channels that have been abrasively ground, chemically etched, or laser drilled into mesa 12. In the preferred embodiment, these vertical conductor means, which implement chip interconnections in space which is orthogonal to rather than coplanar with the active circuitry of the chip, are V-shaped grooves extending transversely across the narrowest dimension of the mesa 12. The faces of the notches 18 are coated with a layer of conductive material such as copper. The best mode of the present invention employs vapor deposition techniques that are well known in the art to coat the notches 18. The top of the mesa 12 contains an array of conductive mesa interface pads 22 that are joined to the conductive coating of the notches 18 by conductive pathways 20. These pads are oversized compared to size of conventional wirebond pads in order to provide a convenient means of external connection to the mesa-chip assembly 10.
FIG. 2 reveals a semiconductor die or chip 24 after it has been brought into alignment two to four mils below mesa 12. The chip 24 and mesa 12 are aligned so that the two planar axes of each, which extend parallel to the length and width dimensions of both the mesa and chip, are substantially parallel. Each notch 18 is substantially centered over a chip interface pad 28 which is, in turn, connected to the active circuitry 25 on the semiconductor substrate via conductive pathways 27 that is hidden from view by the mesa 12. Conventional epoxies may be used to permanently attach mesa 12 to chip 24. Both the mechanical support and electrical couplings between chip 24 and mesa 12 are provided by solder drops 26. Conventional heated lead-tin solder is wicked into the notches 18 by dipping mesa 12 in molten solder after the faces of the notches 18 have been treated with CrCuAu or CuAu in order to make them solder-wettable. The chip interface pads 28 are also pretreated with wetting material. The soldering process is performed in a heated nitrogen atmosphere in order to achieve the tear-drop shape shown in FIG. 2. The notches 18 may be shaped in any configuration which will receive a mass or drop 28 of conductive material which will electrically couple the mesa 12 to chip 24 through pads 28. Automated fabrication processes can be employed to form hundreds or thousands of these solder drop connections simultaneously. Any alloy or conductive substance which can form the electrical coupling between conductive surfaces of the notches 18 and the chip interface pads 28 may be utilized without departing from the essence of the present invention. FIG. 3 illustrates a complete mesa-chip assembly
10 in a top view. This drawing shows a typical arrangement for an actual 188 mil by 220 mil random access memory chip. The contact pads 22 are twenty to twenty-five mils square. These pads are enormous compared to conventional four mil square chip pads encountered in prior designs. The increased surface area provided by the present invention makes it easier to connect a chip to external devices and also greatly enhances the testability of the chip and inspectability of the input and output pad connections. The ductility of the solder joints also inherently compensates for mechanical stress resulting from thermal dissimilarities that are caused by varying amounts of heat which are generated during operation of the electrical components on the chip. Another great advantage of this design is that the solder droplets 26 are also completely visible, in comparison to previous
"flipped-chip" packaging designs. In an alternative embodiment of the invention, the notches 18 need not be disposed perpendicular to the top planar mesa surface
14. The notches may be sloped, curved upward, or generally formed in any useful configuration, so long as they provide adequate mechanical support and electrical coupling for the mesa 12. Another great advantage of the solder droplets 26 is that complex and expensive internal interconnections within chip carriers, such as those employed in the Patraw Inverted Chip Carrier, are completely avoided in the Patraw Chip Interface Mesa.
The Patraw Inverted Chip Carrier, which is described in detail in a related copending patent application, enables a designer ordinarily skilled in the art to take a current, commercially available chip, place that chip in this new carrier, and realize an enormous increase in volume available for active circuitry of 65% for only a tiny 3% increase in planar area compared to the bare die dimensions. The Patraw Chip Interface Mesa provides even greater volume to surface area ratios by completely eliminating all wirebonds. Nearly all the inter-chip spacing required in conventional manufacturing techniques is avoided by employing solder droplets in mesa receptacles that extend perpendicular to the plane of the chip's active circuitry to form the electrical interconnections between the chip and the outside world.
Although the present invention has been described in detail with reference to a particular preferred embodiment, persons possessing ordinary skill in the art to which this invention pertains will appreciate that various modifications and enhancements may be made without departing from the spirit and scope of the invention.

Claims

CLAIMSWhat is claimed is:
1. Apparatus for Microelectronic interconnection comprising:
a mesa Member made from a di electric material having:
a first planar axis extending parallel to the longest planar dimension of said mesa member,
a second planar axis extending parallel to
the second longest planar dimension of said mesa member,
a transverse axis extending perpendicular to both said first and second planar axes,
a top planar Mesa surface extending substantially perpendicular to said transverse axis and bounded by said longest and said shortest planar dimensions of said mesa Member,
a plurality of planar perimeter walls disposed generally parallel to said transverse axis,
a plurality of vertical electrical coupler means located substantially near said planar perimeter walls,
said plurality of vertical electrical coupler means each having a vertical dimension which
is substantially parallel to said transverse axis of said mesa member,
said plurality of vertical electrical coupler means each further having a conductive coating extending along said vertical dimension of said coupler means,
a plurality of mesa interface conductive terminals disposed upon said top planar mesa surface,
said plurality of mesa interface conductive terminals disposed upon said top planar mesa surface being electrically coupled to a plurality of conductive pathways which are mechanically coupled to said top planar mesa surface,
said plurality of conductive pathways being further selectively and electrically coupled to said vertical electrical coupler means,
a semiconductor chip having two planar dimensions corresponding to said chip's two longest dimensions of length and width;
said semiconductor chip further having a top chip surface bounded by said two planar dimensions which contains an uppermost layer of active circuitry;
said chip further having a plurality of chip interface means deployed upon said top chip surface and generally surrounding said uppermost layer of active circuitry;
said plurality of chip interface means also being selectively connected to said active circuitry and disposed generally at the periphery of said top chip surface;
said semiconductor chip being mechanically coupled to said mesa member so that said top chip surface is substantially adjacent to said mesa member; and
said plurality of chip interface means also being selectively and electrically coupled to said vertical electrical coupler means by a plurality of mesa-chip electrical contact means.
2. Apparatus as claimed in Claim 1 in which said mesa member is made from undoped silicon.
3. Apparatus as claimed in Claim 1 in which said vertical electrical coupler means arm V-shaped notches cut in said planar perimeter walls of said mesa member and arm also pretinned with solder and precoated with a solder-wetting agent.
4. Apparatus as claimed in Claim 1 in which said mesa interface conductive terminals are metallized pads which have been placed on said top planar mesa surface by a chemical vapor deposition process.
5. Apparatus as claimed in Claim 1 in which said conductive pathways are metallized strips which have been placed on said top planar mesa surface by a chemical vapor deposition process.
6. Apparatus as claimed in Claim 1 in which said chip interface means are conductive bond pads.
7. Apparatus as claimed in Claim 1 in which each of said vertical electrical coupler means arm each electrically coupled to only one mesa-chip electrical contact means.
8. Apparatus as claimed in Claim 1 in which each of said vertical electrical coupler means is substantially aligned in registry with only one of said chip interface means.
9. Apparatus as claimed in Claim 1 in which said mesa-chip electrical contact means are drops of solder placed in electrical communication with said chip interface means and with said vertical electrical coupler means.
10. Apparatus as claimed in Claim 1 in which said mesa member end said chip are mechanically coupled by a layer of epoxy adhesive.
11. Apparatus as claimed in Claim 1 in which said mesa member has said first and second planar dimensions which arm slightly smaller than said two planar dimensions of said chip.
EP87900403A 1985-12-20 1986-11-24 Chip interface mesa Ceased EP0250541A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81123985A 1985-12-20 1985-12-20
US811239 1985-12-20

Publications (1)

Publication Number Publication Date
EP0250541A1 true EP0250541A1 (en) 1988-01-07

Family

ID=25205984

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87900403A Ceased EP0250541A1 (en) 1985-12-20 1986-11-24 Chip interface mesa

Country Status (7)

Country Link
EP (1) EP0250541A1 (en)
JP (1) JPS63502071A (en)
KR (1) KR900004719B1 (en)
ES (1) ES2002443A6 (en)
IL (1) IL80683A0 (en)
TR (1) TR22838A (en)
WO (1) WO1987004010A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3923533A1 (en) * 1989-07-15 1991-01-24 Diehl Gmbh & Co ARRANGEMENT OF AN INTEGRATED CIRCUIT ON A CIRCUIT BOARD
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1258660A (en) * 1969-12-19 1971-12-30
JPS58151B2 (en) * 1978-09-14 1983-01-05 宮川化成工業株式会社 Method for manufacturing terminal lead-out portion of storage battery
US4352449A (en) * 1979-12-26 1982-10-05 Bell Telephone Laboratories, Incorporated Fabrication of circuit packages
US4549247A (en) * 1980-11-21 1985-10-22 Gao Gesellschaft Fur Automation Und Organisation Mbh Carrier element for IC-modules
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices
KR900001273B1 (en) * 1983-12-23 1990-03-05 후지쑤 가부시끼가이샤 Semiconductor integrated circuit device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8704010A1 *

Also Published As

Publication number Publication date
WO1987004010A1 (en) 1987-07-02
JPS63502071A (en) 1988-08-11
KR880701020A (en) 1988-04-13
KR900004719B1 (en) 1990-07-05
TR22838A (en) 1988-08-22
ES2002443A6 (en) 1988-08-01
IL80683A0 (en) 1987-02-27

Similar Documents

Publication Publication Date Title
US4695870A (en) Inverted chip carrier
US4716049A (en) Compressive pedestal for microminiature connections
US4902606A (en) Compressive pedestal for microminiature connections
US4924353A (en) Connector system for coupling to an integrated circuit chip
EP0559366B1 (en) Stackable three-dimensional multiple chip semiconductor device and method for making the same
US4724472A (en) Semiconductor device
US6982869B2 (en) Folded interposer
EP0531724B1 (en) Stepped electronic device package
CN100470793C (en) Semiconductor device and method of manufacturing semiconductor device
US5247423A (en) Stacking three dimensional leadless multi-chip module and method for making the same
US6268660B1 (en) Silicon packaging with through wafer interconnects
US6392429B1 (en) Temporary semiconductor package having dense array external contacts
US6208025B1 (en) Microelectronic component with rigid interposer
US6221769B1 (en) Method for integrated circuit power and electrical connections via through-wafer interconnects
EP0575051B1 (en) Stacked multi-chip modules and method of manufacturing
US5381039A (en) Hermetic semiconductor device having jumper leads
US5273940A (en) Multiple chip package with thinned semiconductor chips
JP2004282072A (en) Interposer, interposer package, and device assembly employing the same
US5532906A (en) Wiring substrate
EP0252115B1 (en) Compressive pedestal for microminiature connections
KR900004719B1 (en) Chip interface mesa
US12040282B2 (en) Electronic device including interposers bonded to each other
US6297542B1 (en) Connecting a die in an integrated circuit module
JPS617687A (en) Chip carrier package assembly and method of producing same

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19870819

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

17Q First examination report despatched

Effective date: 19900208

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19910211

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PATRAW, NILS, E.