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DE602006009277D1 - Testfähige integrierte schaltung und system in einer verpackung - Google Patents

Testfähige integrierte schaltung und system in einer verpackung

Info

Publication number
DE602006009277D1
DE602006009277D1 DE602006009277T DE602006009277T DE602006009277D1 DE 602006009277 D1 DE602006009277 D1 DE 602006009277D1 DE 602006009277 T DE602006009277 T DE 602006009277T DE 602006009277 T DE602006009277 T DE 602006009277T DE 602006009277 D1 DE602006009277 D1 DE 602006009277D1
Authority
DE
Germany
Prior art keywords
integrated circuit
reset signal
packaging
detector
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009277T
Other languages
English (en)
Inventor
Jong Fransciscus G M De
Alexander S Biewenga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602006009277D1 publication Critical patent/DE602006009277D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
DE602006009277T 2005-07-22 2006-07-20 Testfähige integrierte schaltung und system in einer verpackung Active DE602006009277D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05106761 2005-07-22
PCT/IB2006/052490 WO2007010493A2 (en) 2005-07-22 2006-07-20 Testable integrated circuit, system in package and test instruction set

Publications (1)

Publication Number Publication Date
DE602006009277D1 true DE602006009277D1 (de) 2009-10-29

Family

ID=37478886

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009277T Active DE602006009277D1 (de) 2005-07-22 2006-07-20 Testfähige integrierte schaltung und system in einer verpackung

Country Status (8)

Country Link
US (2) US7948243B2 (de)
EP (1) EP1910857B1 (de)
JP (1) JP2009503444A (de)
CN (1) CN101228451B (de)
AT (1) ATE443269T1 (de)
DE (1) DE602006009277D1 (de)
TW (1) TW200708750A (de)
WO (1) WO2007010493A2 (de)

Families Citing this family (29)

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US7945827B1 (en) * 2006-12-28 2011-05-17 Marvell International Technology Ltd. Method and device for scan chain management of dies reused in a multi-chip package
JP2008310792A (ja) * 2007-05-11 2008-12-25 Nec Electronics Corp テスト回路
US7908532B2 (en) 2008-02-16 2011-03-15 International Business Machines Corporation Automated system and processing for expedient diagnosis of broken shift registers latch chains
CN102165328A (zh) 2008-09-26 2011-08-24 Nxp股份有限公司 用于测试部分地组装的多管芯器件的方法、集成电路管芯和多管芯器件
US8332618B2 (en) * 2009-08-07 2012-12-11 Via Technologies, Inc. Out-of-order X86 microprocessor with fast shift-by-zero handling
IT1402921B1 (it) 2010-12-10 2013-09-27 St Microelectronics Srl Circuito di pilotaggio di una porta d'accesso al test
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
US8756467B2 (en) 2011-11-30 2014-06-17 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
CN103391093B (zh) 2012-05-09 2018-10-19 恩智浦美国有限公司 可重构集成电路
TWI477961B (zh) * 2012-06-26 2015-03-21 Silicon Touch Tech Inc 應用於序列傳輸系統之晶片及相關的故障處理方法
US9304164B2 (en) 2012-08-24 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for RFID tag testing
US9726722B1 (en) * 2013-05-24 2017-08-08 Marvell Israel (M.I.S.L.) Ltd Systems and methods for automatic test pattern generation for integrated circuit technologies
US9455027B1 (en) * 2014-08-08 2016-09-27 Cypress Semiconductor Corporation Power management system for high traffic integrated circuit
US9374094B1 (en) * 2014-08-27 2016-06-21 Altera Corporation 3D field programmable gate array system with reset manufacture and method of manufacture thereof
CN105629180A (zh) * 2014-11-11 2016-06-01 中兴通讯股份有限公司 测试方法、装置及控制器
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan
US10429441B2 (en) * 2017-05-24 2019-10-01 Qualcomm Incorporated Efficient test architecture for multi-die chips
US10495690B2 (en) * 2017-08-28 2019-12-03 Stmicroelectronics International N.V. Combinatorial serial and parallel test access port selection in a JTAG interface
CN109406902B (zh) * 2018-11-28 2021-03-19 中科曙光信息产业成都有限公司 逻辑扫描老化测试系统
CN109557459A (zh) * 2018-12-20 2019-04-02 北京时代民芯科技有限公司 一种基于JTAG测试的SiP系统及其内部芯片的JTAG测试方法
CN109655736A (zh) * 2018-12-21 2019-04-19 中国航空工业集团公司洛阳电光设备研究所 一种芯片焊接故障快速精确定位的方法
CN113906512A (zh) * 2019-05-31 2022-01-07 美光科技公司 耦合到单片系统的存储器装置架构
CN111176563B (zh) * 2019-12-24 2023-10-31 湖南国科微电子股份有限公司 旁路访问存储数据的方法、存储设备及旁路访问存储系统
CN112526328B (zh) * 2020-10-28 2022-11-01 深圳市紫光同创电子有限公司 边界扫描测试方法
CN112098818B (zh) * 2020-11-02 2021-02-02 创意电子(南京)有限公司 一种基于标准边界扫描电路的sip器件测试系统
TWI756970B (zh) * 2020-11-23 2022-03-01 立積電子股份有限公司 電位狀態判別裝置
TWI783555B (zh) * 2021-06-28 2022-11-11 瑞昱半導體股份有限公司 半導體裝置與測試脈衝訊號產生方法
CN114236353A (zh) * 2021-12-13 2022-03-25 山东航天电子技术研究所 一种SiP微系统封装现场快速测试系统及测试方法
CN119311581A (zh) * 2024-09-24 2025-01-14 苏州异格技术有限公司 Fpga测试用例逻辑资源扩充方法、装置、设备、介质及产品

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1536147A (en) 1975-07-02 1978-12-20 Int Computers Ltd Data processing systems
US4860290A (en) 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules
TW253031B (de) 1993-12-27 1995-08-01 At & T Corp
US5677913A (en) * 1996-07-01 1997-10-14 Sun Microsystems, Inc. Method and apparatus for efficient self testing of on-chip memory
US6804725B1 (en) 1996-08-30 2004-10-12 Texas Instruments Incorporated IC with state machine controlled linking module
JP4020462B2 (ja) * 1996-08-30 2007-12-12 テキサス インスツルメンツ インコーポレイテツド テストインタフェースを含む集積回路及びテストインタフェースを使用する方法
JP2001166002A (ja) 1999-12-07 2001-06-22 Matsushita Electric Ind Co Ltd バウンダリスキャン回路
KR100896538B1 (ko) 2001-09-20 2009-05-07 엔엑스피 비 브이 전자 장치
US7346821B2 (en) 2003-08-28 2008-03-18 Texas Instrument Incorporated IC with JTAG port, linking module, and off-chip TAP interface
TWI323467B (en) * 2005-12-27 2010-04-11 Hynix Semiconductor Inc On-die termination circuit for semiconductor memory apparatus

Also Published As

Publication number Publication date
EP1910857B1 (de) 2009-09-16
US7948243B2 (en) 2011-05-24
CN101228451A (zh) 2008-07-23
WO2007010493A2 (en) 2007-01-25
US20110267093A1 (en) 2011-11-03
EP1910857A2 (de) 2008-04-16
US8653847B2 (en) 2014-02-18
ATE443269T1 (de) 2009-10-15
WO2007010493A3 (en) 2007-06-07
US20090309609A1 (en) 2009-12-17
CN101228451B (zh) 2011-07-27
TW200708750A (en) 2007-03-01
JP2009503444A (ja) 2009-01-29

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Legal Events

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8364 No opposition during term of opposition