DE3448379C2 - Gate shutdown thyristor - Google Patents
Gate shutdown thyristorInfo
- Publication number
- DE3448379C2 DE3448379C2 DE19843448379 DE3448379A DE3448379C2 DE 3448379 C2 DE3448379 C2 DE 3448379C2 DE 19843448379 DE19843448379 DE 19843448379 DE 3448379 A DE3448379 A DE 3448379A DE 3448379 C2 DE3448379 C2 DE 3448379C2
- Authority
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- Germany
- Prior art keywords
- layer
- gate
- base layer
- thyristor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/233—Cathode or anode electrodes for thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
Die Erfindung bezieht sich auf einen Gate-Abschaltthyristor nach dem Oberbegriff des Patentanspruches 1 oder des Patentanspruches 2.The invention relates to a gate turn-off thyristor the preamble of claim 1 or claim 2nd
Ein derartiger Gate-Abschaltthyristor ist aus der DE-OS 27 12 533, Fig. 9 bekannt. Bei diesem Gate-Abschaltthyristor sind die Bereiche der kammartig ausgebildeten zweiten Emitter schicht mit einer die Kathoden-Elektrode bildenden Aluminium schicht bedeckt. Bei den feinen Kathodenstrukturen, die für einen hohen steuerbaren Anodenstrom nötig sind, ist es dann schwierig, die Zuleitungsdrähte auf den Elektroden zu befe stigen, und in der DE-OS 27 12 533 ist darüber auch nichts ausgeführt.Such a gate shutdown thyristor is known from DE-OS 27 12 533, Fig. 9. In this gate turn-off thyristor, the areas of the comb-like second emitter layer are covered with an aluminum layer forming the cathode electrode. With the fine cathode structures, which are necessary for a high controllable anode current, it is then difficult to fix the lead wires on the electrodes, and in DE-OS 27 12 533 nothing is said about it.
Aus der US-PS 3 633 076 ist ein Verfahren zum Anbringen eines Anschlußdrahtes an einen Halbleiter bekannt, bei dem ein Strei fen aus drei Schichten zwischen dem Halbleiter und dem Draht verwendet wird. Auf der dem Halbleiter zugewandten Seite ist wahlweise eine Schicht aus Mo, W, V oder Cr vorgesehen, welche den ohmschen Kontakt zum Halbleiter herstellt, dann folgt eine Schicht aus Ni, Fe, Co, Mn oder ggf. Cr und schließlich eine Au- Schicht. Eine Aluminium-Elektrode ist nicht vorgesehen.From US-PS 3 633 076 is a method for attaching a Lead wire to a semiconductor known in which a streak three layers between the semiconductor and the wire is used. On the side facing the semiconductor optionally a layer of Mo, W, V or Cr is provided, which makes the ohmic contact to the semiconductor, then one follows Layer of Ni, Fe, Co, Mn or possibly Cr and finally an Au Layer. An aluminum electrode is not provided.
Aus der DE 28 09 863 A1 ist ein Halbleiterbauelement bekannt, bei dem die Zuleitungen für Ströme über 2 A ausgelegt sind. Dazu befindet sich auf der zu kontaktierenden Halbleiterzone eine Aluminiumschicht als Elektrode. Darauf ist, um das Anlöten eines Anschlußdrahtes zu ermöglichen, ein dreilagiger Kontaktbereich ausgebildet mit einer Cr- oder Ti-Schicht als erste Lage, einer Ni-Schicht als zweite Lage und einer Au- oder Pd-Schicht als dritte Lage. Insbesondere die Chrom- oder Titanschicht erschwert wegen ihrer Zusammensetzung die Anpassung der Elektrode an das Halbleiterbauelement.A semiconductor component is known from DE 28 09 863 A1, in which the supply lines are designed for currents above 2 A. To is located on the semiconductor zone to be contacted Aluminum layer as an electrode. On it is to solder a Connection wire to allow a three-layer contact area formed with a Cr or Ti layer as the first layer, one Ni layer as a second layer and an Au or Pd layer as third layer. In particular, the chrome or titanium layer is difficult because of their composition, the adaptation of the electrode to the Semiconductor device.
Ein weiterer GTO-Thyristor ist aus der DE 32 00 807 A1 bekannt und wird nun mit Bezug auf die Fig. 1 bis 3 beschrieben.Another GTO thyristor is known from DE 32 00 807 A1 and will now be described with reference to FIGS. 1 to 3.
Fig. 1 ist eine Aufsicht auf ein Gate-Abschaltthyristorchip 100. Eine Glaspassivierung 109 ist am Rande des Chips 100 vorgesehen. Eine metallische Gate-Elektrode 106 ist innerhalb der Glaspas sivierung 109, und eine metallische Kathodenelektrode 107 ist weiter innerhalb vorgesehen, wobei diese in die Elektrode 106 in Form der Zähne eines Kammes paßt. Diese Elektroden sind gegen einander durch einen schützenden Oxidfilm 108 isoliert. Fig. 1 is a plan view of a gate Abschaltthyristorchip 100th A glass passivation 109 is provided on the edge of the chip 100 . A metallic gate electrode 106 is inside the glass passivation 109 , and a metallic cathode electrode 107 is further provided inside, which fits into the electrode 106 in the form of teeth of a comb. These electrodes are insulated from one another by a protective oxide film 108 .
Fig. 2 ist eine Schnittansicht, die entlang der Linie 2-2 in dem in Fig. 1 gezeigten Chip 100 aufgenommen wurde. Eine zweite Basisschicht 103 vom p-Typ und eine erste Emitterschicht 102 vom p-Typ werden auf und unter einer ersten Basisschicht 101 vom n- Typ eines Siliziumeinkristallsubstrats vom n-Typ gebildet. Als Verunreinigung vom p-Typ wird Gallium, Bor oder ähnliches diffundiert. Eine zweite Emitterschicht 104 vom n-Typ, die Verunreinigungen vom n-Typ, wie Phosphor, enthält, wird durch Diffusion in Teilbereichen auf der oberen Oberfläche der zweiten Basisschicht 103 vom p-Typ gebildet. Auf den Oberflächen der ersten Emitterschicht 102, der zweiten Basisschicht 103 und der zweiten Emitterschicht 104 werden in Ohm′schem Kontakt eine metallische Anodenelektrode 105, die metallische Gate-Elektrode 106 und die metallische Kathodenelektrode 107 gebildet. FIG. 2 is a sectional view taken along line 2-2 in chip 100 shown in FIG. 1. A second p-type base layer 103 and a first p-type emitter layer 102 are formed on and under a first n-type base layer 101 of an n-type silicon single crystal substrate. Gallium, boron or the like is diffused as a p-type impurity. A second n-type emitter layer 104 containing n-type impurities such as phosphorus is formed by diffusion in portions on the upper surface of the second p-type base layer 103 . On the surfaces of the first emitter layer 102 , the second base layer 103 and the second emitter layer 104 , a metallic anode electrode 105 , the metallic gate electrode 106 and the metallic cathode electrode 107 are formed in ohmic contact.
Fig. 3 ist eine Schnittansicht des Aufbaus, die entlang der Linie 3-3 des Chips 100 in Fig. 1 aufgenommen wurde. Im allge meinen hat die Metallschicht der metallischen Anodenelektrode 105 einen mehrfach metallischen Aufbau aus Al-Mo-Ni-Au, Al-Zn- Ni-Au oder Cr-Ni-Au, so daß der Chip 100 auf einem Kühlblech oder ähnlichem durch Löten befestigt werden kann. Für die Gate- Elektrode 106 und die Kathodenelektrode 107 wird Al verwendet, da Al zur Bildung der Feinstruktur, die notwendig ist, um die gewünschten Funktionen des Gate-Abschaltthyristors zu erhalten, geeignet ist. Zum Anschluß der Kathoden- und Gate-Elektroden 107, 106 wird im allgemeinen eine Methode angewandt, bei der, wie in Fig. 6A in vergrößerter Weise gezeigt, ein dünner, nach außen führender Al-Draht 300 mit einem Durchmesser von ungefähr 300 bis 400 µm auf der Al-metallischen Oberfläche durch Ultra schall-Schweißen befestigt wird. Dabei ist es zum Schalten grö ßerer Ströme, und wenn dünne Al-Drähte verwendet werden, not wendig, eine Mehrzahl von Drähten parallel durch Ultraschall- Schweißen anzuordnen, was eine uneffiziente Zusammenbauarbeit zur Folge hat. FIG. 3 is a sectional view of the structure taken along line 3-3 of chip 100 in FIG. 1. In general, the metal layer of the metallic anode electrode 105 has a multi-metallic structure made of Al-Mo-Ni-Au, Al-Zn-Ni-Au or Cr-Ni-Au, so that the chip 100 is attached to a heat sink or the like by soldering can be. Al is used for the gate electrode 106 and the cathode electrode 107 , since Al is suitable for forming the fine structure which is necessary in order to obtain the desired functions of the gate switch-off thyristor. A method is generally used for connecting the cathode and gate electrodes 107 , 106 , in which, as shown in an enlarged manner in FIG. 6A, a thin, outwardly leading Al wire 300 with a diameter of approximately 300 to 400 is used µm is attached to the Al-metallic surface by ultrasonic welding. Here, for switching larger currents, and when thin Al wires are used, it is necessary to arrange a plurality of wires in parallel by ultrasonic welding, which results in inefficient assembly work.
Um die oben beschriebenen Nachteile eines herkömmlichen Gate- Abschaltthyristors zu vermeiden, ist es Aufgabe der Erfindung, einen Gate-Abschaltthyristor vorzusehen, bei dem die Verbin dungsdrähte zur metallischen Kathode und/oder Gate-Elektrode mit hoher Zuverlässigkeit und hoher Effizienz des Zusammenbaus, ohne die Leistungsfähigkeit des Gate-Abschaltthyristors zu ver schlechtern, angebracht werden können.To overcome the disadvantages of a conventional gate To avoid turn-off thyristor, it is the object of the invention to provide a gate turn-off thyristor in which the connector wire with the metallic cathode and / or gate electrode high reliability and high efficiency of assembly without ver the performance of the gate shutdown thyristor worse, can be attached.
Diese Aufgabe wird gelöst durch einen Gate-Abschaltthyristor, der durch die Merkmale des Patentanspruchs 1 oder 2 gekenn zeichnet ist.This problem is solved by a gate switch-off thyristor, who are characterized by the features of claim 1 or 2 is drawing.
Weitere Eigenschaften des Gate-Abschaltthyristors ergeben sich aus der Beschreibung eines Ausführungsbeispiels anhand der Fi guren. Von den Figuren zeigen:Further properties of the gate turn-off thyristor result from the description of an embodiment using the Fi guren. From the figures show:
Fig. 1 eine Aufsicht auf ein herkömmliches Gate-Abschalt thyristorchip; Figure 1 is a plan view of a conventional gate shutdown thyristor chip.
Fig. 2 eine Schnittansicht des Aufbaus, die entlang der Linie 2-2 des in den Fig. 1 und 4 gezeigten Chips aufgenommen ist; Fig. 2 is a sectional view of the structure taken along line 2-2 of the chip shown in Figs. 1 and 4;
Fig. 3 eine Schnittansicht des Aufbaus, die entlang der Linie 3-3 des in Fig. 1 gezeigten Chips aufgenommen ist; Fig. 3 is a sectional view of the structure taken along line 3-3 of the chip shown in Fig. 1;
Fig. 4 eine Aufsicht auf das Gate-Abschaltthyristorchip einer Ausführungsform der Erfindung; Fig. 4 is a plan view of the gate Abschaltthyristorchip an embodiment of the invention;
Fig. 5 eine Schnittansicht des Aufbaus, die entlang der Linie 5-5 des in Fig. 4 gezeigten Chips aufgenommen ist; Fig. 5 is a sectional view of the structure taken along line 5-5 of the chip shown in Fig. 4;
Fig. 6A ein herkömmliches Verfahren zum Anschluß eines Verbindungsdrahtes an eine metallische Kathodenelek trode oder eine metallische Gate-Elektrode; und Fig. 6A shows a conventional method for connecting a connecting wire to a metallic cathode electrode or a metallic gate electrode; and
Fig. 6B ein erfindungsgemäßes Verfahren. Fig. 6B, a method of the invention.
In den Zeichnungen kennzeichnen identische Bezugszeichen iden tische oder entsprechende Teile.In the drawings, identical reference symbols denote iden tables or corresponding parts.
Der Querschnitt des in Fig. 4 gezeigten Chips entlang der Linie 2-2 ist der gleiche wie der von Fig. 2, während die Fig. 5 den Querschnitt entlang der Linie 5-5 zeigt. Der Aufbau des Haupt teils des Gate-Abschaltthyristors mit den Merkmalen der Erfin dung ist derselbe wie der des herkömmlichen Gate-Abschaltthyri stors nach den Fig. 1 bis 3, und daher wird eine detaillierte Beschreibung darüber weggelassen. Der Gate-Abschaltthyristor nach Fig. 4 unterscheidet sich im Aufbau, verglichen mit dem Gate-Abschaltthyristor nach Fig. 1, dadurch, daß Kontaktbereiche 107a, 106a als lötbare Metallschicht zum Anschluß von Verbin dungsdrähten gebildet sind. Als lötbare Metallschicht der Kon taktbereiche 107a und 106a wird ein mehrfacher Metallaufbau aus Al-Mo-Ni-Au oder Al-Zn-Ni-Au angewendet.The cross section of the chip shown in FIG. 4 along line 2-2 is the same as that of FIG. 2, while FIG. 5 shows the cross section along line 5-5. The structure of the main part of the gate turn-off thyristor having the features of the inven tion is the same as that of the conventional gate turn-off thyristor shown in FIGS . 1 to 3, and therefore a detailed description thereof is omitted. The gate turn-off thyristor according to FIG. 4 is different in structure compared to the gate turn-off thyristor according to Fig. 1, characterized in that contact regions 107 a, 106 a solderable metal layer are formed as extension wires for connecting Verbin. A multiple metal structure made of Al-Mo-Ni-Au or Al-Zn-Ni-Au is used as the solderable metal layer of the contact areas 107 a and 106 a.
Als Verfahren zur Bildung des mehrfachen Metallaufbaus der Kon taktbereiche wird ein Aufdampfverfahren oder ein kombiniertes Verfahren aus Aufdampfen, Überziehen u.ä. angewendet. Dabei wird ein Verfahren angewendet, bei dem gleichzeitig mit der Bildung der Al-Metallschicht, die die Kontaktbereiche 107a und 106a ausschließt, die Al-Metallschicht unter den Kontaktbereichen 107a und 106a durch einen Aufdampfprozeß gebildet wird, und dann wird der geschichtete Metallaufbau der Kontaktbereiche 107a und 106a gebildet. Alternativ kann auch ein Verfahren angewandt werden, bei dem die Kontaktbereiche 107a und 106a durch einen von dem Prozeß der Bildung der Al-Metallschicht 107 und 106 ab weichenden Prozeß gebildet werden.An evaporation method or a combined method of evaporation, coating and the like is used as the method for forming the multiple metal structure of the contact areas. applied. Here, a method is used in which, simultaneously with the formation of the Al metal layer, which excludes the contact regions 107 a and 106 a, the Al metal layer is formed under the contact regions 107 a and 106 a by a vapor deposition process, and then the layered Metal structure of the contact areas 107 a and 106 a formed. Alternatively, a method can also be used in which the contact regions 107 a and 106 a are formed by a process which differs from the process of forming the Al metal layer 107 and 106 .
Ein Beispiel zur Verbindung der Anschlußdrähte mit den Kontakt bereichen 107a und 106a ist in Fig. 6B gezeigt. Ein lötbarer nickelüberzogener Verbindungsdraht 400, der aus relativ dünnem Kupferblech o. ä. hergestellt ist, ist mit einem Lötmaterial 200 auf den Kontaktbereich 107a oder den Kontaktbereich 106a, die zum Anschluß der Verbindungsdrähte gebildet sind, gelötet.An example of the connection of the leads with the contact areas 107 a and 106 a is shown in Fig. 6B. A solderable nickel-plated connecting wire 400 , which is made of relatively thin copper sheet or the like, is soldered with a solder material 200 to the contact area 107 a or the contact area 106 a, which are formed for connecting the connecting wires.
Die Erfindung kann auch auf ein Halbleiterelement, wie einen Leistungstransistor, der eine feinstrukturierte Metallelektrode besitzt, angewendet werden.The invention can also be applied to a semiconductor element such as a Power transistor, which is a finely structured metal electrode owns, applied.
Claims (2)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58228043A JPS60119777A (en) | 1983-11-30 | 1983-11-30 | Gate turn-off thyristor |
Publications (1)
Publication Number | Publication Date |
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DE3448379C2 true DE3448379C2 (en) | 1993-12-16 |
Family
ID=16870300
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19843448379 Expired - Fee Related DE3448379C2 (en) | 1983-11-30 | 1984-11-30 | Gate shutdown thyristor |
DE19843443784 Granted DE3443784A1 (en) | 1983-11-30 | 1984-11-30 | GATE SHUT-OFF THYRISTOR |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19843443784 Granted DE3443784A1 (en) | 1983-11-30 | 1984-11-30 | GATE SHUT-OFF THYRISTOR |
Country Status (3)
Country | Link |
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JP (1) | JPS60119777A (en) |
DE (2) | DE3448379C2 (en) |
GB (1) | GB2150754B (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4073876B2 (en) * | 2004-01-14 | 2008-04-09 | 三菱電機株式会社 | Semiconductor device |
JP5396436B2 (en) | 2011-06-29 | 2014-01-22 | 日立オートモティブシステムズ株式会社 | Semiconductor device and method for manufacturing semiconductor device |
US9583425B2 (en) * | 2012-02-15 | 2017-02-28 | Maxim Integrated Products, Inc. | Solder fatigue arrest for wafer level package |
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DE1214978B (en) * | 1963-06-11 | 1966-04-21 | Licentia Gmbh | Process for soldering a gold foil to a nickel-plated molybdenum disk |
GB1149606A (en) * | 1967-02-27 | 1969-04-23 | Motorola Inc | Mounting for a semiconductor wafer which is resistant to fatigue caused by thermal stresses |
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GB2104290A (en) * | 1981-08-18 | 1983-03-02 | Tokyo Shibaura Electric Co | Semiconductor device and method for manufacturing the same |
DE3346833A1 (en) * | 1982-12-28 | 1984-07-05 | Tokyo Shibaura Denki K.K., Kawasaki | SEMICONDUCTOR ELEMENT |
EP0121605A2 (en) * | 1983-01-20 | 1984-10-17 | BROWN, BOVERI & CIE Aktiengesellschaft | Method of producing a multi-layer contact metallisation on a silicon semiconductor component |
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GB2095904B (en) * | 1981-03-23 | 1985-11-27 | Gen Electric | Semiconductor device with built-up low resistance contact and laterally conducting second contact |
-
1983
- 1983-11-30 JP JP58228043A patent/JPS60119777A/en active Pending
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1984
- 1984-11-30 GB GB8430310A patent/GB2150754B/en not_active Expired
- 1984-11-30 DE DE19843448379 patent/DE3448379C2/en not_active Expired - Fee Related
- 1984-11-30 DE DE19843443784 patent/DE3443784A1/en active Granted
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DE1105526B (en) * | 1959-12-29 | 1961-04-27 | Siemens Ag | Method for manufacturing a semiconductor device |
DE1214978B (en) * | 1963-06-11 | 1966-04-21 | Licentia Gmbh | Process for soldering a gold foil to a nickel-plated molybdenum disk |
US3633076A (en) * | 1966-03-19 | 1972-01-04 | Siemens Ag | Three layer metallic contact strip at a semiconductor structural component |
GB1149606A (en) * | 1967-02-27 | 1969-04-23 | Motorola Inc | Mounting for a semiconductor wafer which is resistant to fatigue caused by thermal stresses |
GB1557399A (en) * | 1976-04-09 | 1979-12-12 | Int Rectifier Corp | Gate controlled semiconductor device |
DE2809863A1 (en) * | 1977-03-08 | 1978-09-14 | Ates Componenti Elettron | METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENTS |
DE2712533A1 (en) * | 1977-03-15 | 1978-12-14 | Meidensha Electric Mfg Co Ltd | SEMICONDUCTOR COMPONENT CONTROLLED BY A CONTROL ELECTRODE, IN PARTICULAR THYRISTOR |
DE3200807A1 (en) * | 1981-01-14 | 1982-10-14 | Hitachi, Ltd., Tokyo | PERFORMANCE SEMICONDUCTOR ARRANGEMENT |
GB2104290A (en) * | 1981-08-18 | 1983-03-02 | Tokyo Shibaura Electric Co | Semiconductor device and method for manufacturing the same |
DE3346833A1 (en) * | 1982-12-28 | 1984-07-05 | Tokyo Shibaura Denki K.K., Kawasaki | SEMICONDUCTOR ELEMENT |
EP0121605A2 (en) * | 1983-01-20 | 1984-10-17 | BROWN, BOVERI & CIE Aktiengesellschaft | Method of producing a multi-layer contact metallisation on a silicon semiconductor component |
Also Published As
Publication number | Publication date |
---|---|
GB8430310D0 (en) | 1985-01-09 |
DE3443784A1 (en) | 1985-07-18 |
GB2150754B (en) | 1987-08-26 |
JPS60119777A (en) | 1985-06-27 |
DE3443784C2 (en) | 1991-10-10 |
GB2150754A (en) | 1985-07-03 |
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