DE3320533A1 - METHOD AND ELECTRONIC CIRCUIT ARRANGEMENT FOR TRANSMITTING DATA IN SERIAL FORM - Google Patents

Description

Method and electronic circuit arrangement for Transmission of data in serial form

The invention relates to a method of transmission a message of η data in serial form between two electronic cards according to the generic term of claim 1 and an electronic circuit arrangement for performing this method .

The term "card" used in the present description and in the claims is in one to understand very general and broad sense and should include electronic assemblies of various forms, which have electronic components arranged at a certain distance from one another, that can be related to each other.

A known method for transmitting a message of η data is, for example, in the publication PCE 2110 from February 1982 from RTC (La Radio Technique-Compelec). It only educates one of the two cards acts as a data transmitter and the other card acts exclusively as a data receiver. That is disadvantageous because; any dialogue between the two Cards is impossible and likewise the feedback of information from the second to the first card. Furthermore, no special measures are planned to to increase the security of the transmission of a message from one card to the other.

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The invention is based on the object of the method specified in the preamble of claim 1 to improve and generalize in such a way that messages between the two cards in both directions can be exchanged.

According to the invention, this task is performed by dl © xrn Characteristics of claim 1 specified features solved.

An electronic circuit arrangement by performing the method is according to the invention by the Characterized in claim 2 specified features.

In this way it becomes a simple procedure or created a simply structured electronic circuit arrangement which allows simultaneous transmission of messages with η data between two electronic cards and thus a dialogue between these two cards or information feedback from the data receiver card to the data transmitter card permitted. At the same time, the method and the electronic circuit arrangement according to the Invention ensures a high level of security for the transmission of these messages between the two cards, whereby the security can be further increased by the fact that a repeated transmission of the same messages is carried out. Furthermore, a parallel operation of the two is at the same time on the two 'electronic Cards in each case provided control units to carry out other tasks possible, so that the Circuit arrangement according to the invention can be optimally exploited.

Expedient embodiments of the invention result from the dependent claims.

The invention is based on the drawings of an exemplary embodiment explained in more detail. Show it:

Figure 1 is a circuit diagram of the electronic circuit arrangement with the two electronic cards,

FIG. 2 shows a flow diagram of the transmission program the clock card,

FIG. 3 shows a flow diagram of the transmission program the clock receiver card and

Figure 4 shows the timing of the clock pulses, the Synchronization signals and the one on the data line generated data chart.

The electronic circuit arrangement according to the invention is shown in Figures 1 to 4 and allows the transmission of messages with η data in serial form between two electronic cards 1 and 2, which are connected to one another by a clock pulse line 3, a data line 5 and a synchronization line k .

The card 2 represents the clock generator and has a circuit for generating clock pulses, which are given to the clock pulse line J and transmitted to the other card 1, which has a circuit for tmplany the only clock pulses. The circuit for the lactic impulses consists of a pulse

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shaping circuit 20 whose input is connected to βχην AC power source of low voltage and its output on the one hand to the input A of an inte grated circuit 2 1 and the other with DWR Lin gangs- outputs - terminal AO of a micropro it ^ sur s> 22 is connected. The integrated circuit 21 (for example with the designation MC 1405U BCP from MOTOROLA) serves to isolate the microprocessor 22 from the external environment of the card 2. The clock pulse line 3 is connected to the output G corresponding to the input A. The integrated circuit 21 also has an input B connected to an input-output terminal A1 of the microprocessor 22 and a corresponding output H to which the synchronization line 4 is connected.

The microprocessor 22 (for example with the designation M 6805 P2 from MOTOROLA) also has a two-way input-output terminal A2 to which the data line 5 connected via a current limiting device formed, for example, by a resistor 23 is. Between the terminal A2 and the negative pole of the supply voltage source is a capacitor 24, the together with the resistor 23 forms a filter which serves to suppress interference that could be generated on the data line 5 by the external environment.

The microprocessor 22 forms the control unit of the card 2 and only comes into operation at that moment which the clock pulse decreases (Figure 4). It has a © central unit 25, which executes the commands which constitute the program stored in a program memory ROM 26. To save the data

is also a working memory in the microprocessor 22 RAM 27 is provided. These data are both data generated by the card 2 or are received, as well as to be transmitted temporary user data, such as that of the clock counter or Time counter Cpt 2.

This microprocessor 22, the suitable transmission program contains, is set up to generate the desired data and at the moment at which the clock pulse decreases, a sequence of η data, in the example under consideration 24 data, which on the other card 1 are to be read on the data line 5. The microprocessor 22 has also a reading circuit which is set up to read the data generated by the other card 1 read, just before the data transmitter circuit of the card 2 on the same data line 5 a signal level generated, which represents the data signal to be transmitted to the card 1. Furthermore, the Microprocessor 22 means for calculating the parity of the η generated by the card 2 data for generating parity information on the data line 5 and means for parity control to read the parity information sent by the card 1 and that of to release this received η data if necessary or to be assessed as valid. Finally, the microprocessor 22 has a circuit for generating a Synchronization signal.

The program to be transferred, which is in the program memory ROM 26 is stored, includes according to Figure 2 a set command 49 to the input-output terminal A2 for setting to input, a delay module

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50, a conditional branch instruction 51 for value? Λ of the clock counter CPt2, a conditional branch instruction 52 to the value 0 of the clock counter CpTl, conditional Verzweig u ng s be missing 53 in case dast> the read parity and the calculated parity are equal , a module 54 for reading the data and for calculating the parity of this data, an initialization command 55 for the clock counter Cpt2 for setting to the value 25, a command 56 for activating the synchronization line, a module 57 for generating the parity, a command 58 for Disconnection of the synchronization line, a module 59 for reading the parity, a module 60 for releasing the message, a module 61 for generating the data and for calculating the parity and a command 62 for switching the clock counter Cpt2 down.

The card 1 is. the clock pulse receiver and has Means for receiving the circuit through the pulse shaper 20 generated clock pulses. These funds remain in the essentially from an interface circuit JO, on whose Input terminal 31 the clock pulse line 3 is connected and its output terminal 32 with the input GO a microprocessor 40 is connected. The interface circuit 30 has, for example, a transistor 33, the base of which is connected to the input terminal 31 via a Resistor 34 is connected, the collector of which is connected on the one hand to the output terminal 32 and on the other hand via a resistor 35 is connected to the positive pole of the supply voltage and its emitter to the negative pole of the supply voltage is connected. This interface circuit JO serves to control the microprocessor 40 to isolate from the external environment of the card 1.

An interface circuit 30 ', which is constructed in the same way like the interface circuit 30 and which the same How this plays a role has an input terminal 36 to which the synchronization line 4 is connected and an output terminal 37 which is connected to an input terminal G1 of the microprocessor AO. This microprocessor 40 (for example with the designation COP 444 L from NSC) also has one Bidirectional input-output terminal G2 to which the data line 5 is connected, for example, by a Resistor 23 'formed current limiting device is connected. The resistors 23 'and 23 allow it means that data generated by the two cards 1 and 2 are simultaneously sent to the bidirectional input-output terminals G2 and A2 of the two microprocessors 40 and 22 exist. This simultaneous presence is moving, as in FIG. 4 illustrates the overlap of the logical states which these data, which in the Example according to Figure 4 with D1 and D1 'are designated, and the same time at the terminals 62 and A2 are present. In the absence of a current limiting device would increase accordingly during this overlap, only by the Set the inherent resistance of the data line 5 limited current, which could damage the circuits.

Aul of the card 1 is between the terminal G2 and the negative Pul of the supply voltage inserted a capacitor 24 ", which together with the resistor 23 '- as in the F-all of the card 2 - a filter to suppress Forms disturbances which could be generated on the data line 5 by the external environment.

The microprocessor 4 rj provides the control unit of the Map 1 and is intended to be used only in iJ «» m those Auyuiibiiuk wii kttttm ^ u werduii, «in wuli, Iimiii di-u I λ k I .ιιιψΜ 1: < increases (Figure 4). He assigns nine central unit 45 Execution of the commands, which are in the program memory ROM 46 show stored programs. In addition, the microprocessor 40 has a working memory RAM 47 for storing the data, whether it is data that is forced by the card 1 or are received, as well as to be transmitted temporary user data, such as that of the clock counter Cpt1. This microprocessor 40, which contains the program to be transmitted, consists of a reading circuit for Reading the data generated by card 2 at the moment at which the clock pulse rises, and from means for data generation, which are used in turn on the following point in time to generate a signal level on the same data line 5, which corresponds to that of card 2 Represents transmitting data signal. Deswaitereri has Microprocessor 40 a circuit for Berachtiung the Parity of the η Datyn generated by card 1, im considered Example 24 Data to be sent on the data line 5 to generate parity information, as well as means for parity control, which serve on the one hand to read the parity information sent from the card 2 at the time at which the synchronization line 4 becomes active, and on the other hand, if necessary, the η received from this card To release data or to evaluate it as valid.

The transmission program, which is stored in the program memory ROM 46, includes, according to FIG. 3, a set command 49 'to the input-output terminal GZ for setting to input, a delay module 50',

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a conditional branch instruction 63 to the active state the synchronization line 4, a conditional branch instruction 52 "to the value 0 of the clock counter Cpt1, a conditional branch instruction 53 'in the event that the parity read and the parity calculated are equal Parity, a command 62 'for switching down the clock counter Cpt1, a module 54' for reading the data and for calculating the parity of the data already received, a module 61 "for generating the data and for Calculating the parity, a module 59 'for reading the parity, a module 60' for releasing the message, an initialization command 55 ″ for the cycle counter Cpt1 to set the value 25 and a module 57 'to generate the parity.

During operation of cards 1 and 2, clock pulses with the frequency of the supply network, in the example according to FIG. 1 with 50 Hz, generated on the clock pulse line 3. Each of the cards reads those of in turn the other card. In the example according to FIG. 4, the card 2 generates the data signals GD1 bis 6024, each of which is read from card 1, where the read data signals are indicated by LD1 to LD24; at the following time the card is generated 1 the data signals GD1 'to GD24' on the data line 5 in the direction of the other card 2, where these data signals LDI 'to LD24' are read. Whenever the clock pulse rises (Figure 4), the following commands are successively from the microprocessor 40 on the Card 1 executed (FIG. 3): The set command 49 '(designated PE in FIG. 4) to the input-output terminal ü2, whereby this is set to input, the delay module 50 ', the command 62' for AbwUr tasi, holding the clock counter Cpt1 and the conditional

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Branch command 63 to the active state of the synchronization line 4, the function cIps delay module 50 'is to allow the filter circuit 23'-24 "to reach the state or the signal level that corresponds to the data signal transmitted by the card 2 before reading this Data signal through the card 1, that is to say to compensate for the delay introduced by the filter circuit mentioned. This delay corresponds to the zone 50 'between PE and LD1, shown hatched in FIG.

As long as the transmitted message from the 24 data has not ended, the synchronization line 4 not activated, and the microprocessor 40 successively allows the module 54 'and then the module 61 "to operate will; the module 54 'has the function of the data signal generated by the clock card 2 (for example LD1) and calculate the parity of the data already received from this card 2 during the Module 61 'the generation of the data signal (GDI') to be transmitted to the clock generator card 2 and the calculation the parity of the data already generated by the card 1.

At this point in time, the microprocessor 40 has finished executing the transmission program and can up to for the arrival of the following rising clock pulse, which is the continuation of the execution of the transmission program determines to execute other programs, such as instructions, if necessary for displaying data or processing keyboard commands , etc.

At the point in time at which the same clock pulse decreases (Figure 4), the following commands are issued by the microprocessor 22 executed successively on the clock generator card 2 (FIG. 2): The set command 49 (PE) to the input-output - Terminal A2 for setting to input, the delay module 50 and the conditional branch command 51 to the value 24 of the cycle counter Cpt2. The delay module 50 allows the filter circuit to do so 23-24 to reach the logical state which the data signal transmitted by the card 1 prior to reading this data signal through the card 2 corresponds. This delay is shown in Figure 4 by the hatched zone 50 between PE and LD1 'illustrated.

As long as the twenty-fourth data signal has not been received and therefore the clock counter Cpt2 does not receive the value 24 has reached, the microprocessor 22 successively leaves the module 54 to read the by the clock pulse reception s card 1 generated data signal (for example LD1 ') and for calculating the parity of the of this card 1 and then the conditional branch instruction 52 to the value Q of the clock counter Cpt2 be effective.

As long as the cycle counter Cpt2 has not assumed the value 0, that is, as long as not the twenty-fourth and The last data signal has been read, the microprocessor 22 allows the module 61 to generate the clock card 1 data signal (GD2) to be transmitted and for calculating the parity of the data signals already from card 2 generated signals become effective and then executes the command 62 to switch back the clock counter Cpt2. At this point in time, the microprocessor 22 has finished executing the transmission program and can,

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as in the case of the other microprocessor «; Ad mentioned until the moment when the following clock pulse falls and therefore the execution of the d © s Transmission program starts again, other programs perform, for example, the speed control of a motor, etc. So each of the di © Transmission of a message, as described, and di @ Alternate execution of another program.

If the module 54 for reading the data signal and calculating the parity is the twenty-fourth and last Has read the data signal (LD24 '), the clock counter Cpt2 assumes the value 0, and the microprocessor 22 performs the Branch instruction 52 to initialization instruction 55 for the clock counter Cpt2, so that it is set to the value 25, and then successively the Activation command 56 for the synchronization line 4 and the module 57 for generating the parity (GP) operative; this parity is when the previous one falls Clock pulse has been calculated by module 61, which, as mentioned, for generating the data signal and for calculating the parity of the 24 data generated by the card 2 and forming the message (GD1 to GD24) is used. As mentioned earlier, the program ends with the command 62 to switch back the clock counter Cpt2.

When the next clock pulse arrives, the microprocessor 40 performs when the pulse rises, as before, successively the program (Figure 3) with the set command 49 '(PE), the delay module 50 "and the command 62' to switch back the clock counter Cpt1!, uwia the branch instruction 63 to the conditional branch command 5.2 ', which sets the cycle counter Cpt1 to the value 0,

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If the synchronization between the generation and reading of the message is correct, the clock counter Cpt1 has the value O ₁ and the following program is successively executed by the microprocessor 40: The module 59 'for reading the parity generated by the card 2 (LP) , the conditional branch instruction 53 "in the event of equality between the parity read by module 59 'and the parity calculated by module 54" when the previous clock pulse rises, this module 54' being set up to read the data signal and the parity of the the card 2 generated 24 data (GD1 to GD24) to calculate. If this parity is correct, the microprocessor 40 allows the module 60 'to operate to enable the message. Otherwise the message will be considered invalid. In both cases, the microprocessor 40 executes the initialization command 55 'for the clock counter Cpt1 to set it to the value 25 and enables the module 57 "to generate the parity (GP") calculated by the module 61 "when the previous clock pulse rises; this module 61 'is used to generate the data signal and to calculate the parity of the data (GD1' to GD24 ') which form the message and generated by the card 1. The execution of the transmission program is thus ended and the microprocessor 40 awaits the following rising clock pulse.

If the synchronization between the creation and reading of the message is not correct, then the 7 λ kt ; r '. \ H 1 or Cpt1 does not reach the value 0 at the point in time at which the synchronization <-. 1 r> itation 4 becomes active, and <li> r Mi U ι .ipiu. · ■> ■. · ,,,! 40 leads ₍ | · <ιι ίΐ.-i..hl Vj ' .χ us, and

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lets module 57 '(GP') take effect without the ^ Release message or air. valid, -u wo i

When the following clock pulse falls, the microprocessor 22, after the set command 49 (PE) and the delay module 50 (Figure 2) have become effective and since the clock counter Cpt2 has the value 24, executes the command 5 8 to switch off the synchronization s 1 <> ι t uny 4 from (Figure 4), then allows the module VJ to read the parity (LP ') generated by the card 1 wi rks.im and finally leads the conditional branch command 53 to the equality of the parity read by the module 59 and the parity calculated by module 54 when the previous clock pulse fell; This module 54 is used to read the data signal and to calculate the parity of the 24 data generated by the card 1 (GD1 ¹ to GD24 '). If the parity is correct, the microprocessor 22 allows the GO module to operate to enable the message. Otherwise the message will be considered invalid. In either case, the microprocessor 22 terminates the execution of the transmission
Program, as indicated above, by allowing the module 61 to take effect, which generates the first data signal (GD1) of the following message for the purpose of transmission to the card 1, and by then executing the command 62.

Claims (5)

PATENT CLAIMS J / Method for the transmission of a message with η Data in serial form between two elektromschan cards (1,2), which are connected to each other by © into the clock pulse line (3), one data line (5) and one © synchronization line (4) are connected, with one of the cards (2), which has a clock, on the Clock pulse line (3) generates a clock pulse which is sent from the other card (1), the © in © n Having clock pulse receiver, is read, with a © the cards (2), which has a data transmitter on the Data & line (5) a sequence of data generated by the other card (1), which is a data receiver having to be read, and wherein further one of the cards (2). which have a synchronization signal generator has generated a synchronization signal to the To activate the synchronization line (4) temporarily at the end © of a message, characterized in that the data receiver card (1) after reading each of the The data transmitter card (2) generates a data signal in turn on the same data line (5) opposite sense in the direction of the © data generator card (2) that these data generator cards (2) reads this data signal before it generates the following data signal itself, to a simultaneous Bidirectional transmission of the two messages, each allowing η data, by the one card (1) to the Time of the rise of the clock pulse and the other Kart «(2) at the time of the fall of the clock pulse in The function occurs that each card after reading the last data signal generated by the other card of the Message a parity information in the direction of this other card generated and that each card ended up of the message reads the parity information sent by the other card and that of the other Card evaluates received η data as valid if the parity is correct and if, if it is the card not generating the sync signal (1) acts, the synchronization line (4) is active. 2. Electronic circuit arrangement for carrying out the transmission method according to claim 1, with two electronic cards (1,2) through a clock pulse line (J), a data line (5) and a synchronization line (4) are connected to each other and of which one, the clock having card (2) Circuits for generating clock pulses on the clock pulse line (3) in the direction of the other card (I) which has circuits (30 and 40) for clock pulse reception, wherein the one card (1) represents a data generator card that contains circuits (3U, 40) to generate a sequence of η data on the Has data line (5) which are read by the other card (1), which is a data receiver card and a reading circuit (40) for this data, and wherein furthermore one of the cards (2) Having circuits (22) for generating a synchronization signal on the synchronization line (4), to temporarily activate this synchronization line (4) at the end of a message, characterized in that that the reading circuit (40) of the data receiver card (1) is set up to be used by the Datenkdi'Le generated data at the point in time at which the clock pulse rises or falls, that the data receiver card (1) also has a circuit (4UJ ZUi- Da tone generation, which for this purpose β «e · * Ο «α ο» ο · β « is directed, in turn <* at the following point in time au + the same data line (5) wiiien ^ ΐ ^ ιιαΐμι · ΐ) ΐ ^ .'u generate which em on the UatengebyiKdiIe (<L) su transmitted data signal represents that this Uatengeberkarte (2) has a reading circuit (22) which is set up to read the data previously sent out by the data receiver card (1) on the data line (5) at the point in time at which the clock pulse falls or rises, specifically just now before the data transmitter circuit (22) of the data transmitter card (2) generates a signal level on the same data line (5) which represents the signal to be transmitted to the data receiver card (1) that each card has a circuit for calculating the parity of the data it generates which is set up, after reading the η η ^^ data signal generated by the other card, to generate parity information on the data line (5) that the card (1), which does not have the circuit for generating the Sy nchronization signal, has a clock counter (Cpt1) and a circuit for parity control, which is set up at the point in time at which the clock pulse rises or falls and at which its clock counter (Cpt1) reaches the end value corresponding to the end of the message, the to read parity information sent out by the second card (2) and to evaluate the η data received from this as valid, if both the parity is correct and the synchronization line (4) is activated, that the clock counter (Cpt1) at its Initial wait is reset, regardless of whether the data are evaluated as valid or not, and that the second card (2) has a circuit for parity control, which is set up by the first card (1) sent to parity information read and evaluate the η data received from this card as valid if at the time at which the Clock pulse falls or rises, the parity is correct, while the synchronization line (4) is activated is. 3. Electronic circuit arrangement according to claim 2, characterized in that the clock having the Card (2) has a pulse shaper circuit (20) which is set up on the clock pulse line (3) to generate pulses with the frequency of the feeding AC voltage network, in such a way that the both cards can simultaneously perform other tasks synchronously with the AC voltage network. ι *. Electronic circuit arrangement according to Claim 2 or 3, characterized in that the data transmitter circuit of each card (2; 1) is formed by a control unit (22; 40) which on the one hand has a bidirectional input-output terminal (A2; G2) and on the other hand a Current limiting device (23; 23) which is connected to the data line (5) in series to ensure the simultaneous existence of the data generated by the two cards (2; 1) at the respective two input-output terminals (A2; G2) of the to enable both control units. 5. Electronic circuit arrangement according to claim 4, characterized in that each card (2; 1) one between the relevant control unit (22; 40) and the Data line (5) switched ^ filters (23, 24; 23 ', 24 ") and a delay circuit (22; 40) which allows the filter to reach the value corresponding to the ) D O OOOQ β • β no OOQ α
Qa α ο f »ο 000 from the other card (1; 2) transmitted data signal after dxe Datenleituny (ί>) before your Ic.un this data signal has been set to input by the control unit (22; 40).