CN221127827U - Display device - Google Patents

Abstract

A display device is provided. The display device includes: a display area, a non-display area, and a pad area; a plurality of data lines arranged to extend from the pad area to the display area along a first direction; a plurality of connection wirings arranged to be separated from the data lines and extending from the pad area to both sides of the display area in the non-display area in a second direction intersecting the first direction; and a plurality of pads arranged to overlap with the data lines and the connection wirings in the pad area, wherein the connection wirings include: a first connection wiring overlapping with the pad and extending along the first direction; a second connection wiring not overlapping with the pad and arranged to overlap with the first connection wiring in the non-display area; and a third connection wiring overlapping with the first connection wiring and electrically connected to the pad, wherein the first connection wiring and the third connection wiring are arranged to overlap with each other in the pad area, and the first connection wiring, the second connection wiring, and the third connection wiring are arranged to overlap with each other in the non-display area.

Description

Display device

Technical Field

The utility model relates to a display device.

Background technique

As multimedia develops, the importance of display devices is increasing. In response to this, various display devices such as organic light emitting display devices (OLED: Organic Light Emitting Display) and liquid crystal display devices (LCD: Liquid Crystal Display) are being used.

As a device for displaying an image of a display device, there is a self-luminous display device including a light-emitting element. The self-luminous display device includes an organic light-emitting display device including a light-emitting element using an organic substance as a light-emitting material, or an inorganic light-emitting display device including a light-emitting element using an inorganic substance as a light-emitting material.

Utility Model Content

The technical problem to be solved by the utility model is to provide a display device with a reduced step difference of a pad electrode in a pad region where multiple layers are stacked.

The technical problems of the present invention are not limited to the technical problems mentioned above, and those skilled in the art can clearly understand other technical problems not mentioned through the following records.

A display device according to one embodiment for solving the above-mentioned technical problems includes: a display area, a non-display area surrounding the display area, and a pad area arranged on one side of the display area in a first direction and surrounded by the non-display area; a plurality of data lines arranged to extend from the pad area along the first direction to the display area; a plurality of connection wirings arranged to be separated from the data lines and extending from the pad area to both sides of the display area in the non-display area in a second direction intersecting the first direction; and a plurality of pads arranged in the pad area to overlap with the data lines and the connection wirings, wherein the connection wirings include: a first connection wiring overlapping with the pad and extending along the first direction; a second connection wiring not overlapping with the pad and arranged to overlap with the first connection wiring in the non-display area; and a third connection wiring overlapping with the first connection wiring and electrically connected to the pad, wherein in the pad area, the first connection wiring and the third connection wiring are arranged to overlap with each other, and in the non-display area, the first connection wiring, the second connection wiring and the third connection wiring are arranged to overlap with each other.

The plurality of pads may include: a plurality of first pads, which are arranged in the pad region so as to overlap with the data line; and a plurality of second pads, which are arranged in the pad region so as to be separated from the first pads along the second direction and arranged so as to overlap with the connection wiring, wherein the first connection wiring may overlap with the second pad, the second connection wiring may not overlap with the second pad, and the third connection wiring may be electrically connected to the second pad.

Each of the first pad and the second pad may include a pad base layer and a pad upper layer arranged on the pad base layer and contacting the pad base layer through a pad contact hole, and the pad base layer of each of the first pad and the second pad may directly contact the data line or the first connection wiring through a first contact hole and a second contact hole spaced apart from the pad contact hole along the first direction.

The data line may overlap the first contact hole, the pad contact hole, and the second contact hole respectively overlapping the first pad in the pad region.

The first connection wiring may respectively overlap with the first contact hole, the pad contact hole and the second contact hole overlapping with the second pad in the pad area, and the third connection wiring may be directly connected to the pad upper layer of the second pad in the pad area, and may be directly contacted with the second connection wiring through a third contact hole formed in a portion overlapping with the first connection wiring and the second connection wiring, respectively, in the non-display area.

The first pad and the second pad may respectively include: a first portion overlapping with the pad contact hole; a second portion overlapping with the first contact hole or the second contact hole; and a third portion arranged between the first portion and the second portion, wherein the widths of the first portion, the second portion and the third portion measured in the second direction may be different from each other.

The width of the first portion may be greater than the widths of the second portion and the third portion, the width of the third portion may be greater than the width of the second portion, the widths of the data line and the pad base layer and the pad upper layer measured in the second direction may be different from each other, and in each of the first portion, the second portion and the third portion, the width difference between the data line, the pad base layer and the pad upper layer may be constant.

The width of the data line measured in the second direction may be greater than the width of the first pad measured in the second direction, and the width of the pad base layer of the first pad and the second pad measured in the second direction may be smaller than the width of the pad upper layer measured in the second direction, respectively.

An interval between adjacent data lines in the pad region may be smaller than an interval between adjacent first pads.

The display device may further include: a plurality of scan lines arranged between the data lines and extending from the pad area to the display area; and a plurality of third pads arranged in the pad area to overlap with the scan lines, wherein the third pads and the first pads may be arranged non-parallel along the second direction, and a spacing between adjacent first pads in the second direction may be greater than a spacing between the data lines and the scan lines.

A display device according to an embodiment for solving the above technical problems includes: a display area in which a plurality of pixels are arranged, a non-display area surrounding the display area, and a pad area arranged on one side of the display area in a first direction and surrounded by the non-display area; a first electrode and a second electrode, arranged in the display area to extend along the first direction and spaced apart from each other along a second direction intersecting the first direction; a plurality of light emitting elements, arranged on the first electrode and the second electrode in the display area; a plurality of data lines, arranged to extend from the pad area to the display area along the first direction; and a plurality of connection wirings, arranged to be spaced apart from the data lines and extending from the pad area to both sides of the display area in the non-display area in the second direction. and arranged; a plurality of first pads, which are arranged in the pad area so as to overlap with the data line; and a plurality of second pads, which are arranged in the pad area so as to be separated from the first pad along the second direction and arranged so as to overlap with the connection wiring, wherein the connection wiring includes: a first connection wiring, which overlaps with the second pad and extends along the first direction; a second connection wiring, which does not overlap with the second pad and is arranged in the non-display area so as to overlap with the first connection wiring; and a third connection wiring, which overlaps with the first connection wiring and is electrically connected to the second pad, wherein in the pad area, the first connection wiring and the third connection wiring are arranged so as to overlap with each other, and in the non-display area, the first connection wiring, the second connection wiring and the third connection wiring are arranged so as to overlap with each other.

Each of the first pad and the second pad may include a pad base layer and a pad upper layer arranged on the pad base layer and contacting the pad base layer through a pad contact hole, and the pad base layer of each of the first pad and the second pad may directly contact the data line or the first connection wiring through a first contact hole and a second contact hole spaced apart from the pad contact hole along the first direction.

The data line may overlap the first contact hole, the pad contact hole, and the second contact hole overlapping the first pad in the pad region, respectively.

The first connection wiring may respectively overlap with the first contact hole, the pad contact hole and the second contact hole overlapping with the second pad in the pad area, and the third connection wiring may be directly connected to the pad upper layer of the second pad in the pad area, and may be directly contacted with the second connection wiring through a third contact hole formed in a portion overlapping with the first connection wiring and the second connection wiring, respectively, in the non-display area.

The first pad and the second pad may respectively include: a first portion overlapping with the pad contact hole; a second portion overlapping with the first contact hole or the second contact hole; and a third portion arranged between the first portion and the second portion, wherein the widths of the first portion, the second portion and the third portion measured in the second direction may be different from each other.

The width of the first portion may be greater than the widths of the second portion and the third portion, the width of the third portion may be greater than the width of the second portion, the widths of the data line and the pad base layer and the pad upper layer measured in the second direction may be different from each other, and in each of the first portion, the second portion and the third portion, the width difference between the data line, the pad base layer and the pad upper layer may be constant.

A width of the data line measured in the second direction may be greater than a width of the first pad measured in the second direction.

The width of the pad base layer of the first pad and the second pad measured in the second direction may be smaller than the width of the pad upper layer measured in the second direction, respectively.

An interval between adjacent data lines in the pad region may be smaller than an interval between adjacent first pads.

The display device may further include: a plurality of scan lines arranged between the data lines and extending from the pad area to the display area; and a plurality of third pads arranged in the pad area to overlap with the scan lines, wherein the third pads and the first pads may be arranged non-parallel to each other along the second direction, and a spacing between adjacent first pads in the second direction may be greater than a spacing between the data lines and the scan lines.

Details of other embodiments are included in the detailed description and drawings.

In the display device according to an embodiment, the wiring electrically connected to the pad in the pad region may be arranged to completely overlap with the pad, thereby minimizing a step difference formed by the overlapping arrangement of the pad and the insulating layer.

Also, the display device according to an embodiment may have a shape in which the width of the pad varies according to a position, and misalignment in an alignment process of components disposed on the pad and the pad can be reduced.

In the display device, the connection structure is formed in the display region, thereby preventing a voltage drop in a potential applied to the common electrode.

The effects according to the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a display device according to an embodiment.

FIG. 2 is a plan view showing the arrangement of a plurality of wirings arranged in the display device of FIG. 1 .

FIG. 3 is a diagram illustrating pixels and lines of a display device according to an embodiment.

FIG. 4 is a circuit diagram showing a pixel of a display device according to an embodiment.

FIG. 5 is a plan view showing a light emitting element layer of a display device according to an embodiment.

FIG. 6 is a plan view showing a fourth metal layer of a display device according to an embodiment.

FIG. 7 is a plan view showing a fifth metal layer of a display device according to an embodiment.

FIG. 8 is a schematic cross-sectional view of a display device according to an embodiment.

FIG. 9 is a schematic diagram of a light emitting element according to an embodiment.

FIG. 10 is a plan view showing an arrangement of a pad region of a display device and wirings arranged around the pad region according to an embodiment.

FIG. 11 is an enlarged view of portion A of FIG. 10 .

FIG. 12 is a cross-sectional view taken along line XII-XII′ of FIG. 11 .

FIG. 13 is a cross-sectional view taken along line XIII-XIII′ of FIG. 11 .

FIG. 14 is an enlarged view showing a portion of a pad portion of a display device according to an embodiment.

FIG. 15 is an enlarged view of portion B of FIG. 10 .

FIG16 is a cross-sectional view taken along line XVI-XVI′ of FIG15 .

FIG. 17 is a cross-sectional view taken along line XVII-XVII′ of FIG. 15 .

FIG. 18 is a plan view showing an arrangement of a pad region of a display device and wirings arranged around the pad region according to another embodiment.

FIG. 19 is an enlarged view of portion C of FIG. 18 .

FIG. 20 is an enlarged view of portion D of FIG. 18 .

FIG21 is a cross-sectional view taken along line XXI-XXI′ of FIG19.

FIG. 22 is a cross-sectional view taken along line XXII-XXII′ of FIG. 20 .

Description of Reference Numerals

10: Display device

100: Display panel

210: Flexible membrane

220: Display driver

230: Circuit board

ED: Light Emitting Element

RME1, RME2: Electrodes

CTE1, CTE2, CTE3, CTE4, CTE5: contact electrodes

DA: Display Area NDA: Non-Display Area PDA: Pad Area

DP1, DP2, DP3: Pad

DPE1: base layer DPE2: top layer

CT1, CT2: contact hole CTA: pad contact hole

MBL: Connection wiring

Detailed ways

The advantages and features of the present invention and the methods for achieving the advantages and features of the present invention as well as the methods for achieving the advantages and features of the present invention can be clearly seen by referring to the embodiments described in detail below together with FIG. 1. However, the present invention can be implemented in various forms different from each other, and is not limited to the embodiments disclosed below, and the purpose of providing the present embodiments is only to make the disclosure of the present invention complete and to fully inform the scope of the present invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is only defined by the scope of the claims.

When an element or layer is referred to as being "on" another element or layer, this includes all cases where the element or layer is immediately above the other element or layer or where other layers or other elements are sandwiched between them. Similarly, cases referred to as "below," "left," and "right" include cases where the element or layer is directly adjacent to other elements or layers or where other layers or other elements are sandwiched between them. Throughout the specification, the same reference numerals refer to the same constituent elements.

Although "first", "second", etc. are used to describe various components, these components are obviously not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can obviously also be the second component within the technical concept of the utility model.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a plan view showing a display device according to an embodiment.

1 , the display device 10 displays a moving image or a still image. The display device 10 may refer to all electronic devices that provide a display screen. For example, a television, a notebook computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet PC (Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP: PortableMultimediaPlayer), a navigator, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the display device 10.

The display device 10 includes a display panel that provides a display screen. Examples of display panels include inorganic light emitting diode display panels, organic light emitting display panels, quantum dot light emitting display panels, plasma display panels, and field emission display panels. Hereinafter, as an example of a display panel, an inorganic light emitting diode display panel is used, but it is not limited thereto. If the same technical concept can be applied, other display panels can also be applied.

The shape of the display device 10 can be variously deformed. For example, the display device 10 can have a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of the display device 10 can also be similar to the overall shape of the display device 10. In FIG. 1 , a display device 10 having a rectangular shape that is long in the second direction DR2 is illustrated.

The display device 10 may include a display area DA and a non-display area NDA. The display area DA is an area where a picture can be displayed, and the non-display area NDA is an area where a picture is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may be referred to as an inactive area. The display area DA may occupy approximately the center of the display device 10.

The display area DA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in rows and columns. The shape of each pixel PX may be a rectangle or a square on a plane, but is not limited thereto, and may also be a rhombus shape with each side inclined relative to a direction. Each pixel PX may be arranged in a stripe type or an island type. Furthermore, each pixel PX may include one or more light emitting elements that emit light of a specific wavelength band to display a specific color.

A non-display area NDA may be arranged around the display area DA. The non-display area NDA may surround the display area DA in whole or in part. The display area DA may be in a rectangular shape, and the non-display area NDA may be arranged adjacent to four sides of the display area DA. The non-display area NDA may constitute a frame of the display device 10. Wiring or circuit driving parts included in the display device 10 may be arranged in each non-display area NDA, or an external device may be installed.

FIG. 2 is a plan view showing the arrangement of a plurality of wirings arranged in the display device of FIG. 1 .

2 , the display device 10 may include a display panel 100 , a flexible film 210 , a display driving part 220 , a circuit board 230 , a timing control part 240 , a power supply part 250 , a gate driving part 260 , and a protective metal layer 300 .

The display panel 100 may be configured in a rectangular form in a plane. For example, the display panel 100 may have a rectangular plane form including a short side in the first direction DR1 and a long side in the second direction DR2. The corner where the short side in the first direction DR1 meets the long side in the second direction DR2 may be formed as a right angle, or may be formed smoothly in a manner having a predetermined curvature. The plane form of the display panel 100 is not limited to a rectangle, and may be formed in other polygonal, circular, or elliptical shapes. For example, the display panel 100 may be formed flat, but is not limited thereto. As another example, the display panel 100 may be formed curved with a predetermined curvature.

The display panel 100 may include a display area DA and a non-display area NDA.

The display area DA is an area where an image is displayed, and may be defined as a central area of the display panel 100. The display area DA may include a sub-pixel SP, a gate line GL, a data line DL, an initialization voltage line VIL, a first voltage line VDL, a horizontal voltage line HVDL, a vertical voltage line VVSL, and a second voltage line VSL. The sub-pixel SP may be formed in each pixel area crossed by the data line DL and the gate line GL.

The display device 10 may include a plurality of sub-pixels SP constituting one pixel PX. The sub-pixel SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be connected to one gate line GL and one data line DL. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be defined as an area of a minimum unit of output light.

Each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may include an organic light emitting diode (Organic Light Emitting Diode) including an organic light emitting layer, a quantum dot light emitting element (Quantum Dot LED) including a quantum dot light emitting layer, an ultra-small light emitting diode (Micro LED) or an inorganic light emitting diode (Inorganic LED) including an inorganic semiconductor.

The first sub-pixel SP1 can emit light of a first color or red light, the second sub-pixel SP2 can emit light of a second color or green light, and the third sub-pixel SP3 can emit light of a third color or blue light. The pixel circuits of the first sub-pixel SP1, the third sub-pixel SP3, and the second sub-pixel SP2 can be arranged along the first direction DR1, but the order of the pixel circuits is not limited thereto.

The gate lines GL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The gate lines GL may receive gate signals from the gate driving unit 260 to supply gate signals to the auxiliary gate lines BGL. The auxiliary gate lines BGL may extend from the gate lines GL to supply gate signals to the first, second, and third subpixels SP1, SP2, and SP3.

The data lines DL may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 may supply data voltages to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

The initialization voltage lines VIL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The initialization voltage lines VIL may supply an initialization voltage received from the display driving section 220 to a pixel circuit of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The initialization voltage lines VIL may receive a sensing signal from a pixel circuit of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and supply it to the display driving section 220.

The first voltage lines VDL may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2 . The first voltage lines VDL may supply a driving voltage or a high potential voltage received from the power supply part 250 to the first, second, and third subpixels SP1 , SP2 , and SP3 .

The horizontal voltage lines HVDL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The horizontal voltage lines HVDL may be connected to the first voltage lines VDL. The horizontal voltage lines HVDL may receive a driving voltage or a high potential voltage from the first voltage lines VDL.

The vertical voltage lines VVSL may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2. The vertical voltage lines VVSL may be connected to the second voltage line VSL. The vertical voltage lines VVSL may supply a low potential voltage received from the power supply part 250 to the second voltage line VSL.

The second voltage lines VSL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The second voltage line VSL may supply a low potential voltage to the first to third sub-pixels SP1, SP2, and SP3.

The connection relationship among the sub-pixels SP, the gate lines GL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL and the second voltage lines VSL may be designed differently according to the number and arrangement of the sub-pixels SP.

The non-display area NDA may be defined as a remaining area except the display area DA in the display panel 100. For example, the non-display area NDA may include a fan-out line connecting the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driving part 220, and a pad portion (not shown) connected to the gate driving part 260 and the flexible film 210.

The flexible film 210 may be connected to a pad portion disposed at the lower side of the non-display area NDA. An input terminal provided on one side of the flexible film 210 may be attached to the circuit board 230 by a film attachment process, and an output terminal provided on the other side of the flexible film 210 may be attached to the pad portion by a film attachment process. For example, the flexible film 210 may be bent like a tape carrier package or a chip on film. The flexible film 210 may be bent to the lower portion of the display panel 100 in order to reduce the frame area of the display device 10.

The display driving part 220 may be mounted on the flexible film 210. For example, the display driving part 220 may be implemented by an integrated circuit (IC). The display driving part 220 may receive digital video data and a data control signal from the timing control part 240, and convert the digital video data into an analog data voltage according to the data control signal and supply it to the data line DL through the fan-out line.

The circuit board 230 may support the timing control section 240 and the power supply section 250, and may supply signals and power to the display driving section 220. For example, in order to display an image on each pixel, the circuit board 230 may supply a signal supplied from the timing control section 240 and a power supply voltage supplied from the power supply section 250 to the flexible film 210 and the display driving section 220. To this end, a signal line and a power line may be provided on the circuit board 230.

The timing control section 240 may be mounted on the circuit board 230, and may receive image data and a timing synchronization signal supplied from a display driving system or a graphics device through a user connector provided on the circuit board 230. The timing control section 240 may align the image data in a manner suitable for the pixel arrangement structure based on the timing synchronization signal to generate digital video data, and may supply the generated digital video data to the display driving section 220. The timing control section 240 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing control section 240 may control the supply timing of the data voltage of the display driving section 220 based on the data control signal, and may control the supply timing of the gate signal of the gate driving section 260 based on the gate control signal.

The power supply unit 250 may be disposed on the circuit board 230 to supply power supply voltage to the flexible film 210, the display driving unit 220, and the gate driving unit 260. For example, the power supply unit 250 may generate a driving voltage or a high potential voltage and supply it to the first voltage line VDL, may generate a low potential voltage and supply it to the vertical voltage line VVSL, and may generate an initialization voltage and supply it to the initialization voltage line VIL. The power supply unit 250 may generate a gate high voltage and a gate low voltage and supply them to the gate driving unit 260.

The gate driving unit 260 may be arranged on the left and right sides of the non-display area NDA. The gate driving unit 260 may generate a gate signal based on a gate control signal supplied from the timing control unit 240. The gate control signal may include a start signal, a clock signal, and a power supply voltage, but is not limited thereto. The gate driving unit 260 may supply the gate signal to the gate line GL according to a set order.

The protective metal layer 300 may be disposed on the left and right sides of the non-display area NDA and overlap the gate driving part 260. The protective metal layer 300 may be disposed on the gate driving part 260 to protect the gate driving part 260. The protective metal layer 300 may receive a power supply voltage from the power supply part 250. For example, the protective metal layer 300 may receive a low potential voltage from the power supply part 250 to eliminate static electricity applied from the outside.

FIG. 3 is a diagram illustrating pixels and lines of a display device according to an embodiment.

3 , the subpixel SP may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The pixel circuits of the first subpixel SP1, the third subpixel SP3, and the second subpixel SP2 may be arranged in opposite directions of the first direction DR1, but the order of the pixel circuits is not limited thereto.

Each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a gate line GL, and a data line DL.

The first voltage line VDL may extend in the first direction DR1. The first voltage line VDL may be arranged on the left side of the pixel circuits of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first voltage line VDL may supply a driving voltage or a high potential voltage to the transistor of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

The horizontal voltage line HVDL may extend along the second direction DR2. The horizontal voltage line HVDL may be arranged at the upper side of the pixel circuit of the first sub-pixel SP1 arranged in the k-th row ROWk (k is a positive integer). The horizontal voltage line HVDL may be connected to the first voltage line VDL. The horizontal voltage line HVDL may receive a driving voltage or a high potential voltage from the first voltage line VDL.

The vertical voltage line VVSL may extend along the first direction DR1. The vertical voltage line VVSL may be arranged on the left side of the first voltage line VDL. The vertical voltage line VVSL may be connected between the power supply unit 250 and the second voltage line VSL. The vertical voltage line VVSL may supply the low potential voltage supplied from the power supply unit 250 to the second voltage line VSL.

The second voltage line VSL may extend along the second direction DR2. The second voltage line VSL may be disposed on an upper side of a pixel circuit of a first sub-pixel SP1 disposed in the k+1th row ROWk+1. The second voltage line VSL may supply a low potential voltage received from the vertical voltage line VVSL to the light emitting element layers of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

The gate line GL may extend along the second direction DR2. The gate line GL may be arranged at the lower side of the pixel circuit of the second sub-pixel SP2. The gate line GL may supply a gate signal received from the gate driving unit 260 to the auxiliary gate line BGL. For example, the k-th gate line GLk may supply a gate signal to the sub-pixel SP arranged in the k-th row ROWk, and the k+1-th gate line GLk+1 may supply a gate signal to the sub-pixel SP arranged in the k+1-th row ROWk+1.

The auxiliary gate line BGL may extend from the gate line GL along the first direction DR1. The auxiliary gate line BGL may be arranged on the right side of the pixel circuits of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. The auxiliary gate line BGL may supply a gate signal received from the gate line GL to the pixel circuits of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

The initialization voltage line VIL may extend along the first direction DR1. The initialization voltage line VIL may be arranged on the right side of the auxiliary gate line BGL. The initialization voltage line VIL may supply an initialization voltage to a pixel circuit of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The initialization voltage line VIL may receive a sensing signal from a pixel circuit of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and supply it to the display driving part 220.

The data lines DL may extend in the first direction DR1. The data lines DL may supply data voltages to the sub-pixels SP. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3.

The first data line DL1 may extend in the first direction DR1. The first data line DL1 may be disposed on the right side of the initialization voltage line VIL. The first data line DL1 may supply a data voltage received from the display driving part 220 to a pixel circuit of the first sub-pixel SP1.

The second data line DL2 may extend in the first direction DR1. The second data line DL2 may be disposed on the right side of the first data line DL1. The second data line DL2 may supply a data voltage received from the display driving part 220 to a pixel circuit of the second sub-pixel SP2.

The third data line DL3 may extend in the first direction DR1. The third data line DL3 may be disposed on the right side of the second data line DL2. The third data line DL3 may supply a data voltage received from the display driving part 220 to a pixel circuit of the third sub-pixel SP3.

FIG. 4 is a circuit diagram showing a pixel of a display device according to an embodiment.

4 , each sub-pixel SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a gate line GL, and a second voltage line VSL.

Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a pixel circuit and a plurality of light emitting elements ED. The pixel circuit may include first, second, and third transistors ST1, ST2, and ST3, and a first capacitor C1.

The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 may be connected to the first node N1, the drain electrode of the first transistor ST1 may be connected to the first voltage line VDL, and the source electrode of the first transistor ST1 may be connected to the second node N2. The first transistor ST1 may control a drain-source current (or a driving current) based on a data voltage applied to the gate electrode.

The light emitting element ED may include a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3 and a fourth light emitting element ED4. The first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3 and the fourth light emitting element ED4 may be connected in series. The first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3 and the fourth light emitting element ED4 may receive a driving current to emit light. The amount of light emitted or the brightness of the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an organic light emitting diode (Organic Light Emitting Diode) including an organic light emitting layer, a quantum dot light emitting element (Quantum Dot LED) including a quantum dot light emitting layer, an ultra-small light emitting diode (Micro LED) or an inorganic light emitting diode (Inorganic LED) including an inorganic semiconductor.

A first electrode of the first light emitting element ED1 may be connected to the second node N2, and a second electrode of the first light emitting element ED1 may be connected to a third node N3. The first electrode of the first light emitting element ED1 may be connected to a source electrode of the first transistor ST1, a drain electrode of the third transistor ST3, and a second capacitor electrode of the first capacitor C1 through the second node N2. The second electrode of the first light emitting element ED1 may be connected to a first electrode of the second light emitting element ED2 through the third node N3.

A first electrode of the second light emitting element ED2 may be connected to the third node N3, and a second electrode of the second light emitting element ED2 may be connected to the fourth node N4. A first electrode of the third light emitting element ED3 may be connected to the fourth node N4, and a second electrode of the third light emitting element ED3 may be connected to the fifth node N5. A first electrode of the fourth light emitting element ED4 may be connected to the fifth node N5, and a second electrode of the fourth light emitting element ED4 may be connected to the second voltage line VSL.

The second transistor ST2 may be turned on by a gate signal of the gate line GL to electrically connect the data line DL to the first node N1 which is the gate electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the gate signal to supply the data voltage to the first node N1. The gate electrode of the second transistor ST2 may be connected to the gate line GL, the drain electrode of the second transistor ST2 may be connected to the data line DL, and the source electrode of the second transistor ST2 may be connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the gate electrode of the first transistor ST1 and the first capacitor electrode of the first capacitor C1 through the first node N1.

The third transistor ST3 may be turned on by the gate signal of the gate line GL to electrically connect the initialization voltage line VIL to the second node N2 as the source electrode of the first transistor ST1. The third transistor ST3 may be turned on based on the gate signal to supply the initialization voltage to the second node N2. The third transistor ST3 may be turned on based on the gate signal to supply the sensing signal to the initialization voltage line VIL. The gate electrode of the third transistor ST3 may be connected to the gate line GL, the drain electrode of the third transistor ST3 may be connected to the second node N2, and the source electrode of the third transistor ST3 may be connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode of the first transistor ST1, the second capacitor electrode of the first capacitor C1, and the first electrode of the first light emitting element ED1 through the second node N2.

Fig. 5 is a plan view showing a light emitting element layer of a display device according to an embodiment. Fig. 6 is a plan view showing a fourth metal layer of a display device according to an embodiment. Fig. 7 is a plan view showing a fifth metal layer of a display device according to an embodiment. Fig. 8 is a schematic cross-sectional view of a display device according to an embodiment.

5 to 8 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML.

The substrate SUB may be a base substrate or a base component. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB may include a glass material or a metal material, but is not limited thereto. As another example, the substrate SUB may include a polymer resin such as polyimide (PI).

The thin film transistor layer TFTL may be disposed on the substrate SUB and may include a first metal layer MTL1, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a second metal layer MTL2, an interlayer insulating layer ILD, a third metal layer MTL3, a protection layer PV, and a via layer VIA.

The first metal layer MTL1 may be disposed on the substrate SUB. The first metal layer MTL1 may include a voltage line VL, a first voltage line VDL, and a vertical voltage line VVSL. The voltage line VL may be a first voltage line VDL, an initialization voltage line VIL, or a data line DL.

The buffer layer BF may be disposed on the first metal layer MTL1. For example, the buffer layer BF may include an inorganic film capable of preventing air or moisture from penetrating. For example, the buffer layer BF may include a plurality of inorganic films alternately stacked.

The active layer ACTL may be arranged on the buffer layer BF. The active layer ACTL may include a drain electrode DE, a semiconductor region ACT, and a source electrode SE of the thin film transistor TFT. The thin film transistor TFT may be the first transistor ST1 of FIG. 4 , but is not limited thereto. For example, the semiconductor region ACT of the thin film transistor TFT may include low temperature polycrystalline silicon (LTPS: Low Temperature Polycrystalline Silicon). The electron mobility of the thin film transistor TFT including low temperature polycrystalline silicon is high and the conduction characteristics may be excellent. As another example, the semiconductor region ACT of the thin film transistor TFT may include an oxide. The thin film transistor TFT including an oxide has an excellent leakage current characteristic and can be driven at a low frequency, thereby reducing power consumption.

A gate insulating layer GI may be disposed on the active layer ACTL. The gate insulating layer GI may insulate the active layer ACTL from the second metal layer MTL2.

The second metal layer MTL2 may be disposed on the gate insulating layer GI. The second metal layer MTL2 may include a gate electrode GE of the thin film transistor TFT. The gate electrode GE of the thin film transistor TFT may overlap with the semiconductor region ACT.

An interlayer insulating layer ILD may be disposed on the second metal layer MTL2 . The interlayer insulating layer ILD may insulate the second metal layer MTL2 from the third metal layer MTL3 .

The third metal layer MTL3 may be arranged on the interlayer insulating layer ILD. The third metal layer MTL3 may include a connection electrode CE, a first anode connection electrode ANE1, a horizontal voltage line HVDL, and a second voltage line VSL. The connection electrode CE may electrically connect the voltage line VL to the source electrode SE of the thin film transistor TFT. The first anode connection electrode ANE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the first contact electrode CTE1. The horizontal voltage line HVDL may electrically connect the first voltage line VDL to the first electrode RME1. The second voltage line VSL may electrically connect the vertical voltage line VVSL to the second electrode RME2, and may electrically connect the vertical voltage line VVSL to the fifth contact electrode CTE5.

The protection layer PV may be disposed on the third metal layer MTL3. The protection layer PV may be disposed on the plurality of thin film transistors TFT to protect the pixel circuits of the sub-pixels SP.

The via layer VIA may be disposed on the protective layer PV. The via layer VIA may planarize the upper end of the thin film transistor layer TFTL. The via layer VIA may include an organic insulating material such as polyimide (PI).

The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a first bank pattern BP1, a second bank pattern BP2, and a third bank pattern BP3, a first electrode RME1 and a second electrode RME2, a first insulating layer PAS1, a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a fourth light emitting element ED4, a bank layer BNL, a second insulating layer PAS2, a first contact electrode CTE1, a second contact electrode CTE2, a third contact electrode CTE3, a fourth contact electrode CTE4, and a fifth contact electrode CTE5, and a third insulating layer PAS3.

The bank layer BNL may define a first light emitting area EMA1, a second light emitting area EMA2, and a third light emitting area EMA3. The light emitting element ED of the first sub-pixel SP1 may be arranged in the first light emitting area EMA1, the light emitting element ED of the second sub-pixel SP2 may be arranged in the second light emitting area EMA2, and the light emitting element ED of the third sub-pixel SP3 may be arranged in the third light emitting area EMA3. FIG8 schematically shows a cross-sectional view of the first light emitting area EMA1.

The first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The first bank pattern BP1 may be arranged between the second bank pattern BP2 and the third bank pattern BP3. The second bank pattern BP2 may be arranged on the left side of the first bank pattern BP1, and the third bank pattern BP3 may be arranged on the right side of the first bank pattern BP1. Each of the first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3 may protrude in an upper direction on the via layer VIA. Each of the first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3 may have an inclined side surface. A plurality of first light emitting elements ED1 and a second light emitting element ED2 of the first sub-pixel SP1 may be arranged between the first bank pattern BP1 and the second bank pattern BP2. A plurality of third light emitting elements ED3 and a fourth light emitting element ED4 of the first sub-pixel SP1 may be arranged between the first bank pattern BP1 and the third bank pattern BP3. The first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3 may be arranged in an island pattern on the entire surface of the display area DA.

The first electrode RME1 and the second electrode RME2 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in the fourth metal layer MTL4. The maximum width of the second electrode RME2 in the second direction DR2 may be greater than the maximum width of the first electrode RME1 in the second direction DR2, but is not limited thereto. The fourth metal layer MTL4 may be arranged on the via layer VIA and the first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3. The first electrode RME1 and the second electrode RME2 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may extend along the first direction DR1. The first electrode RME1 of the first sub-pixel SP1 may be arranged between the second electrode RME2 of the first sub-pixel SP1 and the second electrode RME2 of the second sub-pixel SP2. The first electrode RME1 of the second sub-pixel SP2 may be arranged between the second electrode RME2 of the second sub-pixel SP2 and the second electrode RME2 of the third sub-pixel SP3. The first electrode RME1 of the third sub-pixel SP3 may be arranged on the right side of the second electrode RME2 of the third sub-pixel SP3.

Each of the first electrode RME1 and the second electrode RME2 may cover the upper surface and the inclined side surface of one of the first bank pattern BP1, the second bank pattern BP2, and the third bank pattern BP3. The first electrode RME1 and the second electrode RME2 may be reflective electrodes. The fourth metal layer MTL4 may be formed as a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu). The fourth metal layer MTL4 may include at least one layer containing a substance with high reflectivity. Therefore, each of the first electrode RME1 and the second electrode RME2 may reflect the light emitted from the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 to the upper direction.

The first electrode RME1 and the second electrode RME2 may be alignment electrodes for aligning the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element ED4 during the manufacturing process of the display device 10. The plurality of first electrodes RME1 may be connected to the horizontal voltage line HVDL of the third metal layer MTL3 through the plurality of fifth through holes CNT5. The first electrode RME1 may receive a driving voltage or a high potential voltage from the horizontal voltage line HVDL. The plurality of second electrodes RME2 may be connected to the second voltage line VSL of the third metal layer MTL3 through the plurality of sixth through holes CNT6. The second electrode RME2 may receive a low potential voltage from the second voltage line VSL.

A plurality of light emitting elements ED may be aligned between the first electrode RME1 and the second electrode RME2. A plurality of light emitting elements ED may be arranged in a light emitting element region EDA. A plurality of first light emitting elements ED1 may be arranged in the first light emitting element region EDA1, a plurality of second light emitting elements ED2 may be arranged in the second light emitting element region EDA2, a plurality of third light emitting elements ED3 may be arranged in the third light emitting element region EDA3, and a plurality of fourth light emitting elements ED4 may be arranged in the fourth light emitting element region EDA4. The first light emitting element region EDA1 and the second light emitting element region EDA2 may be arranged between the first electrode RME1 of the first sub-pixel SP1 and the second electrode RME2 of the first sub-pixel SP1. The third light emitting element region EDA3 and the fourth light emitting element region EDA4 may be arranged between the first electrode RME1 of the first sub-pixel SP1 and the second electrode RME2 of the second sub-pixel SP2. The first insulating layer PAS1 may cover the first electrode RME1 and the second electrode RME2. The first insulating layer PAS1 may include an inorganic film. The first light emitting element ED1 , the second light emitting element ED2 , the third light emitting element ED3 , and the fourth light emitting element ED4 may be insulated from the first electrode RME1 and the second electrode RME2 by the first insulating layer PAS1 .

Each of the first electrode RME1 and the second electrode RME2 may receive an alignment signal, and an electric field may be formed between the first electrode RME1 and the second electrode RME2. For example, a plurality of first light-emitting elements ED1, a second light-emitting element ED2, a third light-emitting element ED3, and a fourth light-emitting element ED4 may be sprayed onto the first electrode RME1 and the second electrode RME2 by an inkjet printing process, and a plurality of first light-emitting elements ED1, a second light-emitting element ED2, a third light-emitting element ED3, and a fourth light-emitting element ED4 dispersed in the ink may be aligned by receiving a dielectrophoresis force by means of an electric field formed between the first electrode RME1 and the second electrode RME2. Therefore, a plurality of first light-emitting elements ED1, a second light-emitting element ED2, a third light-emitting element ED3, and a fourth light-emitting element ED4 may be aligned along a first direction DR1 between the first electrode RME1 and the second electrode RME2.

The first contact electrode CTE1, the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5 of each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be arranged in the fifth metal layer MTL5. The first contact electrode CTE1, the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5 may be transparent electrodes. For example, the fifth metal layer MTL5 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. The fifth metal layer MTL5 may have a stacked structure such as ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO, but is not limited thereto.

The second insulating layer PAS2 may be arranged on the bank layer BNL, the first insulating layer PAS1, and the light emitting element ED. The third insulating layer PAS3 may cover the second insulating layer PAS2, the first contact electrode CTE1, the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5. The second insulating layer PAS2 and the third insulating layer PAS3 may include an inorganic film. The second insulating layer PAS2 and the third insulating layer PAS3 may insulate each of the first contact electrode CTE1, the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5. Each of the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5 may include a gap arranged in the center, but is not limited thereto.

The first contact electrode CTE1 of the first sub-pixel SP1 may be disposed on the first electrode RME1 of the first sub-pixel SP1 and may be connected to the first anode connection electrode ANE1 of the third metal layer MTL3 through the first through hole CNT1. The first contact electrode CTE1 may be connected between the first anode connection electrode ANE1 and one end of the plurality of first light emitting elements ED1. The first contact electrode CTE1 may receive a driving current through the first transistor ST1 of FIG. 4. The first contact electrode CTE1 may supply a driving current to the plurality of first light emitting elements ED1 of the first sub-pixel SP1. The first contact electrode CTE1 may correspond to an anode electrode of the plurality of first light emitting elements ED1, but is not limited thereto.

The second contact electrode CTE2 may be insulated from the first electrode RME1 and the second electrode RME2. A first portion of the second contact electrode CTE2 may be disposed on the second electrode RME2 of the first subpixel SP1 and extend along the first direction DR1. A second portion of the second contact electrode CTE2 may extend from a lower side of the first portion and may be disposed on the first electrode RME1 of the first subpixel SP1.

The second contact electrode CTE2 may be connected between the other end of the plurality of first light emitting elements ED1 and one end of the plurality of second light emitting elements ED2. The second contact electrode CTE2 may correspond to the third node N3 of FIG. 4. The second contact electrode CTE2 may correspond to the cathode electrode of the plurality of first light emitting elements ED1, but is not limited thereto. The second contact electrode CTE2 may correspond to the anode electrode of the plurality of second light emitting elements ED2, but is not limited thereto.

The third contact electrode CTE3 may be insulated from the first electrode RME1 and the second electrode RME2. A first portion of the third contact electrode CTE3 may be disposed on the second electrode RME2 of the first subpixel SP1 and extend along the first direction DR1. A second portion of the third contact electrode CTE3 may be disposed on the first electrode RME1 of the first subpixel SP1 and may be disposed on the right side of the first portion.

The third contact electrode CTE3 may be connected between the other ends of the plurality of second light emitting elements ED2 and one ends of the plurality of third light emitting elements ED3. The third contact electrode CTE3 may correspond to the fourth node N4 of FIG. 4. The third contact electrode CTE3 may correspond to the cathode electrodes of the plurality of second light emitting elements ED2, but is not limited thereto. The third contact electrode CTE3 may correspond to the anode electrodes of the plurality of third light emitting elements ED3, but is not limited thereto.

The fourth contact electrode CTE4 may be insulated from the first electrode RME1 and the second electrode RME2. A first portion of the fourth contact electrode CTE4 may be disposed on the second electrode RME2 of the second sub-pixel SP2 and extend along the first direction DR1. A second portion of the fourth contact electrode CTE4 may extend from an upper side of the first portion and may be disposed on the first electrode RME1 of the first sub-pixel SP1.

The fourth contact electrode CTE4 may be connected between the other end of the plurality of third light emitting elements ED3 and one end of the plurality of fourth light emitting elements ED4. The fourth contact electrode CTE4 may correspond to the fifth node N5 of FIG. 4. The fourth contact electrode CTE4 may correspond to the cathode electrode of the plurality of third light emitting elements ED3, but is not limited thereto. The fourth contact electrode CTE4 may correspond to the anode electrode of the plurality of fourth light emitting elements ED4, but is not limited thereto.

The fifth contact electrode CTE5 may be connected between the other ends of the plurality of fourth light emitting elements ED4 and the second voltage line VSL. The fifth contact electrode CTE5 may be arranged on the second electrode RME2 of the second sub-pixel SP2 and extend along the first direction DR1. The fifth contact electrode CTE5 may be connected to the second voltage line VSL of the third metal layer MTL3 through the fourth through hole CNT4. The fifth contact electrode CTE5 may correspond to the cathode electrode of the plurality of fourth light emitting elements ED4, but is not limited thereto. The fifth contact electrode CTE5 may receive a low potential voltage through the second voltage line VSL. The fifth contact electrode CTE5 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be formed as one body, but is not limited thereto.

The first contact electrode CTE1 of the second sub-pixel SP2 may be arranged on the first electrode RME1 of the second sub-pixel SP2, and may be connected to the pixel circuit of the second sub-pixel SP2 through the second through hole CNT2. The first contact electrode CTE1 may be connected between the pixel circuit of the second sub-pixel SP2 and one end of the plurality of first light-emitting elements ED1. The first contact electrode CTE1 may receive a driving current passing through the first transistor ST1 of the second sub-pixel SP2. The first contact electrode CTE1 may supply a driving current to the plurality of first light-emitting elements ED1 of the second sub-pixel SP2.

The first contact electrode CTE1 of the third sub-pixel SP3 may be arranged on the first electrode RME1 of the third sub-pixel SP3, and may be connected to the pixel circuit of the third sub-pixel SP3 through the third through hole CNT3. The first contact electrode CTE1 may be connected between the pixel circuit of the third sub-pixel SP3 and one end of the plurality of first light-emitting elements ED1. The first contact electrode CTE1 may receive a driving current passing through the first transistor ST1 of the third sub-pixel SP3. The first contact electrode CTE1 may supply a driving current to the plurality of first light-emitting elements ED1 of the third sub-pixel SP3.

FIG. 9 is a schematic diagram of a light emitting element according to an embodiment.

9 , the light emitting element ED may be a light emitting diode, and specifically, the light emitting element ED may be an inorganic light emitting diode having a size in nanometer to micrometer units and formed of inorganic substances. If an electric field is formed along a specific direction between two electrodes facing each other, the light emitting element ED may be aligned between the two electrodes forming polarity.

According to an embodiment, the light emitting element ED may have a shape extending in one direction. The light emitting element ED may have a shape such as a cylinder, a rod, a wire, a tube, etc. However, the form of the light emitting element ED is not limited thereto, and the light emitting element ED may have a polygonal column shape such as a cube, a rectangular parallelepiped, a hexagonal column, or a shape extending in one direction and having an outer surface partially inclined, etc.

The light emitting element ED may include a semiconductor layer doped with a dopant of any conductivity type (e.g., p-type or n-type). The semiconductor layer may emit light of a specific wavelength band by transmitting an electrical signal applied from an external power source. The light emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor material having a chemical formula of _{AlxGayIn1 -xyN (} 0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 31 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped into the first semiconductor layer 31 may be Si, Ge, Sn, Se, etc.

The second semiconductor layer 32 is arranged on the first semiconductor layer 31 via the light emitting layer 36. The second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 may include a semiconductor material having a chemical formula of _{AlxGayIn1 -xyN (} 0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 32 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped into the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, etc.

In addition, the first semiconductor layer 31 and the second semiconductor layer 32 are shown in the drawings as being constituted by one layer, but are not limited thereto. Depending on the material of the light-emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include a greater number of layers (e.g., a clad layer or a tensile strain barrier reducing layer (TSBR: Tensile strain barrier reducing) layer). For example, the light-emitting element ED may also include other semiconductor layers arranged between the first semiconductor layer 31 and the light-emitting layer 36 or between the second semiconductor layer 32 and the light-emitting layer 36. The semiconductor layer arranged between the first semiconductor layer 31 and the light-emitting layer 36 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN, and superlattices doped with n-type dopants, and the semiconductor layer arranged between the second semiconductor layer 32 and the light-emitting layer 36 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type dopants.

The light emitting layer 36 is arranged between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material of a single quantum well structure or a multi-quantum well structure. In the case where the light emitting layer 36 includes a material of a multi-quantum well structure, it may also be a structure in which a plurality of quantum layers (Quantum layer) and a well layer (Well layer) are alternately stacked with each other. The light emitting layer 36 may emit light by combining electron-hole pairs according to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, in the case where the light emitting layer 36 is a structure in which quantum layers and well layers are alternately stacked as a multi-quantum well structure, the quantum layer may include materials such as AlGaN or AlGaInN, and the well layer may include materials such as GaN or AlInN.

The light emitting layer 36 may be a structure in which semiconductor materials of a type with a large energy band gap and semiconductor materials of a type with a small energy band gap are alternately stacked, or may include different semiconductor materials of group III to group V according to the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to the light of the blue wavelength band, and may also emit light of the red and green wavelength bands according to the circumstances.

The electrode layer 37 may be an Ohmic connection electrode. However, it is not limited thereto and may also be a Schottky connection electrode. The light emitting element ED may include at least one electrode layer 37. The light emitting element ED may include more than one electrode layer 37, but it is not limited thereto and the electrode layer 37 may also be omitted.

When the light emitting element ED is electrically connected to an electrode or a connection electrode in the display device 10, the electrode layer 37 can reduce the resistance between the light emitting element ED and the electrode or the connection electrode. The electrode layer 37 may include a metal having conductivity. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

The insulating film 38 is arranged to surround the outer surfaces of the plurality of semiconductor layers and the electrode layer. For example, the insulating film 38 may be arranged to surround at least the outer surface of the light emitting layer 36, and may be formed to expose both ends in the length direction of the light emitting element ED. In addition, in the cross-section, in the region adjacent to at least one end of the light emitting element ED, the upper surface of the insulating film 38 may also be formed to be smooth.

The insulating film 38 may include at least one of a substance having insulating properties (e.g., silicon oxide ( _SiOx ), silicon nitride ( _SiNx ), silicon oxynitride ( _SiOxNy ), aluminum nitride ( _AlNx ), aluminum oxide ( _AlOx ), zirconium oxide ( _{ZrOx )} , hafnium oxide ( _HfOx ), and titanium oxide ( _TiOx )). The drawings illustrate a case where the insulating film 38 is formed as a single layer, but are not limited thereto. In some embodiments, the insulating film 38 may also be formed as a multilayer structure in which a plurality of layers are stacked.

The insulating film 38 can perform the function of protecting the semiconductor layer and the electrode layer of the light emitting element ED. The insulating film 38 can prevent an electrical short circuit that may occur in the light emitting layer 36 when directly contacting the electrode that transmits an electrical signal to the light emitting element ED. In addition, the insulating film 38 can prevent the light emitting efficiency of the light emitting element ED from being reduced.

Furthermore, the outer surface of the insulating film 38 may also be subjected to surface treatment. The light emitting elements ED may be sprayed onto the electrodes in a dispersed state in a predetermined ink and aligned. Here, in order to keep the light emitting elements ED dispersed and not aggregated with other adjacent light emitting elements ED in the ink, the surface of the insulating film 38 may be subjected to hydrophobic or hydrophilic treatment.

FIG. 10 is a plan view showing an arrangement of a pad region of a display device and wirings arranged around the pad region according to an embodiment.

10 , a display device 10 according to an embodiment may include a plurality of wirings DL, MBL, VPL arranged in a non-display area NDA and a plurality of pads DP1, DP2 arranged in a pad area PDA. A portion of the plurality of wirings DL, MBL, VPL may be arranged to extend to the display area DA, and another portion may be arranged in the non-display area NDA. For example, a data line DL among the plurality of wirings may extend from the pad area PDA in a first direction DR1 and also be arranged in the display area DA. The data line DL may be electrically connected to a plurality of first pads DP1 in the pad area PDA.

The connection wiring MBL among the plurality of wirings may be arranged to extend in the first direction DR1 in the pad area PDA and be partially bent to extend in the non-display area NDA. The plurality of connection wirings MBL may extend in the first direction DR1 in the non-display area NDA located on both sides of the display area DA in the second direction DR2. The plurality of connection wirings MBL may be electrically connected to the second pad DP2 in the pad area PDA, and may be electrically connected to the gate driving part 260 arranged in the non-display area NDA. In the display device 10, the plurality of data lines DL may be inner wirings arranged in the display area DA, and the connection wiring MBL may be outer wirings arranged in the non-display area NDA. The first pad DP1 connected to the data line DL as the inner wiring may be the inner pad, and the second pad DP2 connected to the connection wiring MBL as the outer wiring may be the outer pad.

The power connection wiring VPL among the plurality of wirings may be arranged to be partially arranged in the pad area PDA and include portions extending in the first direction DR1 and the second direction DR2 to surround the display area DA. The power connection wiring VPL may be electrically connected to a plurality of voltage lines arranged in the display area DA. Although not shown in the drawings, the power connection wiring VPL may also be electrically connected to other power pads in the pad area PDA and may transmit a power voltage to the voltage lines.

A plurality of pads DP1, DP2 may be arranged in a pad area PDA arranged on the lower side of the display area DA as the other side of the first direction DR1 and surrounded by the non-display area NDA. The plurality of pads DP1, DP2 may include a first pad DP1 as an inner pad arranged relatively on the inner side and a second pad DP2 as an outer pad arranged on the outer side than the first pad DP1. In the pad area PDA, a plurality of second pads DP2, a first pad DP1, and other plurality of second pads DP2 may be arranged from the left side of the display device 10 as the other side of the second direction DR2 toward the right side. The first pad DP1 may be electrically connected to a plurality of data lines DL arranged in the display area DA, and the second pad DP2 may be electrically connected to a plurality of connection wirings MBL arranged in the non-display area NDA. The plurality of first pads DP1 may be arranged corresponding to the data lines DL. However, the intervals between the first pads DP1 may be different from the intervals between the data lines DL. Similarly, the plurality of second pads DP2 may be arranged corresponding to the plurality of connection wirings MBL. The intervals between the second pads DP2 may be different from the intervals between the connection wirings MBL.

In the drawings, a part of the power connection wiring VPL is shown to be arranged between the first pad DP1 and the second pad DP2, but their arrangement relationship is not limited to this. The arrangement relationship of the first pad DP1, the second pad DP2 and the power connection wiring VPL can be designed to be different from the arrangement relationship illustrated in the drawings. A flexible film 210 (FIG. 2) can be arranged on the plurality of pads DP1 and DP2, and the pads DP1 and DP2 can be electrically connected to the display driving unit 220 (FIG. 2) and the circuit board 230 (FIG. 2).

The plurality of pads DP1, DP2 and the plurality of wirings DL, MBL, VPL may be arranged symmetrically to each other with reference to a virtual line that crosses the center of the display device 10 along the first direction DR1. Among the plurality of pads DP1, DP2 and the plurality of wirings DL, MBL, VPL, the pads and wirings arranged on both sides in the second direction DR2 with reference to the virtual line may have a symmetrical structure to each other. The arrangement order of the wirings arranged on the left and right sides of the center of the display device 10 from the center to both sides in the second direction DR2 may be the same as each other. For example, the wirings adjacent to the center in the left side of the display device 10 and the wirings adjacent to the center in the right side of the display device 10 may be the same as each other, and the wirings arranged on the left side of the display device 10 may be the same as the wirings arranged on the right side of the display device 10. However, it is not limited thereto.

Fig. 11 is an enlarged view of the A portion of Fig. 10. Fig. 12 is a cross-sectional view taken along the line XII-XII' of Fig. 11. Fig. 13 is a cross-sectional view taken along the line XIII-XIII' of Fig. 11.

Fig. 11 is an enlarged plan view showing a first pad DP1 of the plurality of pads DP1 and DP2. Fig. 12 shows a cross section across two adjacent first pads DP1 shown in Fig. 11 along the second direction DR2. Fig. 13 shows a cross section across the first pad DP1 shown in Fig. 11 along the first direction DR1.

11 to 13, a plurality of pads DP1 and DP2 of a display device 10 according to an embodiment may include a pad base layer DPE1 and a pad upper layer DPE2 disposed on the pad base layer DPE1. The pad base layer DPE1 and the pad upper layer DPE2 may be disposed to overlap each other on the data line DL in the pad area PDA, respectively. The pad base layer DPE1 and the pad upper layer DPE2 may have a shape extending in the first direction DR1, and the overall shape of the first pad DP1 may have a shape extending in the first direction DR1.

In the pad area PDA, in addition to the data line DL, the pad base layer DPE1 and the pad upper layer DPE2, a plurality of layers arranged therebetween may be arranged. For example, a buffer layer BF arranged on the data line DL, an interlayer insulating layer ILD arranged on the buffer layer BF, a protective layer PV arranged on the interlayer insulating layer ILD, and a second insulating layer PAS2 on the protective layer PV may be arranged in the pad area PDA. Unlike the display area DA, the gate insulating layer GI, the via layer VIA and the first insulating layer PAS1 are not arranged in the pad area PDA, so a step difference may be formed between the display area DA and the pad area PDA.

The data line DL may be arranged in the same layer as the first metal layer MTL1 arranged in the display area DA. For example, the data line DL may be arranged on the substrate SUB and may be arranged in the same layer as other wirings or lines of the first metal layer MTL1 and include the same material. The pad base layer DPE1 may be arranged in the same layer as the third metal layer MTL3 arranged in the display area DA. For example, the pad base layer DPE1 may be arranged on the interlayer insulating layer ILD. The pad upper layer DPE2 may be arranged in the same layer as the fifth metal layer MTL5 arranged in the display area DA. For example, the pad upper layer DPE2 may be arranged on the second insulating layer PAS2. The pad base layer DPE1 may be arranged in the same layer as the voltage line arranged in the display area DA and include the same material. The pad upper layer DPE2 may be arranged in the same layer as the first contact electrode CTE1, the second contact electrode CTE2, the third contact electrode CTE3, the fourth contact electrode CTE4, and the fifth contact electrode CTE5 arranged in the display area DA and include the same material. Although FIGS. 11 to 13 illustrate the structure of the first pad DP1, the second pad DP2 may also have substantially the same structure.

According to an embodiment, in the pads DP1 and DP2 of the display device 10, the pad base layer DPE1 may be electrically connected to the wiring of the first metal layer MTL1, and the pad upper layer DPE2 may be electrically connected to the pad base layer DPE1. For example, the pad base layer DPE1 may be electrically connected to the first metal layer MTL1 through the first contact hole CT1 and the second contact hole CT2 penetrating the buffer layer BF and the interlayer insulating layer ILD. The pad upper layer DPE2 may be electrically connected to the pad base layer DPE1 through the pad contact hole CTA penetrating the protective layer PV and the second insulating layer PAS2.

As described above, the flexible film 210 may be arranged on the pads DP1 and DP2, and the conductive balls may be arranged between the flexible film 210 and the pads DP1 and DP2 so that they may be electrically connected to each other. The conductive balls may be arranged on the pad upper layer DPE2 of the pads DP1 and DP2, and the pad upper layer DPE2 may have a step difference based on the position due to the layer arranged thereunder. For example, the portion of the pad upper layer DPE2 arranged on the second insulating layer PAS2 may be located at a higher position than the portion contacting the pad base layer DPE1 through the pad contact hole CTA. The larger the step difference based on the position of the pad upper layer DPE2, the less smooth the connection between the conductive balls and the pads DP1 and DP2 may be. The display device 10 according to an embodiment may have a structure capable of minimizing the step difference of the area where the pads DP1 and DP2 are arranged in the pad area PDA, and the poor connection of the flexible film 210 arranged on the pads DP1 and DP2 due to the step difference may be reduced.

For example, a plurality of first pads DP1 may contact the data lines DL arranged at the lower part thereof in the first contact holes CT1 and the second contact holes CT2 arranged at both sides in the first direction DR1 based on the pad contact hole CTA. The data lines DL of the first metal layer MTL1 electrically connected to the first pad DP1 may extend along the first direction DR1 and be arranged in a manner that overlaps all of the first contact holes CT1, the second contact holes CT2, and the pad contact holes CTA, and the step difference between the portion of the first pad DP1 where the first contact holes CT1 or the second contact holes CT2 are formed and the portion where the pad contact holes CTA are formed may be minimized. Since the data lines DL of the first metal layer MTL1 are arranged to overlap the pad contact holes CTA, the step difference may be reduced in the entire first pad DP1, and the entire first pad DP1 may have a structure in which the first metal layer MTL1 and the third metal layer MTL3 are overlapped and arranged.

Furthermore, according to one embodiment, the width of the data line DL and the pad upper layer DPE2 of the first metal layer MTL1 may be greater than the width of the pad base layer DPE1 of the pads DP1 and DP2. Since the data line DL has a greater width (D1×2) than the pad base layer DPE1, it is possible to prevent the pad base layer DPE1 from having a step difference in the width direction. Considering the tolerance occurring in the formation process, the pad upper layer DPE2 may have a greater width (D2×2) than the pad base layer DPE1. In some embodiments, the width of the data line DL may be greater than the width of the pad upper layer DPE2, and the step difference in the width direction of the pad upper layer DPE2 may also be reduced by the data line DL. In the pad area PDA, the interval between the data lines DL of the first metal layer MTL1 adjacent in the second direction DR2 may be smaller than the interval between the pad base layers DPE1 of the first pad DP1 adjacent in the second direction DR2, which can ensure that the first pad DP1 can be formed in sufficient space on the data line DL.

In the pad area PDA, the first pad DP1 may extend in the first direction DR1, and the data line DL may also extend in the first direction DR1 and overlap with the first pad DP1. The width difference between the data line DL and the pad base layer DPE1 and the pad upper layer DPE2 of the first pad DP1 may remain constant. As described later, the width of the first pad DP1 may differ depending on the position, and the pad base layer DPE1, the pad upper layer DPE2, and the data line DL may have a shape that constantly maintains the width difference and the width varies depending on the position. A more detailed description will be given later with reference to other drawings.

In the display device 10, since a large number of pads DP1 and DP2 are densely arranged in the pad area PDA, precise alignment between the pads DP1 and DP2 and the flexible film 210 may be required when attaching the flexible film 210 on the pads DP1 and DP2. The display device 10 according to an embodiment can be used as an alignment mark in the process of attaching the pads DP1 and DP2 and the flexible film 210 by adjusting the line widths of the pads DP1 and DP2 and the wiring of the first metal layer MTL1 arranged in the pad area PDA.

FIG. 14 is an enlarged view showing a portion of a pad portion of a display device according to an embodiment.

14, in the display device 10 according to an embodiment, the plurality of pads DP1 and DP2 may include a first portion P1 in which a pad contact hole CTA is formed, a second portion P2 in which contact holes CT1 and CT2 are formed, and a third portion P3 between the first portion P1 and the second portion P2. In the pads DP1 and DP2, the widths of the first portion P1, the second portion P2, and the third portion P3 measured in the second direction DR2 may be different from each other, and the second portion P2 and the third portion P3 whose widths vary with respect to the first portion P1 may respectively perform the role of alignment marks.

The width W1 of the data line DL overlapping the first portion P1 of the pads DP1 and DP2 may be greater than the widths W2 and W3 of the data line DL overlapping the second portion P2 and the third portion P3. The width W2 of the data line DL overlapping the second portion P2 of the pads DP1 and DP2 may be greater than the width W3 of the data line DL of the portion overlapping the third portion P3. The pads DP1 and DP2 are based on the first portion P1 formed with the pad contact hole CTA, and the third portion P3 with a narrowed width is respectively provided on the upper and lower sides thereof, and the second portion P2 with a widened width is respectively provided on the upper and lower sides of the third portion P3. The wiring of the first metal layer MTL1 overlapping the pads DP1 and DP2 may also include a portion whose line width varies according to the position, similarly to the pads DP1 and DP2. The pads DP1 and DP2 have a shape whose width varies according to the position, but the width difference of the data line DL, the pad base layer DPE1, and the pad upper layer DPE2 may be kept constant in the first portion P1, the second portion P2, and the third portion P3.

In the process of attaching the flexible film 210 to the plurality of pads DP1 and DP2, the positions of the second portion P2 and the third portion P3 whose widths vary with respect to the first portion P1 can be sensed to accurately align the attachment positions of the first portion P1 or the conductive ball and the flexible film 210. Accordingly, defects that occur during the process of attaching the flexible film in the manufacturing process of the display device 10 can be reduced.

In the above, the connection structure between the first pad DP1 arranged in the pad area PDA and the data line DL in the first metal layer MTL1 is described. The connection structure between the second pad DP2 as another pad arranged in the pad area PDA and the connection wiring MBL may also be the same as that described with reference to Figures 11 to 14. However, in some embodiments, the connection wiring MBL may be composed of more than one layer. The overlapping structure between the wirings in the portion of the connection wiring MBL arranged in the pad area PDA and the portion extending from the portion and arranged in the non-display area NDA may be partially different. In the following, the arrangement and connection structure of the second pad DP2 and the connection wiring MBL are described.

Fig. 15 is an enlarged view of the B portion of Fig. 10. Fig. 16 is a cross-sectional view taken along the line XVI-XVI' of Fig. 15. Fig. 17 is a cross-sectional view taken along the line XVII-XVII' of Fig. 15.

Fig. 15 is an enlarged plan view showing the second pad DP2 and the connection wiring MBL among the plurality of pads DP1 and DP2. Fig. 16 shows a cross section along the second direction DR2 across two adjacent connection wirings MBL shown in Fig. 15, and Fig. 17 shows a cross section along the first direction DR1 across the second pad DP2 and the connection wiring MBL shown in Fig. 15.

15 to 17, the display device 10 according to an embodiment may include a plurality of connection wirings MBL1, MBL2, MBL3 arranged in metal layers MTL1, MTL2, MTL3 different from each other. The plurality of connection wirings MBL1, MBL2, MBL3 may include a first connection wiring MBL1 arranged in the first metal layer MTL1, a second connection wiring MBL2 arranged in the second metal layer MTL2, and a third connection wiring MBL3 arranged in the third metal layer MTL3. The first connection wiring MBL1, the second connection wiring MBL2, and the third connection wiring MBL3 may extend overlapping each other in the non-display area NDA, and may be arranged on both sides of the display area DA in the second direction DR2. Among them, the first connection wiring MBL1 and the third connection wiring MBL3 may extend from the pad area PDA respectively and also be arranged in the non-display area NDA, and the second connection wiring MBL2 may be arranged only in the non-display area NDA. The second connection wiring MBL2 may not overlap with the second pad DP2.

The first connection wiring MBL1 may be arranged to extend from the pad area PDA similarly to the data line DL and to overlap with the second pad DP2 in the pad area PDA. Although not shown in the drawings, the arrangement relationship between the first pad DP1 and the data line DL illustrated in FIGS. 11 to 13 may be the same as the arrangement relationship between the second pad DP2 and the first connection wiring MBL1. For example, in the pad area PDA, the pad base layer DPE1 of the second pad DP2 may contact the first connection wiring MBL1 of the first metal layer MTL1 through the contact holes CT1 and CT2. The first connection wiring MBL1 may be arranged to overlap with the pad contact hole CTA that also contacts the pad upper layer DPE2 and the pad base layer DPE1 of the second pad DP2, and the step difference based on the position of the second pad DP2 may be reduced. Furthermore, the line width of the first connection wiring MBL1 may be formed to be greater than the line width of the pad base layer DPE1 and the pad upper layer DPE2 of the second pad DP2. The description of this is the same as that made with reference to FIGS. 11 to 13.

The third connection wiring MBL3 may be arranged on the third metal layer MTL3 and connected to the pad base layer DPE1 of the second pad DP2. The third connection wiring MBL3 may be formed as an integral body with the pad base layer DPE1 and may be arranged to extend from the pad area PDA to the non-display area NDA. The portion of the second pad DP2 where the first contact hole CT1 and the second contact hole CT2 are formed may have a structure in which the first connection wiring MBL1 and the pad base layer DPE1 or the third connection wiring MBL3 are arranged to overlap each other.

The second connection wiring MBL2 may be arranged to overlap with the first connection wiring MBL1 and the third connection wiring MBL3 in the non-display area NDA. The second connection wiring MBL2 may be arranged in the same layer as the second metal layer MTL2 of the display area DA and include the same material. The second connection wiring MBL2 may be arranged on the buffer layer BF and may be arranged between the first connection wiring MBL1 and the third connection wiring MBL3. The third connection wiring MBL3 may be electrically connected to the second connection wiring MBL2 in the non-display area NDA through a third contact hole CT3 penetrating the interlayer insulating layer ILD.

The display device 10 has a structure in which the first connection wiring MBL1 of the first metal layer MTL1 and the third connection wiring MBL3 of the third metal layer MTL3 overlap each other at the first contact hole CT1 or the second contact hole CT2 in the pad area PDA, and can have a structure in which the first connection wiring MBL1, the second connection wiring MBL2 and the third connection wiring MBL3 of the first metal layer MTL1, the second metal layer MTL2 and the third metal layer MTL3 overlap each other at the third contact hole CT3 in the non-display area NDA. Since the connection wiring MBL is composed of a plurality of wirings arranged in different metal layers, it can be arranged around the display area DA while reducing the voltage drop caused by the increase in resistance as it moves away from the pad area PDA.

In addition, although the via layer VIA is not arranged in the pad area PDA, the via layer VIA may be arranged in the non-display area NDA located inside the pad area PDA, and the second insulating layer PAS2 may be arranged on the upper portion of the via layer VIA. The first contact hole CT1 for contacting the second pad DP2 with the first connection wiring MBL1 may not overlap with the via layer VIA, and the third contact hole CT3 for contacting the third connection wiring MBL3 with the second connection wiring MBL2 may overlap with the via layer VIA.

In the display device 10 according to an embodiment, the wiring arranged in the pad area PDA may be arranged to completely overlap with the pads DP1 and DP2, and the step difference that may be generated due to the wiring arranged under the pads DP1 and DP2 may be minimized. Also, in the display device 10, the connection wiring MBL arranged in the pad area PDA and the non-display area NDA is configured using a plurality of layers, and may have a structure in which wirings arranged in different layers overlap in the pad area PDA and the non-display area NDA.

Hereinafter, another embodiment of the display device 10 will be described with reference to other drawings.

FIG. 18 is a plan view showing an arrangement of a pad region of a display device and wirings arranged around the pad region according to another embodiment.

18 , the display device 10_1 according to an embodiment further includes a plurality of third pads DP3 arranged in the pad area PDA, and the third pads DP3 may be electrically connected to the plurality of scan lines SL arranged in the display area DA. Unlike the display device 10 of FIG. 2 , in the display device 10_1, a portion of the gate driving part 260 arranged on both sides of the display area DA in the second direction DR2 may be arranged on the circuit board 230 connected through the flexible film 210. Accordingly, the third pads DP3 electrically connected to the scan lines SL may also be arranged in the pad area PDA.

The third pad DP3 may have substantially the same structure as the first pad DP1, and may be arranged non-parallel to the first pad DP1 in the second direction DR2. For example, in the pad area PDA, the first pad DP1 and the second pad DP2 may be arranged as pads arranged in the first pad row, and a plurality of third pads DP3 may be arranged as pads arranged in the second pad row located on the other side of the first pad row in the first direction DR1. In the first pad row, the first pad DP1 and the second pad DP2 may be arranged spaced apart in the second direction DR2, and in the second pad row, the third pad DP3 may be arranged spaced apart in the second direction DR2.

A plurality of scan lines SL may be arranged extending from the display area DA along the first direction DR1, and may extend to the pad area PDA and be electrically connected to the third pads DP3, respectively. The scan lines SL and the data lines DL may be alternately arranged along the second direction DR2, and the scan lines SL may extend along the first direction DR1 in the space between the first pads DP1 in the pad area PDA. Accordingly, in the display area DA, the data lines DL and the scan lines SL are alternately arranged with each other along the second direction DR2 and in parallel with each other, whereas, in the pad area PDA, the first pads DP1 connected to the data lines DL and the third pads DP3 connected to the scan lines SL may not be arranged in parallel with each other.

Fig. 19 is an enlarged view of the C portion of Fig. 18. Fig. 20 is an enlarged view of the D portion of Fig. 18. Fig. 21 is a cross-sectional view taken along the line XXI-XXI' of Fig. 19. Fig. 22 is a cross-sectional view taken along the line XXII-XXII' of Fig. 20.

19 shows an enlarged view of a region where a plurality of first pads DP1 and scan lines SL are arranged, and FIG20 shows an enlarged view of a region where a plurality of third pads DP3 are arranged. FIG21 shows a cross section across the first pads DP1 and scan lines SL along the second direction DR2, and FIG22 shows a cross section across the third pads DP3 along the second direction DR2.

19 to 22, each of the first pad DP1 and the third pad DP3 may include a pad base layer DPE1 and a pad upper layer DPE2 and have a structure stacked on each other. Since the cross-sectional structure and the planar structure of the first pad DP1 and the third pad DP3 are substantially the same as those described with reference to FIGS. 11 to 13, detailed description thereof is omitted.

A plurality of first pads DP1 may be arranged to overlap the data lines DL, and a scan line SL may be arranged therebetween. The data lines DL and the scan lines SL are arranged on the first metal layer MTL1, respectively, and the first pad DP1 may include a pad base layer DPE1 and a pad upper layer DPE2 arranged on the third metal layer MTL3 and the fifth metal layer MTL5. In the pad area PDA, the intervals between the wirings different from each other arranged on the first metal layer MTL1 may be smaller than the intervals between the first pads DP1.

The pad base layer DPE1 of the third pad DP3 may contact the scan line SL through the fourth contact hole CT4 and the fifth contact hole CT5. The scan line SL may be arranged to also overlap with the fourth contact hole CT4, the fifth contact hole CT5, and the pad contact hole CTA located therebetween, and may completely overlap with the third pad DP3. Since the scan line SL is arranged at the lower portion of the third pad DP3, the step difference due to the lower wiring or the lower layer may be minimized.

The scan line SL may extend in the space between the first pad DP1 or the data line DL in the pad area PDA and be connected to the third pad DP3 of the second pad row. In the display device 10_1, compared with the display device 10 of FIG. 10, a greater number of pads DP1, DP2, DP3 and wirings DL, SL are arranged in the pad area PDA, but the first pad DP1 and the third pad DP3 may be arranged non-parallel along the second direction DR2, thereby ensuring a sufficient separation distance between the pads DP1, DP2, DP3. Accordingly, in the display device 10_1, the wirings DL, SL overlapping the pads DP1, DP2, DP3 may also fully ensure the spacing and width therebetween, and the wirings DL, SL may be arranged to completely overlap the pads DP1, DP2, DP3, thereby minimizing the step difference that may be generated in the pads DP1, DP2, DP3.

The embodiments of the present invention are described above with reference to the accompanying drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and are not restrictive.

Claims (10)

1. A display device, comprising: a display area, a non-display area surrounding the display area, and a pad area arranged at one side of the display area in a first direction and surrounded by the non-display area; a plurality of data lines arranged to extend from the pad area to the display area along the first direction; a plurality of connection wirings arranged to be separated from the data lines and extending from the pad area to both sides of the display area in the non-display area in a second direction intersecting the first direction; and a plurality of pads arranged in the pad region so as to overlap with the data line and the connection wiring, wherein the connection wiring includes: a first connection wiring overlapping the pad and extending along the first direction; a second connection wiring not overlapping the pad and arranged overlapping with the first connection wiring in the non-display area; and a third connection wiring overlapping with the first connection wiring and electrically connected to the pad, In the pad region, the first connection wiring and the third connection wiring are arranged to overlap with each other, and in the non-display region, the first connection wiring, the second connection wiring, and the third connection wiring are arranged to overlap with each other. 2. The display device according to claim 1, characterized in that A plurality of said pads comprises: a plurality of first pads arranged in the pad region to overlap with the data line; and a plurality of second pads arranged in the pad region so as to be spaced apart from the first pads along the second direction and arranged to overlap with the connection wiring, The first connection wiring overlaps with the second pad, the second connection wiring does not overlap with the second pad, and the third connection wiring is electrically connected to the second pad. 3. The display device according to claim 2, characterized in that Each of the first pad and the second pad includes a pad base layer and a pad upper layer disposed on the pad base layer and contacting the pad base layer through a pad contact hole, The pad base layer of each of the first pad and the second pad directly contacts the data line or the first connection wiring through a first contact hole and a second contact hole spaced apart from the pad contact hole along the first direction. 4. The display device according to claim 3, characterized in that The data line overlaps the first contact hole, the pad contact hole, and the second contact hole respectively overlapping the first pad in the pad region. 5. The display device according to claim 3, characterized in that: The first connection wiring overlaps with the first contact hole, the pad contact hole, and the second contact hole respectively, which overlap with the second pad in the pad region. The third connection wiring is directly connected to the pad upper layer of the second pad in the pad region, and is directly in contact with the second connection wiring through a third contact hole formed in a portion overlapping the first connection wiring and the second connection wiring in the non-display region. 6. The display device according to claim 3, characterized in that: The first pad and the second pad each include: a first portion overlapping the pad contact hole; a second portion overlapping the first contact hole or the second contact hole; and The third part is arranged between the first part and the second part, The widths of the first portion, the second portion, and the third portion measured in the second direction are different from each other. 7. The display device according to claim 6, characterized in that: The width of the first portion is greater than the widths of the second portion and the third portion, The width of the third portion is greater than the width of the second portion, The widths of the data line, the pad base layer, and the pad upper layer measured in the second direction are different from each other, In each of the first portion, the second portion, and the third portion, a width difference between the data line, the pad base layer, and the pad upper layer is constant. 8. The display device according to claim 3, characterized in that: The width of the data line measured in the second direction is greater than the width of the first pad measured in the second direction, The width of the pad base layer of the first pad and the second pad measured in the second direction is respectively smaller than the width of the pad upper layer measured in the second direction. 9. The display device according to claim 8, characterized in that: An interval between adjacent data lines in the pad region is smaller than an interval between adjacent first pads. 10. The display device according to claim 2, further comprising: A plurality of scan lines arranged between the data lines and extending from the pad area to the display area; and a plurality of third pads arranged in the pad region to overlap with the scan line, wherein the third pad and the first pad are arranged non-parallel along the second direction, An interval between adjacent first pads in the second direction is greater than an interval between the data line and the scan line.