CN211151943U - Level switching circuit composed of separated elements - Google Patents
Level switching circuit composed of separated elements Download PDFInfo
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- CN211151943U CN211151943U CN201922424129.6U CN201922424129U CN211151943U CN 211151943 U CN211151943 U CN 211151943U CN 201922424129 U CN201922424129 U CN 201922424129U CN 211151943 U CN211151943 U CN 211151943U
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Abstract
The problem that the high level signal that sends in order to solve 1.8V operating voltage's signalling chip can't be discerned by 3.3V operating voltage's signal reception chip, the utility model provides a level conversion circuit that disconnect-type component is constituteed, it includes: the signal sends chip U1, signal reception chip U2, triode Q1, first resistance R1, second resistance R2, electric capacity C1, its characterized in that: an emitter E of the triode Q1 is connected with a transmitting end UART _ TXD of a signal transmitting chip U1, a collector C of the triode Q1 is connected with a receiving end MCU _ RX of a signal receiving chip U2, a second end of the second resistor R2 is connected between the collector C of the triode Q1 and the receiving end MCU _ RX of the signal receiving chip U2, the second resistor R2 is a pull-up resistor, and a base B of the triode Q1 is connected with a power supply VDD _ EXT of 1.8V through a first resistor R1 in series.
Description
Technical Field
The utility model relates to level shift technical field, it is comparatively concrete, involve a level shift circuit that disconnect-type component is constituteed.
Background
In many application circuits, since the working voltage of the chip of the signal sending end is different from the working voltage of the chip of the signal receiving end, the working voltage of the chip of the sending end needs to be processed, so that the working voltage of the chip of the signal receiving end is matched with the working voltage of the chip of the signal receiving end, and thus the signal can be correctly identified. If the working voltages of the signal sending end chip and the signal receiving end chip are different, only two conditions exist, the first condition is that the working voltage of the signal sending end chip is lower than the working voltage of the signal receiving end chip, and the second condition is that the working voltage of the signal sending end chip is higher than the working voltage of the signal receiving end chip.
For the first situation, the working voltage of the signal sending chip is lower than the working voltage of the signal receiving end chip, and if a mode of directly connecting a resistor between the signal sending chip and the signal receiving chip is adopted, the signal sending chip with the lower working voltage is damaged, and the signal of the signal sending chip may not be identified and received by the signal receiving chip. More specifically, the current signal transmitting chips have many working voltages of 1.8V, the signal receiving chips have many working voltages of 3.3V, and usually, the low level identification range of the signal receiving chip with 3.3V working voltage is 0-0.66V, the high level identification range of the signal receiving chip with 3.3V working voltage is 1.98-3.3V, when the signal transmitting chip with 1.8V working voltage sends out a low level signal, the low level is 0V, which is just in the low level identification range of 0-0.66V of the signal receiving chip with 3.3V working voltage, when the signal transmitting chip with 1.8V working voltage sends out a high level signal, the high level signal is 1.8V, and the high level signal is not in the high level identification range of 1.98-3.3V signal receiving chip with 3.3V working voltage, and is not in the low level identification range of 0.66V-0.66V of the signal receiving chip with 3.3V working voltage, belonging to signals which cannot be identified by a signal receiving chip with 3.3V working voltage.
SUMMERY OF THE UTILITY MODEL
In view of this, in order to solve the problem that the high level signal that the signaling chip of 1.8V operating voltage sent can't be discerned by the signal receiving chip of 3.3V operating voltage, the utility model provides a level conversion circuit that disconnect-type component is constituteed, it includes that a triode Q1, a electric capacity C1 and two resistance R1 and R2 can realize the conversion of level for 1.8V signal can be converted into the signal transmission of 3.3V and send the signal receiving chip, only need a few minutes under the general condition and just can solve above-mentioned problem, and the cost is lower, is suitable for industrial production.
A level conversion circuit composed of separated elements comprises: the signal transmitting chip U1, the signal receiving chip U2, the triode Q1, the first resistor R1, the second resistor R2 and the capacitor C1, the working voltage of the signal transmitting chip U1 is 1.8V, and the action voltage of the signal receiving chip U2 is 3.3V, and the signal transmitting chip U1, the signal receiving chip U2, the triode Q1 and the capacitor C1 are characterized in that: an emitter E of the triode Q1 is connected with a transmitting end UART _ TXD of a signal transmitting chip U1, a collector C of the triode Q1 is connected with a receiving end MCU _ RX of a signal receiving chip U2, a second end of the second resistor R2 is connected between the collector C of the triode Q1 and the receiving end MCU _ RX of the signal receiving chip U2, a first end of the second resistor R2 is connected with 3.3V voltage, the second resistor R2 is a pull-up resistor, a base B of the triode Q1 is connected with a power supply VDD _ EXT of 1.8V through the first resistor R1 in series, and the first resistor R1 is used for reducing the base B current of the triode Q1.
Further, the transistor Q1 is an NPN transistor.
Further, the model of the triode Q1 is FHT 8050Y-ME.
Furthermore, a capacitor C1 is connected in parallel with the first resistor R1, one end of the capacitor C1 is connected to the base B of the transistor Q1, the other end of the capacitor C1 is connected between one end of the resistor R1 and the 1.8V power supply VDD _ EXT, and the capacitor C1 plays a role in filtering and prevents noise.
Further, the operating parameter of the first resistor R1 is 4.7K, the operating parameter of the second resistor R2 is 4.7K, and the operating parameter of the capacitor C1 is 10 nF.
Furthermore, the acceptable low level of the signal receiving chip U2 is 0-0.66V, and the acceptable high level of the signal receiving chip U2 is 1.98-3.3V.
Furthermore, the working frequency of the signal sending data of the signal sending chip U1 is less than or equal to 1 KHz.
The utility model discloses a level shift circuit's that disconnect-type component is constituteed theory of operation as follows: when a transmitting end UART _ TXD of the signal transmitting chip U1 transmits a low-level signal, namely a 0V signal, a triode Q1 is saturated, the voltage UCE of a collector C of Q1 to an emitter E is 0.3V, a pin 3 of the triode Q1 outputs a 0V voltage signal to a receiving end MCU _ RX of the signal receiving chip U2, the OV voltage signal at the moment is within a low-level signal identification range of 0-0.66V of the signal receiving chip U2, and the signal receiving chip U2 can identify the low-level signal; when a transmitting end UART _ TXD of the signal transmitting chip U1 transmits a high level signal, that is, a 1.8V signal, the triode Q1 is turned off, and under the action of the pull-up resistor R2, a receiving end MCU _ RX of the signal receiving chip U2 receives a 3.3V signal, and at this time, the 3.3V voltage signal is within a high level signal identification range of 1.98-3.3V of the signal receiving chip U2, and the signal receiving chip U2 can identify the high level signal.
Therefore, the utility model discloses a level conversion circuit that disconnect-type component is constituteed can realize the conversion of level through a triode Q1, a electric capacity C1 and two resistance R1 and R2 for 1.8V's signal can be converted into 3.3V's signal transmission and send the signal reception chip, and the cost is lower, is fit for industrial production. Meanwhile, the signal transmitting chip U1 cannot be damaged by the saturation and cut-off states of the transistor Q1. In addition, the level conversion circuit composed of the separate elements is suitable for the working frequency of signal transmission data with medium and low speed within 1KHz, and has strong adaptability. Furthermore, if the conventional logic chip is used to solve the level switching problem, the standby current is several hundred milliamperes, and the level switching circuit composed of the separated elements of the present invention has only several hundred nanoamperes of standby current and very low power consumption.
Drawings
Fig. 1 is a schematic diagram of a level shift circuit composed of separate elements according to the present invention.
The following detailed description of the invention will be further described in conjunction with the above-identified drawings.
Detailed Description
Specific embodiment example 1:
fig. 1 is a schematic diagram of a level shift circuit composed of separate elements according to the present invention. A level conversion circuit composed of separated elements comprises: the signal transmitting chip U1, the signal receiving chip U2, the triode Q1, the first resistor R1, the second resistor R2 and the capacitor C1, the working voltage of the signal transmitting chip U1 is 1.8V, and the action voltage of the signal receiving chip U2 is 3.3V, and the signal transmitting chip U1, the signal receiving chip U2, the triode Q1 and the capacitor C1 are characterized in that: an emitter E of the triode Q1 is connected with a transmitting end UART _ TXD of a signal transmitting chip U1, a collector C of the triode Q1 is connected with a receiving end MCU _ RX of a signal receiving chip U2, a second end of the second resistor R2 is connected between the collector C of the triode Q1 and the receiving end MCU _ RX of the signal receiving chip U2, a first end of the second resistor R2 is connected with 3.3V voltage, the second resistor R2 is a pull-up resistor, a base B of the triode Q1 is connected with a power supply VDD _ EXT of 1.8V through the first resistor R1 in series, and the first resistor R1 is used for reducing the base B current of the triode Q1.
The triode Q1 is an NPN type triode, and the model of the triode Q1 is FHT 8050Y-ME. The capacitor C1 is connected in parallel with the first resistor R1, one end of the capacitor C1 is connected to the base B of the triode Q1, the other end of the capacitor C1 is connected between one end of the resistor R1 and the 1.8V power supply VDD _ EXT, and the capacitor C1 plays a role in filtering and prevents noise. The operating parameter of the first resistor R1 is 4.7K, the operating parameter of the second resistor R2 is 4.7K, and the operating parameter of the capacitor C1 is 10 nF. The acceptable low level of the signal receiving chip U2 is 0-0.66V, and the acceptable high level of the signal receiving chip U2 is 1.98-3.3V. The working frequency of the signal sending data of the signal sending chip U1 is less than or equal to 1 KHz.
The operation principle of the level shift circuit composed of the separate components as described above is as follows: when a transmitting end UART _ TXD of the signal transmitting chip U1 transmits a low-level signal, namely a 0V signal, a triode Q1 is saturated, the voltage UCE of a collector C of Q1 to an emitter E is 0.3V, a pin 3 of the triode Q1 outputs a 0V voltage signal to a receiving end MCU _ RX of the signal receiving chip U2, the OV voltage signal at the moment is within a low-level signal identification range of 0-0.66V of the signal receiving chip U2, and the signal receiving chip U2 can identify the low-level signal; when a transmitting end UART _ TXD of the signal transmitting chip U1 transmits a high level signal, that is, a 1.8V signal, the triode Q1 is turned off, and under the action of the pull-up resistor R2, a receiving end MCU _ RX of the signal receiving chip U2 receives a 3.3V signal, and at this time, the 3.3V voltage signal is within a high level signal identification range of 1.98-3.3V of the signal receiving chip U2, and the signal receiving chip U2 can identify the high level signal.
Therefore, the utility model discloses a level conversion circuit that disconnect-type component is constituteed can realize the conversion of level through a triode Q1, a electric capacity C1 and two resistance R1 and R2 for 1.8V's signal can be converted into 3.3V's signal transmission and send the signal reception chip, and the cost is lower, is fit for industrial production. Meanwhile, the signal transmitting chip U1 cannot be damaged by the saturation and cut-off states of the transistor Q1. In addition, the level conversion circuit composed of the separate elements is suitable for the working frequency of signal transmission data with medium and low speed within 1KHz, and has strong adaptability. Furthermore, if the conventional logic chip is used to solve the level switching problem, the standby current is several hundred milliamperes, and the level switching circuit composed of the separated elements of the present invention has only several hundred nanoamperes of standby current and very low power consumption.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (7)
1. A level conversion circuit composed of separated elements comprises: the signal transmitting chip U1, the signal receiving chip U2, the triode Q1, the first resistor R1, the second resistor R2 and the capacitor C1, the working voltage of the signal transmitting chip U1 is 1.8V, and the action voltage of the signal receiving chip U2 is 3.3V, and the signal transmitting chip U1, the signal receiving chip U2, the triode Q1 and the capacitor C1 are characterized in that: an emitter E of the triode Q1 is connected with a transmitting end UART _ TXD of a signal transmitting chip U1, a collector C of the triode Q1 is connected with a receiving end MCU _ RX of a signal receiving chip U2, a second end of the second resistor R2 is connected between the collector C of the triode Q1 and the receiving end MCU _ RX of the signal receiving chip U2, a first end of the second resistor R2 is connected with 3.3V voltage, the second resistor R2 is a pull-up resistor, and a base B of the triode Q1 is connected with a power supply VDD _ EXT of 1.8V through the first resistor R1 in series.
2. The split component level shifter of claim 1, wherein: the transistor Q1 is an NPN type transistor.
3. The split component level shifter of claim 1, wherein: the model of the triode Q1 is FHT 8050Y-ME.
4. The split component level shifter of claim 1, wherein: the capacitor C1 is connected in parallel with the first resistor R1, one end of the capacitor C1 is connected to the base B of the transistor Q1, and the other end of the capacitor C1 is connected between one end of the resistor R1 and the 1.8V power supply VDD _ EXT.
5. The split component level shifter of claim 1, wherein: the operating parameter of the first resistor R1 is 4.7K, the operating parameter of the second resistor R2 is 4.7K, and the operating parameter of the capacitor C1 is 10 nF.
6. The split component level shifter of claim 1, wherein: the acceptable low level of the signal receiving chip U2 is 0-0.66V, and the acceptable high level of the signal receiving chip U2 is 1.98-3.3V.
7. The split component level shifter of claim 1, wherein: the working frequency of the signal sending data of the signal sending chip U1 is less than or equal to 1 KHz.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922424129.6U CN211151943U (en) | 2019-12-30 | 2019-12-30 | Level switching circuit composed of separated elements |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922424129.6U CN211151943U (en) | 2019-12-30 | 2019-12-30 | Level switching circuit composed of separated elements |
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| CN211151943U true CN211151943U (en) | 2020-07-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114384840A (en) * | 2021-12-30 | 2022-04-22 | 成都天佑智云科技发展有限公司 | Control system of total station |
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- 2019-12-30 CN CN201922424129.6U patent/CN211151943U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114384840A (en) * | 2021-12-30 | 2022-04-22 | 成都天佑智云科技发展有限公司 | Control system of total station |
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