CN208580401U - A kind of multiplexed port system based on SPI communication - Google Patents
A kind of multiplexed port system based on SPI communication Download PDFInfo
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- CN208580401U CN208580401U CN201821188198.0U CN201821188198U CN208580401U CN 208580401 U CN208580401 U CN 208580401U CN 201821188198 U CN201821188198 U CN 201821188198U CN 208580401 U CN208580401 U CN 208580401U
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Abstract
The utility model discloses a kind of multiplexed port system based on SPI communication, including MCU, clock circuit, system reset circuit, AD sample circuit, liquid crystal circuit, storage circuit, Ethernet control circuit, safety chip circuit, CAN communication circuit etc..There are multiple communication interface inside the MCU, wherein SPI interface altogether there are three: flash chip and ferroelectricity register are multiplexed first group of SPI interface, and two ethernet controllers are multiplexed second group of SPI interface, safety chip third group SPI interface.The purposes quickly accessed of data is realized by SPI port multiplexing, the purpose with main website high-speed traffic is realized by the multiplexing of the SPI port of Dual-Ethernet controller and MCU.The multiplexed port system based on SPI communication that the utility model provides, Yi Yizhi, it is easy to accomplish Function Extension can be widely applied to the various automation equipments using SPI communication mode.
Description
Technical field
The present invention relates to fields of communication technology, and in particular to a kind of multiplexed port system based on SPI communication.
Background technique
For a long time, in the design process of product, the mismatch between peripheral equipment and MCU speed is a disaster always
Topic, affects the service performance of product systems.With increasing rapidly for computer storage size and processing capacity, this problem table
It must now become increasingly conspicuous.Although the method for having had taken up various soft and hardwares constantly improves connecing between MCU and I/O equipment
Mouth performance.However, interface problem still restricts system performance in numerous applications.For specifically designing, designer is faced
Diversified interface standard, the generally cost according to needed for system and function select suitable standardized product, this may cause
Interface standard conflict and cause interoperability problems；Perhaps the normal component with interface compatibility is reselected, but is likely to result in
It is unsatisfactory for function needs or cost requirement etc..
SPI is the communication bus of a kind of high speed, synchronization, full duplex, and 4 lines are only taken up on the pin of chip, are not only saved
The about pin of chip, while in the layout of PCB also saving space.Exactly few for its signal wire, agreement is simple, relative number
According to the high characteristic of rate, this communication protocol of more and more integrated chips now.
In the product design process of distribution power automation terminal, the peripheral circuit of MCU is more, used communication interface
It is not quite similar.Wherein storage circuit (ferroelectricity register and flash), double network port circuits and safety chip circuit are all logical using SPI
Believe interface, and used MCU controller only has 3 SPI interfaces, causes the situation of port assignment unevenness.If using software
IO simulates the scheme of SPI timing, this simulation process is entirely MCU in responsible execution, in order to stablize access data, can be inserted into soft
Part delay, this time is not obvious in the case where reading data volume is little, but in reading process, other are non-interrupted non-
Abnormal program is unable to get execution；Therefore the scheme of software simulation is undesirable.
Summary of the invention
In view of the above-mentioned problems of the prior art, the present invention discloses a kind of multiplexed port system based on SPI communication, adopt
The scheme being multiplexed with hardware port, occupancy MCU resource is few, saves program runtime, and MCU is facilitated to carry out more other grasp
Make.
Hardware port multiplexing technology scheme of the invention is: flash chip and ferroelectricity register are multiplexed the same SPI and connect
Mouthful, two ethernet controllers are multiplexed the same SPI interfaces, and the I/O port resource in effective solution MCU system design is not
The problem of foot, simplifies system structure, and perfect system function.
A kind of multiplexed port system based on SPI communication, it is characterised in that: including MCU, clock circuit, system reset electricity
Road, AD sample circuit, liquid crystal circuit, storage circuit, Ethernet control circuit, safety chip circuit, CAN communication circuit etc..
The MCU using the Cortex M4 kernel of TI STM32 microcontroller, inside there are multiple communication interface,
Wherein SPI interface altogether there are three, to meet system design, port assignment situation are as follows: flash chip and ferroelectricity register multiplexing the
One group of SPI interface, two ethernet controllers are multiplexed second group of SPI interface, safety chip third group SPI interface.Its SPI connects
Mouth holotype controller includes: fifo module, control module, data packing block, bus interface configuration module, SPI physical layer
Module etc..
A kind of above-mentioned multiplexed port system based on SPI communication, it is further characterized by: the source of SPI clock is
The clock signal divided by the clock that external system clock circuit provides, by be arranged each distinct interface when
Clock Frequency Dividing Factor register generates corresponding clock output signal as serial clock.In order to guarantee the reliability of timing, according to
Data transmission successively requires, and different Frequency Dividing Factors is arranged to three SPI respectively, reaches the mesh of the timesharing sub-module operation of system
's.
The flash storage chip, ferroelectricity register, ethernet controller are multiplexed by SPI interface to be connected with MCU
It connects, MCU used by this system is that 3.3V power supply can connect if selected peripheral chip is 5V power supply in peripheral chip and SPI
Bus transceiver SN74LVC4245A is added between mouthful to complete level conversion.
The Dual-Ethernet control circuit main function is the communication realized between MCU and main website, and present invention design is adopted
Be multiplexed same SPI interface circuitry with double network interfaces, system carries out the mode of time-sharing operation, by electric power specification realize double network interfaces with
Communication between main website.
Detailed description of the invention
Fig. 1 is the composition block diagram of the multiplexed port system based on SPI communication of the embodiment of the present invention.
Fig. 2 is the full size figure of the multiplexed port system based on SPI communication of the embodiment of the present invention.
Specific embodiment
For the ease of the understanding of those skilled in the art, below with reference to embodiment, the present invention is further illustrated.
The multiplexed port system based on SPI communication of the present embodiment, composition block diagram is as shown in Figure 1, it includes MCU, clock
Circuit, system reset circuit, AD sample circuit, liquid crystal circuit, storage circuit, Ethernet control circuit, safety chip circuit,
CAN communication circuit etc..The MCU using the Cortex M4 kernel of TI STM32 microcontroller, inside there are a variety of logical
Believe interface, wherein SPI interface altogether there are three, for meet system design, port assignment situation are as follows: flash chip and ferroelectricity deposit
Device is multiplexed first group of SPI interface, and two ethernet controllers are multiplexed second group of SPI interface, and safety chip is connect with third group SPI
Mouthful.Its SPI interface holotype controller include: fifo module, control module, data packing block, bus interface configuration module,
SPI physical layer block etc..
The source of SPI clock is the clock signal that the clock provided by external system clock circuit is divided,
By the way that the clock division factor register of each distinct interface is arranged, corresponding clock output signal is generated as serial clock.
In order to guarantee the reliability of timing, is transmitted according to data and successively required, different Frequency Dividing Factors is arranged to three SPI respectively, is reached
The purpose operated to the timesharing sub-module of system.
The flash storage chip, ferroelectricity register, ethernet controller are multiplexed by SPI interface to be connected with MCU,
MCU used by this system is 3.3V power supply, can be in peripheral chip and SPI interface if selected peripheral chip is 5V power supply
Between bus transceiver SN74LVC4245A be added complete level conversion.
For the demand of technical standard of distribution power automation terminal equipment, the signal wire based on SPI communication is few, and agreement is simple,
The high characteristic of relative data rate, the present invention use the design scheme of SPI hardware port multiplexing, design the end based on SPI communication
Mouth multiplex system device, is applied in a station power distribution automatization terminal equipment, as the core cell of terminal device, leads to
Crossing SPI port multiplexing realizes the purpose of data quickly accessed, and is multiplexed by the SPI port of Dual-Ethernet controller and MCU
The purpose with main website high-speed traffic is realized, desired effect is achieved.Dual-Ethernet control circuit main function be realize MCU and
Communication between main website, the present invention, which is designed, is multiplexed the same SPI interface circuitry using double network interfaces, and system carries out the side of time-sharing operation
Formula realizes the communication between double network interfaces and main website by electric power specification.
Fig. 2 is the full size figure of the multiplexed port system based on SPI communication of the embodiment of the present invention.
Above embodiment is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all
It is any changes made on the basis of the technical scheme according to the technical idea provided by the invention, each falls within present invention protection model
Within enclosing.The technology that the present invention is not directed to can be realized by existing technology.
Claims (3)
1. a kind of multiplexed port system based on SPI communication, it is characterised in that: including MCU, clock circuit, system reset circuit,
AD sample circuit, liquid crystal circuit, storage circuit, Ethernet control circuit, safety chip circuit, CAN communication circuit；
The MCU using TI Cortex M4 kernel STM32 microcontroller, inside there are multiple communication interfaces, wherein
There are three SPI interface is total: flash storage chip and ferroelectricity register are multiplexed first group of SPI interface, and two ethernet controllers are multiple
With second group of SPI interface, safety chip third group SPI interface；The SPI interface holotype controller include: fifo module,
Control module, data packing block, bus interface configuration module, SPI physical layer block；The clock circuit, system reset electricity
Road, AD sample circuit, liquid crystal circuit, storage circuit, Ethernet control circuit, safety chip circuit, CAN communication circuit respectively with
The MCU connection.
2. the multiplexed port system according to claim 1 based on SPI communication, it is characterised in that: the clock circuit is
The external oscillating circuit being made up of crystal oscillator and trimmer provides clock source for system, SPI clock be by system clock into
The clock signal that row frequency dividing obtains generates corresponding clock by the way that the clock division factor register of each distinct interface is arranged
Output signal is as serial clock；In order to guarantee the reliability of timing, is transmitted according to data and successively required, respectively to three SPI
Different Frequency Dividing Factors is set, achievees the purpose that the timesharing sub-module operation of system.
3. the multiplexed port system according to claim 1 based on SPI communication, it is characterised in that: the flash stores core
Piece, ferroelectricity register, ethernet controller are multiplexed by SPI interface to be connected with the MCU；The Ethernet control circuit is adopted
It is multiplexed the same SPI interface circuitry with double network interfaces, system carries out the mode of time-sharing operation, realizes MCU and master by electric power specification
Communication between standing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821188198.0U CN208580401U (en) | 2018-07-25 | 2018-07-25 | A kind of multiplexed port system based on SPI communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821188198.0U CN208580401U (en) | 2018-07-25 | 2018-07-25 | A kind of multiplexed port system based on SPI communication |
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| Publication Number | Publication Date |
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| CN208580401U true CN208580401U (en) | 2019-03-05 |
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| CN201821188198.0U Active CN208580401U (en) | 2018-07-25 | 2018-07-25 | A kind of multiplexed port system based on SPI communication |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113615130A (en) * | 2019-03-19 | 2021-11-05 | 德克萨斯仪器股份有限公司 | Sample-based data transmission over a lower-layer communication channel |
-
2018
- 2018-07-25 CN CN201821188198.0U patent/CN208580401U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113615130A (en) * | 2019-03-19 | 2021-11-05 | 德克萨斯仪器股份有限公司 | Sample-based data transmission over a lower-layer communication channel |
| CN113615130B (en) * | 2019-03-19 | 2024-01-26 | 德克萨斯仪器股份有限公司 | Sample-based data transmission over a low-level communication channel |
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Address after: 211100 No. 5 Jinxin East Road, Jiangning District, Nanjing City, Jiangsu Province Patentee after: Nanjing Jialong Electric Technology Co., Ltd Address before: 211100 No. 5 Jinxin East Road, Jiangning District, Nanjing City, Jiangsu Province Patentee before: NANJING JIALONG ELECTRIC TECHNOLOGY Co.,Ltd. |