CN204289500U - Led chip - Google Patents
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- CN204289500U CN204289500U CN201420762434.0U CN201420762434U CN204289500U CN 204289500 U CN204289500 U CN 204289500U CN 201420762434 U CN201420762434 U CN 201420762434U CN 204289500 U CN204289500 U CN 204289500U
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Abstract
The utility model proposes a kind of LED chip, this LED chip comprises: substrate; Comprise resilient coating, n type semiconductor layer, luminescent layer, electronic barrier layer, p type semiconductor layer and transparency conducting layer successively in described substrate, wherein, the surface of described transparency conducting layer arranges multiple concentric arc line trenches of different interval; Be positioned at the P-type electrode be electrically connected with described transparency conducting layer on described transparency conducting layer, and be positioned at the N-type electrode that described transparency conducting layer side is electrically connected with described n type semiconductor layer.LED chip of the present utility model can effectively reduce electric current and block up, and make current spread more even, luminous efficiency is improved, and life-span length, stability are enhanced.
Description
Technical field
The utility model relates to light emitting device technologies field, particularly a kind of LED chip.
Background technology
LED(Lighting Emitting Diode, light-emitting diode) chip is the core texture of LED, at present, LED chip adopts sapphire as substrate mostly, and as shown in Figure 1, chip structure comprises: (1), difference deposit epitaxial layers on saphire substrate material, be followed successively by resilient coating, N-type GaN layer from top to bottom, MQW(Multiple Quantum Wells, Multiple Quantum Well) luminescent layer, P type GaN layer.(2), by chip be etched to N-type GaN layer from P type GaN layer, etch areas is prepared N electrode and negative pole.(3), in P type GaN layer ITO(Indium tin oxide is deposited, tin indium oxide) layer, prepare P electrode and positive pole on the ito layer, wherein, on ITO layer, comprise silicon dioxide passivation layer.
But, for the LED chip of horizontal structure as shown in Figure 1, current spread is very uneven, generation current spreads uneven reason mainly because the resistivity difference of P type GaN and N-type GaN is very large, when electric current flows through P type GaN layer, substantially there is no horizontal proliferation, therefore solved the problem of current spread on P type GaN surface by ITO transparency conducting layer.But, as shown in Figure 2, when electric current spreads through P type GaN layer, because the resistivity of ITO layer is lower, electric current can be collected at the region of close negative pole in a large number through ITO horizontal proliferation, get congestion phenomenon, causes this portion of electrical current density excessive, and then affect the stability of chip, reduce its light efficiency and useful life.
Particularly, as shown in Figure 3, be the path model of the LED chip current direction in correlation technique.Occur that the region of electric current horizontal proliferation only has ITO layer and N-type GaN layer, wherein, ITO layer resistance is set to dt, and N-type GaN layer resistance is set to dx, and P type GaN layer resistance is set to R1, and PN junction step resistance is set to R2.Resistivity due to conventional ITO material is less than the resistivity of N-type GaN, and wherein, the resistivity of ITO is 10
-4the order of magnitude, and the resistivity of N-type GaN layer is 10
-2-10
-3the order of magnitude, therefore electric current can be preferential by the L path of ITO horizontal proliferation extremely in region such as Fig. 3 of negative pole, causes electric current to block up in the region near negative pole.
Electric current for the LED chip of horizontal structure can block up in the shortcoming in the region near electrode, discloses a kind of scheme of improvement in the related.As shown in Figure 4, in the related, based on said chip structure, complete hole on the ito layer, density distribution is there is in hole from positive pole to negative pole, the making of hole makes electric current to try one's best to inject whole LED chip equably, make it work in the state of uniformly light-emitting, improve the luminous efficiency of LED chip.
Although make hole on ITO layer surface, alleviate electric current preferentially to the non-uniform phenomenon of negative regions diffusion, but, some problems of same existence, such as, the local diffusion of ITO layer surface current is uneven, electric current meeting preferential flow is to the region not having ITO hole, that is: on ITO, imperforate zone current density is large, and pertusate zone current density is little, thus also can cause the inhomogeneities of current spread.
Utility model content
The utility model is intended to solve one of above-mentioned technical problem at least to a certain extent.For this reason, the utility model needs to propose a kind of LED chip, and this LED chip can effectively reduce electric current and block up, and make current spread more even, luminous efficiency is improved, and life-span length, stability are enhanced.
For solving the problem, the utility model on the one hand embodiment proposes a kind of LED chip, and this LED chip comprises: substrate; Comprise resilient coating, n type semiconductor layer, luminescent layer, electronic barrier layer, p type semiconductor layer and transparency conducting layer successively in described substrate, wherein, the surface of described transparency conducting layer arranges multiple concentric arc line trenches of different interval; Be positioned at the P-type electrode be electrically connected with described transparency conducting layer on described transparency conducting layer, and be positioned at the N-type electrode that described transparency conducting layer side is electrically connected with described n type semiconductor layer.
According to the LED chip of the utility model embodiment, by arranging multiple concentric arc line trenches of different interval over transparent conductive layer, electric current can be reduced block up, and compared with the chip that hole is set, current spread is more even, and then the luminous efficiency of chip is improved, life-span length, stability are enhanced.
The aspect that the utility model is additional and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present utility model.
Accompanying drawing explanation
The utility model above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 is the structural representation of a kind of LED chip of prior art;
Fig. 2 is that the electric current of the LED chip of prior art blocks up schematic diagram;
Fig. 3 is the current spread schematic equivalent circuit of the LED chip of prior art;
Fig. 4 is the pore space structure schematic diagram in the ITO layer of the LED chip of prior art;
Fig. 5 is the structural representation of the LED chip according to an embodiment of the present utility model;
Fig. 6 is according to the camber line groove schematic diagram on the transparency conducting layer of the LED chip of a specific embodiment of the present utility model;
Fig. 7 is the structural representation of the LED chip according to another embodiment of the present utility model;
Fig. 8 is the flow chart of the preparation method of LED chip according to an embodiment of the present utility model;
Fig. 9 is the structural representation of the epitaxial wafer prepared in the preparation method according to the LED chip of another embodiment of the present utility model;
Figure 10 is the structural representation with PN junction step prepared in the preparation method according to the LED chip of another embodiment of the present utility model;
Figure 11 is the structural representation with transparency conducting layer prepared in the preparation method according to the LED chip of another embodiment of the present utility model;
Figure 12 is the schematic diagram with camber line groove structure prepared in the preparation method according to the LED chip of another embodiment of the present utility model;
Figure 13 is the flow chart of the preparation method of LED chip according to another embodiment of the present utility model.
Embodiment
Be described below in detail embodiment of the present utility model, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the utility model, and can not being interpreted as restriction of the present utility model.
Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present utility model.Of the present utility model open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the utility model.In addition, the utility model can in different example repeat reference numerals and/or letter.This repetition is to simplify and clearly object, itself does not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique that the utility model provides and the example of material, but those of ordinary skill in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, fisrt feature described below second feature it " on " structure can comprise the embodiment that the first and second features are formed as directly contact, also can comprise other feature and be formed in embodiment between the first and second features, such first and second features may not be direct contacts.
In description of the present utility model, it should be noted that, unless otherwise prescribed and limit, term " installation ", " being connected ", " connection " should be interpreted broadly, such as, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be directly be connected, also indirectly can be connected by intermediary, for the ordinary skill in the art, the concrete meaning of above-mentioned term can be understood as the case may be.
With reference to description below and accompanying drawing, by these and other aspects of clear embodiment of the present utility model.In these descriptions and accompanying drawing, specifically disclose some particular implementation in embodiment of the present utility model, represent some modes of the principle implementing embodiment of the present utility model, but should be appreciated that the scope of embodiment of the present utility model is not limited.On the contrary, embodiment of the present utility model comprise fall into attached claims spirit and intension within the scope of all changes, amendment and equivalent.
The preparation method of LED chip and the LED chip proposed according to the utility model embodiment is described with reference to the accompanying drawings.
First, the LED chip of the utility model embodiment is described.Fig. 5 is the structural representation of the LED chip according to an embodiment of the present utility model.As shown in Figure 5, the LED chip 100 of the utility model embodiment comprises substrate 10 such as Sapphire Substrate, resilient coating 20 is comprised successively on substrate 10, n type semiconductor layer 30 is N-type GaN layer such as, luminescent layer 40 such as mqw layer, p type semiconductor layer 50 such as P type GaN layer and transparency conducting layer 60 such as ITO layer, ITO layer plays the effect increasing current spread, and, be positioned at the P-type electrode 70 be electrically connected with transparency conducting layer 60 on transparency conducting layer 60, with the N-type electrode 80 being positioned at transparency conducting layer 60 side and being electrically connected with n type semiconductor layer 30, particularly, in instances, electrode and P-type electrode 70 and N-type electrode 80 can comprise Cr/Ti/Au electrode, one or both in Cr/Pt/Au electrode and Ti/Al/Ti/Au electrode.
Wherein, the surface of transparency conducting layer 60 arranges multiple concentric arc line trenches 61 of different interval, in an embodiment of the present utility model, the distribution of the multiple concentric arc line trenches on transparency conducting layer 60 as shown in Figure 6, the distribution density of multiple camber line groove 61 is different, and multiple camber line groove is concentric camber line.Particularly, material resistance and cross-sectional area are inversely proportional to, the ITO camber line groove with density gradient is made on the surface of transparency conducting layer 60 i.e. current-diffusion layer such as ITO layer, the areal cross-section then reducing transparency conducting layer 60 amasss, wherein, the resistance ratio on the ito layer with the region of camber line groove 61 does not have the resistance in the region of camber line groove 61 large, and the pitch density of camber line groove 61 is larger, the degree of depth is darker, then the resistance in this region is larger.Therefore, as shown in Figure 3, electric current transparency conducting layer 60 to during the horizontal proliferation of negative regions by more and more difficult, can not preferentially through transparency conducting layer 60 horizontal proliferation to negative electrode area, thus reach the object preventing electric current from assembling in negative electrode area.Meanwhile, because camber line groove 61 is concentric camber line, such as, shown in Fig. 6, be the isocentric circular arc being the center of circle with P-type electrode 70, then electric current is identical to the resistance of either direction, so electric current will be diffused into whole transparency conducting layer 60 more equably.
Can find out, transparency conducting layer 60 makes the camber line groove 61 with different intervals, the effect of camber line groove 61 has: first, the resistance of transparency conducting layer 60 can be increased gradually, make electric current in transparency conducting layer 60, the region of close N-type electrode 80 during horizontal proliferation, can not be gathered in, the effect thus minimizing electric current blocks up; Secondly, make hole with in transparency conducting layer 60 such as ITO layer, electric current can be more even during horizontal proliferation in the transparency conducting layer 60 with concentrically ringed camber line groove 61; Finally, the thickness of the transparency conducting layer 60 at camber line groove 61 place is less, then less to the absorption of emergent light, therefore can improve the efficiency of LED chip 100.
Particularly, as shown in Figure 6, camber line groove 61 can centered by P-type electrode 70, interval the closer to P-type electrode 70 camber line groove 61 is larger, and the interval more away from P-type electrode 70 camber line groove 61 is less, then from P-type electrode the closer to N-type electrode 80, the resistance of transparency conducting layer 70 is increasing, then electric current spreads more and more difficult to N-type electrode 80, thus can reduce electric current gathering to N-type electrode 80, reduces electric current jam.
Particularly, in the utility model embodiment, the thickness of transparency conducting layer 60 such as ITO layer is 250-300nm, the width of camber line groove 61 is 1-3um, camber line groove 61 be spaced apart 2-15um, the degree of depth of camber line groove 61 is 80-200nm, the parameter of concrete camber line groove 61 should with the resistors match of the resistance of transparency conducting layer 60 such as ITO layer and epitaxial loayer n type semiconductor layer 30 such as N-type GaN layer.In addition, the P-type electrode 70 of conventional LED chips 100 is circular, P-type electrode 70 can be regarded as a point, then flow to the resistance of arbitrary rectilinear direction on transparency conducting layer 60 surface from this point identical for electric current, and therefore the diffusion of electric current in transparency conducting layer 60 is more even.
In the utility model embodiment, described LED chip 100 also comprises the electronic barrier layer (not shown) be formed between luminescent layer 40 and p type semiconductor layer 50, is generally AlGaN barrier layer.Electronic barrier layer can effectively block electrons overflow from active area, thus increases the quantity of active area electronics, improves Carrier recombination efficiency in luminescent layer 40, promotes LED chip 100 luminous efficiency.
Further, as shown in Figure 7, above-mentioned LED chip 100 also comprises passivation layer 90, and passivation layer 90 is positioned at the part except P-type electrode 70 on transparency conducting layer 60, and transparency conducting layer 60 side is except the part of N-type electrode 80.Can be understood as, the passivation layer 90 such as transparency conducting layer 60 of the naked leakage of silicon dioxide layer covering surfaces and the n type semiconductor layer 30 of PN junction step and naked leakage, passivation layer 90 can reduce the total reflection of light.
In sum, according to the LED chip of the utility model embodiment, by arranging multiple concentric arc line trenches of different interval density over transparent conductive layer, electric current can be reduced block up, and compared with the chip that hole is set, current spread is more even, and then the luminous efficiency of chip is improved, and life-span length, stability are enhanced.
Based on the structure of the LED chip of above-mentioned aspect embodiment, the preparation method of the LED chip proposed according to another aspect embodiment of the present utility model is described with reference to the accompanying drawings.
Fig. 8 is the flow chart of the preparation method of LED chip according to an embodiment of the present utility model, and as shown in Figure 8, the preparation method of the LED chip of the utility model embodiment comprises the following steps:
S1, on substrate successively epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer to obtain epitaxial wafer.
Particularly, as shown in Figure 9, take sapphire as substrate, adopting MOCVD(metal organic chemical vapor deposition) equipment prepares the epitaxial loayer of LED, upwards comprise successively from Sapphire Substrate: resilient coating is gallium nitride such as, n type semiconductor layer is N-GaN(n type gallium nitride such as), luminescent layer is MQW(Multiple-quantum hydrazine layer such as) structure, p type semiconductor layer is P-GaN(p type gallium nitride such as).
S2, epitaxial wafer is produced PN junction step, and prepares transparency conducting layer producing on the epitaxial wafer after PN junction step.
Particularly, epitaxial wafer is produced PN junction step and specifically comprises: on epitaxial wafer, prepare mask by photoetching method, such as, adopt positive photoresist to carry out photoetching to make mask to epitaxial wafer surface, expose the position of the N-GaN needing etching.And then etch to obtain PN junction step to the epitaxial wafer with mask, such as, utilize ICP(Inductive Coupled Plasma Emission Spectrometer, inductively coupled plasma) etching machine carries out dry etching to the epitaxial wafer with mask, etch period is such as 10-14 minute, and etching depth reaches 1.2-1.6 um, after having etched, remove residual photoresist, namely obtain PN junction step as shown in Figure 10.
Further, prepare transparency conducting layer producing on the epitaxial wafer after PN junction step, specifically comprise: adopt evaporation coating method producing evaporation transparency conducting layer on the epitaxial wafer after PN junction step, such as, the epitaxial wafer having made PN junction step is carried out chemical solution surface treatment, then put into evaporator and carry out evaporation to form transparency conducting layer such as ito thin film, the final thickness 250-300 nm of transparency conducting layer and film, and then in nitrogen atmosphere, annealing in process is carried out to transparency conducting layer, such as, annealing is in pure nitrogen gas atmosphere, annealing temperature is 450-540 DEG C, annealing time is 20-40 minute.Finally, the epitaxial wafer after annealing in process is etched, such as, need the region retained in yellow light area with positive photoresist protection, remove the region not needing to protect with ITO etching liquid, complete ITO preparation, obtain transparency conducting layer as shown in figure 11.
S3, produces multiple concentric arc line trenches of different interval on the surface of described transparency conducting layer.
Particularly, such as, yellow light area photoetching technique is utilized, transparency conducting layer such as ITO layer make mask, to expose the region needing to make camber line groove, and then using ITO etching liquid to etch exposing part, controlling etching liquid concentration, temperature and soak time, to control the interval of camber line groove, width and the degree of depth, in an embodiment of the present utility model, the width of camber line groove is 1-3um, camber line groove be spaced apart 2-15um, the degree of depth of camber line groove is 80-200nm.Wherein, as shown in Figure 6, the P-type electrode of such as pre-prepared circle, then can with the P-type electrode center of circle for concentric circles, the closer to the P-type electrode center of circle, groove camber line interval is larger, more away from the P-type electrode center of circle, groove camber line interval is less, then from P-type electrode the closer to N-type electrode, the resistance of transparency conducting layer is increasing, then electric current is more and more difficult to N-type electrode diffusion, thus electric current gathering to N-type electrode can be reduced, reduce electric current jam.Concrete camber line groove parameter should be mated with the resistance sizes of ITO resistance sizes and n type semiconductor layer such as N-GaN layer.After etching completes, get rid of remaining photoresist, thus prepare multiple camber line groove over transparent conductive layer as shown in figure 12.
S4, preparation P-type electrode and N-type electrode.
Particularly, first, adopt photoetching method to obtain electrode mask on the epitaxial wafer preparing arcuate furrow, such as, in yellow light area, utilize negative photoresist to carry out photoetching to prepare electrode mask to epitaxial wafer, need to prepare the region of electrode to expose.Then, evaporation coating method is adopted to prepare P-type electrode and N-type electrode respectively, the epitaxial wafer preparing mask is put into metal evaporation machine and carries out evaporation, wherein, electrode material can be one or both in Cr Ti Au, Cr Pt Au and Ti Al Ti Au.
After evaporation completes, remove electrode mask, and after the described electrode mask of removal, heat-treat epitaxial wafer in nitrogen atmosphere, wherein, heat treatment temperature is 280-350 DEG C, time is 15-25 minute, after carrying out alloy heat treatment, complete the preparation of electrode, prepare P-type electrode and N-type electrode as shown in Figure 5.
In addition, after preparation P-type electrode and N-type electrode, after obtaining LED chip, in order to reduce the diffuse reflection of emergent light, as shown in figure 13, above-mentioned preparation method can also comprise:
S5, deposit passivation layer on the epitaxial wafer preparing electrode.
Particularly, passivation layer can be silicon dioxide layer.Making the epitaxial wafer surface PECVD(Plasma Enhanced Chemical Vapor Deposition of electrode, plasma enhanced chemical vapor deposition) equipment deposits one deck SiO
2, the thickness of silicon dioxide layer is 50-100nm.And then adopt photoetching, lithographic method to process to obtain electrode part to passivation layer, such as, make mask to expose electrode part by photoetching technique, use HF-NH
4f cushions the SiO that etching liquid gets rid of expose portion
2, after having etched, get rid of remaining photoresist, namely obtain the LED chip of deposit passivation layer as shown in Figure 7, then complete the preparation of whole LED chip.
According to the preparation method of the LED chip of the utility model embodiment, multiple concentric arc line trenches of different interval are produced on the surface of transparency conducting layer, the electric current that can reduce LED chip blocks up, and compared with the chip that hole is set, current spread is more even, and then improve the luminous efficiency of chip, extend the life-span of LED chip, strengthen the stability of chip.
Describe and can be understood in flow chart or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of preferred implementation of the present utility model comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiment person of ordinary skill in the field of the present utility model.
In flow charts represent or in this logic otherwise described and/or step, such as, the sequencing list of the executable instruction for realizing logic function can be considered to, may be embodied in any computer-readable medium, for instruction execution system, device or equipment (as computer based system, comprise the system of processor or other can from instruction execution system, device or equipment instruction fetch and perform the system of instruction) use, or to use in conjunction with these instruction execution systems, device or equipment.With regard to this specification, " computer-readable medium " can be anyly can to comprise, store, communicate, propagate or transmission procedure for instruction execution system, device or equipment or the device that uses in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wiring, portable computer diskette box (magnetic device), random-access memory (ram), read-only memory (ROM), erasablely edit read-only memory (EPROM or flash memory), fiber device, and portable optic disk read-only memory (CDROM).In addition, computer-readable medium can be even paper or other suitable media that can print described program thereon, because can such as by carrying out optical scanner to paper or other media, then carry out editing, decipher or carry out process with other suitable methods if desired and electronically obtain described program, be then stored in computer storage.
Should be appreciated that each several part of the present utility model can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the application-specific integrated circuit (ASIC) of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, each functional unit in each embodiment of the utility model can be integrated in a processing module, also can be that the independent physics of unit exists, also can be integrated in a module by two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.If described integrated module using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present utility model or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and described embodiment of the present utility model, for the ordinary skill in the art, be appreciated that and can carry out multiple change, amendment, replacement and modification to these embodiments when not departing from principle of the present utility model and spirit, scope of the present utility model is by claims and equivalency thereof.
Claims (7)
1. a LED chip, is characterized in that, comprising:
Substrate;
Comprise resilient coating, n type semiconductor layer, luminescent layer, electronic barrier layer, p type semiconductor layer and transparency conducting layer successively in described substrate, wherein, the surface of described transparency conducting layer arranges multiple concentric arc line trenches of different interval;
Be positioned at the P-type electrode be electrically connected with described transparency conducting layer on described transparency conducting layer, and be positioned at the N-type electrode that described transparency conducting layer side is electrically connected with described n type semiconductor layer.
2. LED chip as claimed in claim 1, it is characterized in that, described camber line groove is centered by described P-type electrode, larger the closer to the interval of camber line groove described in described P-type electrode, more less away from the interval of camber line groove described in described P-type electrode.
3. LED chip as claimed in claim 1, it is characterized in that, the thickness of described transparency conducting layer is 250-300nm, and the width of described camber line groove is 1-3um, described camber line groove be spaced apart 2-15um, the degree of depth of described camber line groove is 80-200nm.
4. LED chip as claimed in claim 1, is characterized in that, also comprise:
Passivation layer, described passivation layer is positioned at the part except described P-type electrode on described transparency conducting layer, and described transparency conducting layer side is except the part of described N-type electrode.
5. LED chip as claimed in claim 1, is characterized in that, electrode comprise in Cr/Ti/Au electrode, Cr/Pt/Au electrode and Ti/Al/Ti/Au electrode one or both.
6. LED chip as claimed in claim 1, it is characterized in that, described electronic barrier layer is AlGaN layer.
7. LED chip as claimed in claim 4, it is characterized in that, described passivation layer is silicon dioxide layer.
Priority Applications (1)
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| CN111276586A (en) * | 2015-12-22 | 2020-06-12 | 晶元光电股份有限公司 | Light emitting assembly |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111276586A (en) * | 2015-12-22 | 2020-06-12 | 晶元光电股份有限公司 | Light emitting assembly |
| CN111276586B (en) * | 2015-12-22 | 2021-08-24 | 晶元光电股份有限公司 | Light emitting assembly |
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