CN1295768C - Ultrathin pinless packaging process of integrated circuit and discrete component and its packaging structure - Google Patents
Ultrathin pinless packaging process of integrated circuit and discrete component and its packaging structure Download PDFInfo
- Publication number
- CN1295768C CN1295768C CNB2004100416456A CN200410041645A CN1295768C CN 1295768 C CN1295768 C CN 1295768C CN B2004100416456 A CNB2004100416456 A CN B2004100416456A CN 200410041645 A CN200410041645 A CN 200410041645A CN 1295768 C CN1295768 C CN 1295768C
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- integrated circuit
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- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 238000012858 packaging process Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 141
- 239000002184 metal Substances 0.000 claims abstract description 141
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 42
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000004033 plastic Substances 0.000 claims abstract description 31
- 229920003023 plastic Polymers 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 30
- 229910052802 copper Inorganic materials 0.000 claims abstract description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 28
- 239000000956 alloy Substances 0.000 claims abstract description 28
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 21
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 35
- 238000005538 encapsulation Methods 0.000 claims description 25
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 19
- 239000000047 product Substances 0.000 claims description 15
- 239000011265 semifinished product Substances 0.000 claims description 15
- 238000012856 packing Methods 0.000 claims description 14
- 230000004913 activation Effects 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 239000012528 membrane Substances 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 239000000976 ink Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000000084 colloidal system Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 238000007648 laser printing Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000003466 welding Methods 0.000 abstract description 2
- 241000412565 Argentina sphyraena Species 0.000 abstract 3
- AILDTIZEPVHXBF-UHFFFAOYSA-N Argentine Natural products C1C(C2)C3=CC=CC(=O)N3CC1CN2C(=O)N1CC(C=2N(C(=O)C=CC=2)C2)CC2C1 AILDTIZEPVHXBF-UHFFFAOYSA-N 0.000 abstract 3
- 235000016594 Potentilla anserina Nutrition 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000002390 adhesive tape Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 230000008595 infiltration Effects 0.000 description 3
- 238000001764 infiltration Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000012958 reprocessing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Laminated Bodies (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to an ultrathin pinless packaging process for integrated circuits and discrete elements and a packaging structure thereof, which comprises the following process steps: a basal plate is fetched; dry ink is coated on the basal plate; a chip area and an inner pin area of throwing are etched on the basal plate; a metal layer, a metal active layer and a copper or alloy layer are coated on the basal plate; an argentine layer or a nickel and palladium layer is coated on the copper or alloy layer of the inner pin area of the throwing; a dry ink layer is removed; argentine sol is coated on the copper or alloy layer of the chip area; a chip is implanted into the argentine sol; the throwing operates; the operation is packaged by plastics and is printed by laser l; the basal plate on a bottom layer is removed and is pasted on a blue rubber film; packaged bodies are divided. The present invention has the advantages of strong welding capability, fine quality, low cost, smooth production, strong applicability, highest efficiency of cutting implements and cutter blades, flexible multi-chip arrangement and can not bring in various troubles of plastic package penetration.
Description
Technical field:
The present invention relates to a kind of integrated circuit or discrete components ultra-thin non-pin packing technology and encapsulating structure thereof.Belong to integrated circuit or discrete component encapsulation technology field.
Background technology:
Traditional integrated circuit or discrete components ultra-thin non-pin packing technology and encapsulating structure thereof, its encapsulation pattern is for being listed as old formula aggregate through being cut into single unit.Its substrate pattern is etching.It mainly has the following disadvantages:
1, needs to use special adhesive tape; in order to prevent that the plastics high pressure from sealing the time; its plastics can be penetrated on the lead frame; increase the crisis of solder joint insulation; if the reprocessing when the plastics infiltration takes place is easy to the solder joint metal level is destroyed; influence weldering sexuality, material cost like this, reprocessing cost and quality all have influence to a certain degree.
2, in order to make routing technology and output solder joint, in this technology, can produce smoothly, so plate expensive palladium material on the two sides of substrate, except electroplating cost than higher, the routing parameter also will be set special parameter at this material, causes because the parameter disunity directly influences the smoothness of production line.
3, the general material of using of substrate is to use the material of CU194, its conductance only have 65% and rate of heat dispation also slow, only be fit to general logicality or lower powered product.
4, because use the solvent of adhesive tape in the various again high-temperature technologies of special-purpose chemical adhesive tape to gasify out because of high temperature easily, the aluminium pad of indirect pollution or covering chip is the interior pin of routing, usually causes the instability of routing ability.
5, because this product is that plastics add copper material, so can not use identical blade and blade rotary speed under different materials to cut apart being listed as old formula integrated circuit or discrete component aggregate, two kinds of blades can not be the same, and if force when using identical blade to be rotary speed parameter, then the life-span of blade then can have a greatly reduced quality, and maintenance cost and quality all can be subjected to certain influence certainly.
6, because adopt the restriction of traditional handicraft, cause the solder joint of multicore sheet and different outputs, also arrangement that only can be inflexible, the property applied flexibly is significantly had a greatly reduced quality.
7, because adopt the restriction of traditional handicraft; the solder joint that causes output is the same flat with plastic encapsulation body bottom also, even the crisis of depression is arranged, and when surface mount scaling powder; rust remover and other chemical agent etc. all can't be discharged smoothly, so be relatively can have a greatly reduced quality on the weldering sexuality.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of and weld that sexuality is strong, best in quality, cost is lower, production is smooth and easy, applicability is strong, cutting implement and blade can have been given play to the highest efficient, the multicore sheet is arranged all puzzlements that the plastics infiltration flexibly, can not take place and integrated circuit or the discrete components ultra-thin non-pin packing technology and the encapsulating structure thereof of environmental protection.
The object of the present invention is achieved like this: a kind of integrated circuit or discrete components ultra-thin non-pin packing technology and encapsulating structure thereof comprise following processing step:
1) gets the Metal Substrate sheet material that a slice is fit to thickness;
2) do the China ink coating on metal substrate, its purpose is to make the program of insulation in the shallow plating of convenient follow-up every essential regions metal with unnecessary zone.Be not coated with on the metal substrate and do the Nei Jiao district that black zone forms chip region and routing;
3) on metal substrate with the Nei Jiao district of chip region and routing, carry out etching, its purpose is convenient bottom metal with every metal level, expose the mass colour colloid surface, when making plastic encapsulation body bottom carry out surface adhering again, tackability is better, is not easy to produce the phenomenon that the surface adhering solder joint has air or empty weldering;
4) on the metal substrate in chip region and routing Nei Jiao district, the sputter layer of metal, and this metal major function is that to have given play to the reliability and the conductive capability of metal its tackability when carrying out surface adhering better;
5) on the metal level in chip region and routing Nei Jiao district, sputter layer of metal active layer, and this metal activation layer major function is to have given play to metal and copper metal or alloy layer in the activation of carrying out two-way surface, and two kinds of different metal levels can fluid-tight engagement up and down to make the metal activation layer;
6) on the metal activation floor in chip region and routing Nei Jiao district, sputter layer of copper metal or alloy layer, and this copper metal or alloy layer major function is to be used as the real carrying base of this chips, again because be the copper metal or alloy, so conductive capability and heat-sinking capability all have extraordinary performance;
7) on the copper metal or alloy floor in routing Nei Jiao district, sputter one deck silver metal or nickel metal or palladium metal layer, and this metal level major function to be the performance metal wire smooth and firm with routing in pin zone carry out fluid-tight engagement;
8) original dried China ink on metal substrate is divested, prepare the operation of follow-up encapsulation the/test;
9) carry out the coating of elargol on the copper metal or alloy layer with chip region, in order to the program of subsequent wafer adhesion;
10) chip region that will just finish elargol coating is carried out the implantation of chip, carries out the operation of solidifying behind the elargol according to the characteristic of elargol after finishing, and makes the old formula aggregate of the row semi-finished product of integrated circuit or discrete component;
11) will finish the semi-finished product that chip is implanted operation, carry out the routing operation according to the characteristic of product;
12) will be the semi-finished product finished of routing, carry out the plastic encapsulation operation;
13) will finish the semi-finished product of plastic encapsulation operation, carry out laser printing in the plastic encapsulation surface;
14) will finish the semi-finished product of plastic encapsulation operation, and carry out the underlying metal substrate and divest operation, can find out that at the black encapsulated member each connects bond pad locations fully so;
15) will finish metal substrate and divest operation after, the plastic encapsulation body front with product is pasted on the blue glued membrane again, prepares to carry out follow-up colloid cutting operation;
16) will finish product and be attached at blue glued membrane after, can utilize cutting machine to carry out colloid is cut open, making originally is integrated circuit or the discrete component that the old formula aggregate mode of row connects together, and can be independent separately through cutting each integrated circuit of back or discrete component.
Purpose of the present invention can also be achieved in that a kind of integrated circuit or discrete components ultra-thin non-pin encapsulating structure, comprises interior pin carrying base, chip, metal wire and the encapsulated layer of chip bearing base, routing, is characterized in:
A) bottom of the interior pin carrying base of chip bearing base and routing is a metal level;
B) pin carries on the metal level of base in chip bearing base and the routing, first sputter layer of metal active layer, sputter layer of copper metal or alloy layer again;
C) on the copper metal or alloy layer of the interior pin carrying base of routing, sputter one deck silver metal or nickel metal or palladium metal layer;
D) coating one deck elargol layer on the copper metal or alloy layer of chip bearing base;
E) implant chip on the elargol layer of chip bearing base;
F) silver metal of the interior pin of the chip of the superiors of chip bearing base and the routing carrying base the superiors or nickel metal or palladium metal layer upper surface are connected with the metal wire two ends respectively;
G) except that the interior pin carrying base bottom of chip carrying base bottom and routing, plastic encapsulation is all used in the periphery of interior pin carrying base, chip and the metal wire of chip bearing base, routing.
Integrated circuit of the present invention or discrete components ultra-thin non-pin packing technology and encapsulating structure thereof, its encapsulation pattern also adopts the old formula aggregate of row through being cut into single unit.Its substrate pattern is to utilize substrate to grow the metal that other need again.Compare with traditional integrated circuit or discrete component packaging technology and structure, the present invention has following advantage:
1, need not use special-purpose high temperature high pressure rubber belt material,, and cost waste such as all puzzlements of plastics infiltrations and quality be bad can not take place fully so material cost is lower.
2, the substrate front side used of chip adopts traditional silver-plated mode interior foot part of routing, more popular cost is lower, the routing parameter is used and is generally got final product, substrate back signal output solder joint adopts partially plating gold to belong to the mode of layer, can make the function of chip reach the highest transmission and heat sinking function, but cost can't increase.
3, substrate adopts the material of fine copper or alloy, and its conductance and thermal diffusivity almost can reach 100%, except general logicality product, even in high-power product also be very suitable.
4, do not need fully to use any chemical adhesive tape, so can consider pollution problems fully.
5, new-type encapsulation pattern then will enter when cutting, and the part of encapsulated member is not have the material of unlike material to cut in the lump, so under the situation that a kind of material is only arranged, cutting implement and blade can have been given play to the highest efficient, quality is also more stable.
6, because of adopting new-type packaging technology and structure, in chip region or the solder joint of routing output can fully play ability and space.
It is to protrude from the encapsulated member surface that 7 new-type encapsulating structures then can be selected whether to use the solder joint of output, so the weldering sexuality of at present general chip can be kept in independently welding aspect of single-point, unsteadiness in the time of more can not worrying surface mount, quality is more stable than conventional package pattern more certainly.
Description of drawings:
Fig. 1～19 are respectively integrated circuit of the present invention or each operation schematic diagram of discrete components ultra-thin non-pin packing technology.
Figure 20 is integrated circuit of the present invention or discrete components ultra-thin non-pin encapsulating structure schematic diagram.
Embodiment:
1), gets the Metal Substrate sheet material A that a slice is fit to thickness referring to Fig. 1.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: alloy or copper etc.;
2), on metal substrate A, do black B coating referring to Fig. 2.Be not coated with on the metal substrate and do the Nei Jiao district C2 that black zone forms chip region C1 and routing;
3), on metal substrate,, carry out etching D with the Nei Jiao district C2 of chip region C1 and routing referring to Fig. 3;
4) referring to Fig. 4, on metal substrate A1, the A2 of chip region C1 and routing Nei Jiao district C2, sputter one deck simple metal layer 1;
5) referring to Fig. 5, on the simple metal 11,12 of chip region C1 and routing Nei Jiao district C2, sputter layer of metal active layer 2 is as aluminium lamination or nickel, titanium, silver, gold layer;
6) referring to Fig. 6, on the metal activation floor 21,22 of chip region C1 and routing Nei Jiao district C2, sputter one deck fine copper metal or alloy layer 3;
7) referring to Fig. 7, on the fine copper metal or alloy floor 31,32 of chip region C1 and routing Nei Jiao district C2, dash coat layer of metal active layer 41,42, and this metal activation layer major function is to have given play to fine copper metal or alloy layer and silver or nickel dam to carry out the activation on two-way surface, and two kinds of different metal levels can fluid-tight engagement up and down to make the metal activation layer;
8) referring to Fig. 8, on the metal activation floor 41,42 of chip region C1 and routing Nei Jiao district C2, sputter one deck silver metal or nickel metal or palladium metal layer 51,52;
9), original dried black B above metal substrate A is divested referring to Fig. 9;
10), the coating of elargol 61 will be carried out on the silver metal of chip region C1 or nickel metal or the palladium metal layer 51 referring to Figure 10;
11) referring to Figure 11, the chip region C1 that just finishes elargol coating is carried out the implantation of chip 7, carry out the operation of solidifying behind the elargol according to the characteristic of elargol after finishing, make the old formula aggregate of the row semi-finished product of integrated circuit or discrete component;
12) referring to Figure 12, implant the semi-finished product of operation with finishing chip, carry out routing 8 operations according to the characteristic of product;
13) referring to Figure 13, the semi-finished product that routing is finished carry out plastic encapsulation 9 operations except that bottom metal layer 1, and carry out curing operation after the plastic encapsulation according to the characteristic of plastics, and bottom metal layer 1 is protruded from outside the plastic encapsulation body 9;
14),, carry out laser printing 10 with finishing the semi-finished product of plastic encapsulation and back curing operation referring to Figure 14;
15),, carry out underlying metal substrate A and divest operation finishing the semi-finished product of plastic encapsulation and back curing operation referring to Figure 15;
16) referring to Figure 16, finish metal substrate layer divest operation after, can carry out the product function test jobs, and the mode of test also can adopt the test mode of single integrated circuit or discrete component except adopting full wafer array formula aggregate probe test mode;
17) referring to Figure 17, after will finishing metal substrate and divesting operation, the colloid front with product is affixed on the blue glued membrane E again;
18), after will finishing product and being attached at blue glued membrane, can utilize cutting machine to carry out the plastic encapsulation body is cut open referring to Figure 18;
19), the product utilization of finishing cutting is picked and placeed encapsulated member one by one the sucking-off blue glued membrane E of conversion equipment with single integrated circuit or discrete component, and be placed in the plastics carrier referring to Figure 19.Referring to Figure 20, integrated circuit or discrete components ultra-thin non-pin encapsulating structure mainly are made up of interior pin carrying base Y, chip 7, metal wire 8 and the encapsulated layer 9 of chip bearing base X, routing.Be characterized in:
A) bottom of the interior pin carrying base Y of chip bearing base X and routing is a metal level 11,12;
B) pin carries on the metal level 11,12 of base Y in chip bearing base X and the routing, first sputter layer of metal active layer 21,22, and sputter layer of copper metal or alloy layer 31,32 again;
C) on the copper metal or alloy layer 31,32 of the interior pin carrying base Y of chip bearing base X and routing, first sputter layer of metal active layer 41,42, sputter one deck silver metal or nickel metal or palladium metal layer 51,52 again;
D) on the silver metal of chip bearing base 1 or nickel metal or the palladium metal layer 51, coating one deck elargol layer 61;
E) implant chip 7 on the elargol layer 61 of chip bearing base X;
F) silver metal of the interior pin of the chip 7 of the superiors of chip bearing base X and the routing carrying base Y the superiors or nickel metal or palladium metal layer 52 upper surface are connected with metal wire 8 two ends respectively;
G) except that the interior pin carrying base Y bottom 12 of chip carrying base X bottom 11 and routing, all seal with plastic encapsulation body 9 periphery of interior pin carrying base Y, chip 7 and the metal wire 8 of chip bearing base X, routing.
Claims (10)
1, a kind of integrated circuit or discrete components ultra-thin non-pin packing technology is characterized in that it comprises following processing step:
1) gets a slice metal substrate (A);
2) on metal substrate (A), do China ink (B) coating, be not coated with the Nei Jiao district (C2) that the zone of doing China ink forms chip region (C1) and routing on the metal substrate;
3) on metal substrate with the Nei Jiao district (C2) of chip region (C1) and routing, carry out etching (D);
4) on the metal substrate (A1, A2) in chip region (C1) and routing Nei Jiao district (C2), dash coat layer of metal (1);
5) on the metal level (11) in chip region (C1) and routing Nei Jiao district (C2), (12), sputter layer of metal active layer (2);
6) on the metal activation floor (21) in chip region (C1) and routing Nei Jiao district (C2), (22), sputter layer of copper metal or alloy layer (3);
7) on the copper metal or alloy floor (32) in routing Nei Jiao district (C2), sputter one deck silver metal or nickel metal or palladium metal layer (52);
8) originally the dried China ink layer (B) in metal substrate (A) top divests;
9) carry out the coating of elargol (61) on the copper metal or alloy layer (31) with chip region (C1);
10) chip region (C1) that will just finish elargol coating is carried out the implantation of chip (7), carries out the operation of solidifying behind the elargol after finishing, and makes the old formula aggregate of the row semi-finished product of integrated circuit or discrete component;
11) will finish the semi-finished product that chip is implanted operation, carry out routing (8) operation;
12) will be the semi-finished product finished of routing, carry out plastic encapsulation (9) operation;
13) will finish the semi-finished product of plastic encapsulation, carry out laser printing (10) on plastic encapsulation body (9) surface;
14) will finish the semi-finished product of plastic encapsulation, and carry out underlying metal substrate (A) and divest operation;
15) will finish metal substrate and divest operation after, the colloid front with product is pasted on the blue glued membrane (E) again;
16) will finish product and be attached at blue glued membrane after, carry out plastic encapsulation body (9) and cut apart.
2, a kind of integrated circuit according to claim 1 or discrete components ultra-thin non-pin packing technology, it is characterized in that before doing China ink layer and divesting, the copper metal or alloy layer (31) that is chip region (C1) earlier goes up sputter layer of metal active layer (41) or/and layer of metal layer (51), and this metal level is silver layer or nickel dam or palladium layer.
3, a kind of integrated circuit according to claim 1 and 2 or discrete components ultra-thin non-pin packing technology, it is characterized in that on the copper metal or alloy floor (32) in routing Nei Jiao district (C2), at dash coat one deck silver metal or nickel metal or the preceding first dash coat layer of metal active layer of palladium metal layer (52) (42).
4, a kind of integrated circuit according to claim 1 or discrete components ultra-thin non-pin packing technology is characterized in that metal activation layer (2) is aluminium lamination or nickel, titanium, silver, gold layer.
5, a kind of integrated circuit according to claim 2 or discrete components ultra-thin non-pin packing technology is characterized in that metal activation layer (2) is aluminium lamination or nickel, titanium, silver, gold layer.
6, a kind of integrated circuit according to claim 3 or discrete components ultra-thin non-pin packing technology is characterized in that metal activation layer (42) is aluminium lamination or nickel, titanium, silver, gold layer.
7, a kind of integrated circuit according to claim 1 and 2 or discrete components ultra-thin non-pin packing technology, it is characterized in that finishing metal substrate layer divest operation after, carry out the product function test jobs.
8, a kind of integrated circuit or discrete components ultra-thin non-pin encapsulating structure comprise that the interior pin of chip bearing base (X), routing carries base (Y), chip (7), metal wire (8) and encapsulated layer (9), it is characterized in that:
A) bottom of the interior pin carrying base (Y) of chip bearing base (X) and routing is metal level (11,12);
B) pin carries on the metal level (11,12) of base (Y) in chip bearing base (X) and the routing, first sputter layer of metal active layer (2), sputter layer of copper metal or alloy layer (31,32) again;
C) on the copper metal or alloy layer (32) of the interior pin carrying base (Y) of routing, sputter one deck silver metal or nickel metal or palladium metal layer (52);
D) the copper metal or alloy layer (31) of chip bearing base (X) is gone up coating one deck elargol layer (61);
E) the elargol layer (61) of chip bearing base (X) is gone up and is implanted chip (7);
F) silver metal of the interior pin of the chip (7) of the superiors of chip bearing base (X) and routing carrying base (Y) the superiors or nickel metal or palladium metal layer (52) upper surface are connected with metal wire (8) two ends respectively;
G) except that interior pin carrying base (Y) bottom (12) of chip carrying base (X) bottom (11) and routing, the periphery of interior pin carrying base (Y), chip (7) and the metal wire (8) of chip bearing base (X), routing all uses plastics (9) to seal.
9, a kind of integrated circuit according to claim 8 or discrete components ultra-thin non-pin encapsulating structure, it is characterized in that at coating one deck elargol layer (61) preceding, the copper metal or alloy layer (31) that is chip region (C1) goes up first dash coat layer of metal active layer (41) or/and layer of metal layer (51), and this metal level is silver layer or nickel dam or palladium layer.
10, according to Claim 8 or 9 described a kind of integrated circuit or discrete components ultra-thin non-pin encapsulating structures, the interior pin that it is characterized in that routing carries on the copper metal layer (32) of base (Y), at dash coat one deck silver metal or nickel metal or the preceding first sputter layer of metal active layer of palladium metal layer (52) (42).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100416456A CN1295768C (en) | 2004-08-09 | 2004-08-09 | Ultrathin pinless packaging process of integrated circuit and discrete component and its packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100416456A CN1295768C (en) | 2004-08-09 | 2004-08-09 | Ultrathin pinless packaging process of integrated circuit and discrete component and its packaging structure |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100078379A Division CN100447998C (en) | 2004-08-09 | 2004-08-09 | Lead frame for integrated circuit or discrete components ultra-thin non-pin packing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1599046A CN1599046A (en) | 2005-03-23 |
| CN1295768C true CN1295768C (en) | 2007-01-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100416456A Expired - Lifetime CN1295768C (en) | 2004-08-09 | 2004-08-09 | Ultrathin pinless packaging process of integrated circuit and discrete component and its packaging structure |
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| CN (1) | CN1295768C (en) |
Cited By (1)
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| TWI453872B (en) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | Semiconductor package and fabrication method thereof |
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| CN106856179A (en) * | 2017-01-20 | 2017-06-16 | 深圳市环基实业有限公司 | A kind of new type integrated circuit packaging technology |
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| CN1599046A (en) | 2005-03-23 |
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