CN1293632C - Thin film transistor array and its driving circuit structure - Google Patents

Abstract

A thin film transistor array and its drive circuit structure is suitable for being configured on a substrate, which is mainly composed of a plurality of scanning wirings, a plurality of signal wirings, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of storage capacitors and a plurality of complementary metal oxide semiconductor transistors. The thin film transistor mainly comprises a polysilicon layer, a source/drain, an N + doped thin film, a gate and a gate insulating layer. The polycrystalline silicon layer is configured on the substrate, the source/drain electrode is configured above the polycrystalline silicon, the N + doped thin film is configured between the polycrystalline silicon layer and the source/drain electrode, the grid electrode is configured above the polycrystalline silicon, and the grid electrode insulating layer is configured between the polycrystalline silicon and the grid electrode.

Description

Thin film transistor array and its driving circuit structure

technical field

The invention relates to a thin film transistor array and its driving circuit structure, in particular to a thin film transistor array and its driving circuit structure which can be completed with six photomask manufacturing processes.

Background technique

The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor components or man-machine display devices. As far as the display is concerned, the cathode ray tube (Cathode Ray Tube, CRT) has been monopolizing the display market in recent years because of its excellent display quality and economy. However, for the environment where individuals operate most terminals/display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is used to predict that cathode ray tubes still have many problems in terms of space utilization and energy consumption, and for The demands of lightness, thinness, shortness, smallness and low power consumption cannot effectively provide a solution. Therefore, thin film transistor liquid crystal displays (TFT-LCDs) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

The well-known thin film transistors can be roughly divided into two types: amorphous silicon thin film transistors and polycrystalline silicon thin film transistors. Low-temperature polysilicon (LTPS) technology is different from the general traditional amorphous silicon (a-Si) technology. Its electron mobility can reach more than 200cm2/V-sec, so it can make the size of thin-film transistors smaller and increase the opening of the display. rate (aperture ratio), reduce power consumption and other functions. In addition, the low-temperature polysilicon manufacturing process can manufacture part of the driving circuit on the substrate together with the thin film transistor manufacturing process, which greatly improves the characteristics and reliability of the liquid crystal display panel, so the manufacturing cost is greatly reduced.

FIG. 1(A) to FIG. 1(H) are cross-sectional views of the manufacturing process of the conventional thin film transistor array and the driving circuit. Please refer to FIG. 1A , first provide a substrate 100, and form a polysilicon layer (polysilicon layer) on the substrate 100, then define the polysilicon layer with the first photomask manufacturing process (Mask 1), so that it forms a plurality of Island structures 102a, 102b, 102c of polysilicon material.

The island structure 102a is used to form a thin film transistor (TFT), and the island structure 102b and the island structure 102c are used to form a driving circuit, such as a complementary metal oxide semiconductor (CMOS). Since the island structure 102a is used to form a thin film transistor, the island structure 102a is usually arranged on the substrate 100 in an array, while the island structure 102b and the island structure 102c are usually arranged on the edge or other areas of the substrate 100 .

Next, referring to FIG. 1(B), a first dielectric layer 104 and a conductive layer (not shown in the figure) are sequentially formed on the substrate 100 formed with the island structures 102a, 102b, 102c. Then define the conductor layer with the second photomask manufacturing process (Mask 2), so as to form gates 106a, 106b, 106c on the island structures 102a, 102b, 102c respectively, and form storage devices at appropriate positions on the substrate 100. The lower electrode 108 of the capacitor.

Then please refer to FIG. 1(C), the positions of the N+ doped regions 110 and 112 are determined by the third photomask manufacturing process (Mask 3), so as to form the N+ doped regions 110 in the island structure 102a, and in the island structure An N+ doped region 112 is formed in structure 102c. Wherein, the N+ doped region 110 in the island structure 102a is distributed on both sides of the gate 106a, and the N+ doped region 112 in the island structure 102c is distributed on both sides of the gate 106c.

Then please refer to FIG. 1(D), and then determine the position of the N-doped region by the fourth photomask manufacturing process (Mask 4), so as to form the N-doped region 114 in the island structure 102a, and in the island structure N-doped regions 116 are formed in structure 102c. Wherein, the N-doped region 114 in the island structure 102a is distributed between the gate 106a and the N+ doped region 110, while the N-doped region 116 in the island structure 102c is distributed between the gate 106c and the N+ doped region 110. between N+ doped regions 112 .

Next, referring to FIG. 1(E), the position of the P+ doped region is determined by the fifth photomask manufacturing process (Mask 5), so as to form the P+ doped region 118 in the island structure 102b. Wherein, the P+ doped region 110 in the island structure 102b is distributed on both sides of the gate 106b.

1(F), a second dielectric layer 120 is formed to cover the substrate 100, and then the first dielectric layer 104 and the second dielectric layer 120 are defined by the sixth photomask manufacturing process (Mask 6). , to determine the patterns of the first dielectric layer 104 and the second dielectric layer 120 .

The first dielectric layer 104 and the second dielectric layer 120 have an opening 122 a , an opening 122 b and an opening 122 c therein. The opening 122 a exposes the N+ doped region 110 , the opening 122 b exposes the P+ doped region 118 , and the opening 122 c exposes the N+ doped region 112 .

Next, please refer to FIG. 1(G), a conductive layer (not shown in the figure) is formed to cover the second dielectric layer 120, and then the seventh photomask manufacturing process (mask 7) is used to define the above-mentioned conductive layer to form source/drain 124 . The source/drain 124 is electrically connected to the N+ doped region 110 , the exposed P+ doped region 118 and the N+ doped region 112 through the opening 122 a , the opening 122 b and the opening 122 c .

Then referring to FIG. 1(H), a flat layer 126 is formed to cover the substrate 100 on which the source/drain 124 has been formed, and then the eighth photomask manufacturing process (Mask 8) is used to define the flat layer 126, To determine the pattern of the flat layer 126 . Wherein, the flat layer 126 has an opening 128 for exposing the source/drain 124a.

After the flat layer 126 is defined by the eighth photomask manufacturing process (Mask 8), a conductive layer (not shown in the figure) is formed on the substrate 100. The conductive layer is usually a transparent material such as ITO. Finally, the ninth photomask manufacturing process (Mask 9) is used to define the above-mentioned conductive layer to form the pixel electrode 130.

Please also refer to FIG. 1(H), as can be seen from the left side of FIG. 1(H), the N-doped region 116 and the N+ doped region 112, the gate 106c, and the source/drain 124c in the island structure 102c It constitutes an N-type metal oxide semiconductor (NMOS). The P+ doped region 118 , the gate 106 b and the source/drain 124 b in the island structure 102 b constitute a P-type metal oxide semiconductor (PMOS). A complementary metal oxide semiconductor (CMOS) can be formed by the above-mentioned N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS). The role is a built-in driving circuit, which is used to drive the thin-film transistor (TFT) on the right side of FIG. 1H to control the display of the pixels.

It can be known from the right side of FIG. 1(H) that the N-doped region 110 and the N+ doped region 114, the gate 106a and the source/drain 124a in the island structure 102a constitute a polysilicon type thin film transistor (Poly-TFT). Wherein, the thin film transistor is driven by the complementary metal oxide semiconductor (CMOS) to control the data written into the pixel electrode 130 .

FIG. 2 is a flow chart showing the manufacturing process of the existing thin film transistor array and driving circuit. Please refer to FIG. 2, the manufacturing process of the existing thin film transistor array and driving circuit is mainly defined by defining the polysilicon layer S200, defining the lower electrode S202 of the gate & storage capacitor, defining the N+ doped region S204, defining the N-doped region S206, Define the P+ doped region S208, define the pattern S210 of the first dielectric layer, define the upper electrode S212 of the source/drain & storage capacitor, define the pattern S214 of the second dielectric layer, and define the pattern S216 of the pixel electrode, etc. constituted.

The existing thin-film transistor array and its driving circuit structure require a large number of photomasks for fabrication, usually requiring eight (not including the fabrication of N-doped regions 114 and 116 ) or nine photomask manufacturing processes Only then can it be completed, making it difficult to reduce the cost of the manufacturing process. In addition, due to the large number of photomasks required, the time for panel fabrication cannot be effectively shortened, and the yield rate is difficult to improve.

Contents of the invention

The object of the present invention is to propose a thin film transistor array and its driving circuit structure, which can be completed with only six photomask manufacturing processes.

In order to achieve the above object of the present invention, a thin film transistor array and its driving circuit structure are proposed, which are suitable for being arranged on a substrate, and the structure includes: a plurality of scanning wirings, arranged on the substrate; a plurality of signal wirings, arranged on the substrate; a plurality of thin film transistors, the thin film transistors are driven by the scanning lines and the signal lines, and each of the thin film transistors includes: a polysilicon layer arranged on the substrate; a The source/drain is arranged above the polysilicon; an N+ doped thin film is arranged between the polysilicon layer and the source/drain; a gate is arranged above the polysilicon; a gate insulating layer is arranged between the polysilicon and the gate; a plurality of pixel electrodes corresponding to the configuration of the thin film transistors; a plurality of storage capacitors corresponding to the configuration of the pixel electrodes; and a plurality of complementary metal oxide semiconductors, each of the complementary The metal oxide semiconductor includes an N-type metal oxide semiconductor and a P-type metal oxide semiconductor, and the gate insulating layer includes: a first dielectric layer; and a second dielectric layer disposed on the first dielectric layer. on the electrical layer.

According to the thin film transistor array and its driving circuit structure of the present invention, it is suitable to be arranged on a substrate, which is mainly composed of a plurality of scanning wiring, a plurality of signal wiring, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of storage Capacitors and a plurality of complementary metal-oxide-semiconductor transistors.

In the present invention, the thin film transistor is mainly composed of a polysilicon layer, a source/drain, an N+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the N+ doped thin film is arranged between the polysilicon layer and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is It is arranged between the polysilicon and the gate.

In the present invention, the pixel electrodes and storage capacitors are arranged on the substrate corresponding to the thin film transistors.

In the present invention, the complementary metal oxide semiconductor is composed of an N-type metal oxide semiconductor and a P-type metal oxide semiconductor. The NMOS is mainly composed of a polysilicon layer, a source/drain, an N+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the N+ doped thin film is arranged between the polysilicon and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is arranged on the between the polysilicon layer and the gate.

In addition, in the NMOS, the polysilicon layer between the gate and the source/drain further includes an N-doped region.

The P-type metal oxide semiconductor is mainly composed of a polysilicon layer, a source/drain, a P+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the P+ doped film is arranged between the polysilicon and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is arranged on the between the polysilicon layer and the gate.

The above-mentioned gate insulating layer is composed of at least one first dielectric layer, wherein the material of the first dielectric layer is, for example, silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, and the like. In addition, the gate insulating layer may also be composed of at least a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer includes silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, etc., and The material of the second dielectric layer is, for example, a photosensitive resin.

In the present invention, the material of the gate is, for example, aluminum/molybdenum, aluminum/titanium, etc., and the material of the source/drain is, for example, aluminum/molybdenum, molybdenum, etc.

For the transmissive panel, the material of the conductor layer can be a transparent conductor such as indium tin oxide. For the reflective panel, the material of the conductor layer can be selected from materials with good reflective properties such as metal. In addition, taking the reflective panel as an example, the surface of the protective layer under the conductive layer (usually a metal with good reflective ability) is for example a concave-convex surface to enhance the light reflection effect of the conductive layer.

In order to make the above objects, features, and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

1(A) to 1(H) are cross-sectional views of the manufacturing process of the existing thin film transistor array and driving circuit;

Fig. 2 is the fabrication flowchart of existing thin film transistor array and drive circuit;

3(A) to FIG. 3(I) are cross-sectional views of a thin film transistor array and a driving circuit manufacturing process according to a preferred embodiment of the present invention;

FIG. 4 is a flow chart of manufacturing a thin film transistor array and a driving circuit according to a preferred embodiment of the present invention;

FIG. 5 is a schematic layout diagram of a complementary metal oxide semiconductor (CMOS) according to a preferred embodiment of the present invention; and

FIG. 6 is a schematic diagram of a pixel layout according to a preferred embodiment of the present invention.

Detailed ways

3(A) to 3(I) are cross-sectional views of the manufacturing process of the thin film transistor array and the driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 3(A), first provide a substrate 300, and sequentially form a polysilicon layer and an N+ doped thin film on the substrate 300, and then a first photomask manufacturing process (Mask 1) defines the above-mentioned polysilicon Layers and N+ doped thin films to form a plurality of island structures formed by stacking polysilicon layers 302a, 302b, 302c and N+ doped thin films 304a, 304b, 304c.

The above-mentioned polysilicon layer is formed by, for example, first forming an amorphous silicon film (a-Si) on the substrate 300, and then performing an excimer laser annealing process (Excimer Laser Annealing, ELA) on the amorphous silicon layer, so that The amorphous silicon layer is crystallized into a polysilicon layer. The method for forming the N+ doped thin film is, for example, directly depositing an N+ doped amorphous silicon thin film on the substrate 300 by chemical vapor deposition; or forming an amorphous silicon thin film on the substrate 300 first, Then N-type ion doping is performed on the amorphous silicon to form an N+ doped film.

The island structure 302a is used to form a thin film transistor (TFT), and the island structure 302b and the island structure 302c are used to form a driving circuit, such as a complementary metal oxide semiconductor (CMOS). Since the island structure 302a is used to form a thin film transistor, the island structure 302a is, for example, arranged in an array on the substrate 300, while the island structure 302b and the island structure 302c are, for example, disposed on the edge or other regions of the substrate 300. .

Then please refer to FIG. 3(B) and FIG. 3(C), the position of the P+ doped region 306 is determined by the second photomask manufacturing process (Mask 2), and the N+ doped area is formed by the action of doping P-type ions. The P+ doped region 306 is formed in the whole region (as shown in FIG. 3(B) ) or a part of the region (as shown in FIG. 3(C )) of the impurity thin film 304b.

Next, referring to FIG. 3(D), a first conductor layer (not shown) is formed on the substrate 300, and then the third photomask manufacturing process (Mask 3) is used to define the above-mentioned first conductor layer, so as to Source/drain electrodes 308a, 308b, 308c are respectively formed on the N+ doped film 304a, the P+ doped region 306 and the N+ doped film 304c. And the lower electrode 310 of the storage capacitor is formed on a proper position of the substrate 300 .

However, when defining the first conductor layer, the third photomask manufacturing process can simultaneously define the N+ doped films 304a, 304b, 304c or the P+ doped regions 306 below the first conductor layer (FIG. 3(B), 3(C)). Therefore, the source/drain 308a will have the same pattern as the underlying N+ doped film 304a; the source/drain 308b will have the same pattern as the underlying P+ doped region 306; and the source/drain 308c will also have the same pattern. will have the same pattern as the underlying N+ doped film 304c.

Next, please refer to FIG. 3(E), a first dielectric layer (not shown in the figure) and a second conductor layer (not shown in the figure) are sequentially formed on the substrate 300, and then a fourth photomask The manufacturing process (Mask 4) defines the above-mentioned dielectric layer and the second conductive layer to form stacked structures of gate insulating layers 312a, 312b, 312c and gates 314a, 314b, 314c on the polysilicon layers 302a, 302b, 302c respectively.

In this embodiment, after the gate insulating layers 312a, 312b, 312c are formed, for example, a rapid thermal process (Rapid Thermal Process, RTP) can be performed on the gate insulating layers 312a, 312b, 312c, so that the gate insulating layers 312a, 312c The quality of 312b and 312c is further improved.

The gate insulating layers 312 a , 312 b , and 312 c are, for example, composed of at least one first dielectric layer, wherein the material of the first dielectric layer is, for example, silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, and the like. The gate insulating layers 312a, 312b, and 312c can also be composed of at least one first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer includes silicon oxide, silicon nitride, and a hydrogen-containing dielectric layer. etc., and the material of the second dielectric layer is, for example, a photosensitive resin. In addition, the materials of the gates 314a, 314b, 314c are, for example, aluminum/molybdenum, aluminum/titanium, etc., while the materials of the source/drain electrodes 308a, 308b, 308c are, for example, aluminum/molybdenum, molybdenum, etc.

Please also refer to FIG. 3(E), in the fourth photomask manufacturing process (Mask 4), a dielectric layer 316 and an upper electrode 318 will be formed on the lower electrode 310, the lower electrode 310, the dielectric layer 316 and the upper electrode 318 constitutes a storage capacitor. In addition, in the fourth photomask manufacturing process (Mask 4), a stacked structure of the dielectric layer 320 and the wiring 322 will be formed on the proper position of the substrate 300.

However, those skilled in the art should easily understand that the fabrication sequence of the gates 314a, 314b, 314c and the source/drains 308a, 308b, 308c can be adjusted according to the fabrication process. That is, in this embodiment, the fabrication sequence of the source/drain 308a, 308b, 308c and the gate 314a, 314b, 314c is not limited.

3(F), a protective layer 324 is formed on the substrate 300, and then the fifth photomask manufacturing process (Mask 5) is used to define the protective layer 324 to determine the pattern of the protective layer 324. For example, the protective layer 324 has openings 326 a , 326 b , 326 c , 326 d , and 326 e therein. Wherein, the opening 326a is used to expose the source/drain 308a, the opening 326b is used to expose the source/drain 308b, the opening 326c is used to expose the source/drain 308c, and the opening 326d is used to expose The upper electrode 318 of the storage capacitor is exposed, and the opening 326e is used to expose the wiring 322 .

Then please refer to FIG. 3(G), after defining the protective layer 324 with the fifth photomask manufacturing process (Mask 5), a conductive layer (not shown in the figure) is then formed on the substrate 300. This conductive layer is usually Transparent materials such as indium tin oxide. Finally, the above-mentioned conductive layer is defined by the sixth photomask manufacturing process (Mask 6) to form the wire 328 and the pixel electrode 330.

Then please refer to Fig. 3(H) and Fig. 3(I), which are similar to Fig. 3(F) and 3(G), except that one is a penetrating panel (Fig. 3(H) and Fig. (I)), and the other is a reflective panel (Fig. 3(F) and Fig. 3(G)). The protection layer 324 in FIG. 3(H) and FIG. 3(I) has a concave-convex surface 332, and the pixel electrodes 334 disposed on the concave-convex surface 332 are, for example, selected conductors with good effects. The light reflection effect of the pixel electrode 334 (reflective electrode) can be enhanced by the concave-convex surface 332 on the protective layer 324 .

Then please refer to FIG. 3(G) and FIG. 3(I) at the same time. From the left side of FIG. 3(G) and FIG. , the gate insulating layer 312c and the gate 314c constitute an N-type metal oxide semiconductor (NMOS). The polysilicon layer 302b, the P+ doped thin film 306, the source/drain 308b, the gate insulating layer 312b and the gate 314b constitute a P-type metal oxide semiconductor (PMOS). A complementary metal oxide semiconductor (CMOS) can be formed by the above-mentioned N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS). The role played by the complementary metal oxide semiconductor on the panel is a The built-in driving circuit is used to drive the thin film transistors on the right side of FIG. 3(G) and FIG. 3(I), and then control the display of the pixels.

3(G) and the right side of FIG. 3(I), it can be seen that the polysilicon layer 302a, the N+ doped film 304a, the source/drain 308a, the gate insulating layer 312a and the gate 314a constitute a polysilicon type thin film transistors. Wherein, the thin film transistor controls the data written into the pixel electrode 330 or the pixel electrode 334 by driving the CMOS.

FIG. 4 is a flow chart illustrating the fabrication of a thin film transistor array and a driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 4, the manufacturing process of the thin film transistor array and the driving circuit in this embodiment is mainly defined by defining the polysilicon layer S400, defining the P+ doped region S402, defining the source/drain & N+ doped film etch back & the lower electrode of the storage capacitor S404, defining the upper electrode of the gate & storage capacitor S406, defining the pattern of the protective layer S408, and defining the pattern of the pixel electrode & wire S410. A total of six photomask manufacturing processes are required from S400 to S410 . However, if an N-doped region (lightly doped region) is formed in the N-type metal oxide semiconductor (NMOS) in the driving circuit, another photomask manufacturing process needs to be added.

FIG. 5 is a schematic diagram of a CMOS layout in a driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 5, apply voltages Vin, Vdd, and Vss to the contacts 504, 506, and 508 respectively. Since the contact 504 is electrically connected to the gate 500 and the gate 502, Vin applied to the contact 504 can be used to control the N-type Whether the conduction of the metal oxide semiconductor and the P-type metal oxide semiconductor channel layer is conducted, and whether the conduction of the N-type metal oxide semiconductor and the P-type metal oxide semiconductor channel layer will directly affect the complementary metal oxide semiconductor. The output Vout of the contact 510, and the value of Vout output by the contact 510 may be one of Vdd or Vss.

However, the driving circuit shown in FIG. 5 is only a schematic layout diagram of a CMOS unit, and those who are familiar with this technology should understand that the driving circuit on the panel can be composed of the above-mentioned CMOS with other circuits. or elements to drive the pixel array on the panel.

FIG. 6 is a schematic diagram of a pixel layout according to a preferred embodiment of the present invention. Please refer to FIG. 6 , the pixel structure produced by the six photomask manufacturing processes in FIG. 3(A) to FIG. 3(I) mainly includes a scanning wiring 600, a signal wiring 602, a thin film transistor 604, A storage capacitor 606 and a pixel electrode 330 (334) are formed. Wherein, the TFT 604 is mainly composed of a polysilicon layer 302a, a gate 314a, an N+ doped film 304a, and a source/drain 308a. In addition, the scanning wiring 600 is connected to the gate 314a of the thin film transistor 604 to control the switch of the lower channel layer (polysilicon layer 302a), and the data to be written is transmitted through the signal wiring 602 and the thin film transistor 604 is written into the pixel electrode 330 (334) under the control.

In summary, the thin film transistor array and its driving circuit structure of the present invention have at least the following advantages:

1. The thin film transistor array and its driving circuit structure of the present invention can be completed with only six photomasks in production, so that the production cost is greatly reduced.

2. The thin film transistor array and its driving circuit structure of the present invention use fewer photomasks during fabrication, which greatly shortens the panel fabrication time.

3. The thin film transistor array and its driving circuit structure of the present invention use fewer photomasks in its production, which helps to improve the yield of the panel.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention.

Claims (10)

1. A thin film transistor array and its drive circuit structure are suitable for being configured on a substrate, characterized in that the structure comprises: A plurality of scanning wirings are arranged on the substrate; A plurality of signal wirings are arranged on the substrate; A plurality of thin film transistors, the thin film transistors are driven by the scanning lines and the signal lines, each of the thin film transistors includes: a polysilicon layer configured on the substrate; a source/drain configured on the polysilicon; an N+ doped thin film disposed between the polysilicon layer and the source/drain; a gate configured on the polysilicon; a gate insulating layer configured between the polysilicon and the gate; A plurality of pixel electrodes, corresponding to the thin film transistor configurations: a plurality of storage capacitors corresponding to the pixel electrode configurations; and A plurality of complementary metal oxide semiconductors, each of which includes an N-type metal oxide semiconductor and a P-type metal oxide semiconductor, Wherein, the gate insulating layer includes: a first dielectric layer; and A second dielectric layer is configured on the first dielectric layer. 2. The thin film transistor array and its driving circuit structure according to claim 1, wherein the N-type metal oxide semiconductor comprises: a second polysilicon layer configured on the substrate; a second source/drain configured above the second polysilicon; a second N+ doped thin film disposed between the second polysilicon and the second source/drain; a second gate configured on the second polysilicon; and A second gate insulation layer is disposed between the second polysilicon layer and the second gate. 3 . The thin film transistor array and its driving circuit structure as claimed in claim 1 , wherein the polysilicon layer between the gate and the source/drain further includes an N-doped region. 4 . 4. The thin film transistor array and its drive circuit structure according to claim 1, wherein the P-type metal oxide semiconductor comprises: a third polysilicon layer configured on the substrate; a third source/drain configured above the third polysilicon; a P+ doped thin film disposed between the third polysilicon and the third source/drain; a third gate configured on the third polysilicon; and A third gate insulation layer is disposed between the third polysilicon layer and the third gate. 5. The thin film transistor array and its driving circuit structure according to claim 1, wherein the gate insulating layer comprises a dielectric layer, and the material of the dielectric layer comprises silicon oxide, silicon nitride, containing One of the dielectric layers of hydrogen. 6. The thin film transistor array and its driving circuit structure according to claim 5, wherein the material of the first dielectric layer comprises one of silicon oxide, silicon nitride, and a hydrogen-containing dielectric layer, and The material of the second dielectric layer includes a photosensitive resin. 7. The thin film transistor array and its driving circuit structure according to claim 1, wherein the material of the gate comprises one of aluminum/molybdenum and aluminum/titanium. 8 . The thin film transistor array and its driving circuit structure according to claim 1 , wherein the material of the source/drain includes one of aluminum/molybdenum and molybdenum. 9. The thin film transistor array and its driving circuit structure according to claim 1, wherein the pixel electrode is a transparent electrode, and the material of the pixel electrode includes indium tin oxide. 10. The thin film transistor array and its driving circuit structure according to claim 1, wherein the pixel electrode is a reflective electrode, and the material of the pixel electrode includes metal.

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