CN112875641B - Integrated structure of MEMS device and circuit device and manufacturing method thereof - Google Patents
Integrated structure of MEMS device and circuit device and manufacturing method thereof Download PDFInfo
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0035—Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0045—Packages or encapsulation for reducing stress inside of the package structure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00277—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00325—Processes for packaging MEMS devices for reducing stress inside of the package structure
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides an integrated structure of an MEMS device and a circuit device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer; forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion; providing an upper substrate, forming the upper substrate on the device layer by bonding technology to form a sealed cavity for accommodating the movable part of the micromechanical structure; and forming a circuit device in the upper substrate. The MEMS device and the circuit device are monolithically integrated, so that the integration level is improved, and the process complexity and the manufacturing cost are reduced.
Description
Technical Field
The present invention relates to the field of microelectromechanical systems, and more particularly, to an integrated structure of a MEMS device and a circuit device, and a method for manufacturing the same.
Background
The field of microelectromechanical systems (Micro Electro Mechanical System, abbreviated MEMS) relates to the technology of manufacturing microelectromechanical devices and nanoelectromechanical devices. In particular, the techniques may be applied to fabricating high performance processing circuitry and mems devices or nanoelectromechanical system devices on the same substrate. For example, MEMS speedometers, gyroscopes, microphones, resonators, and the like all employ fabrication techniques in the MEMS field. MEMS fabrication techniques, like IC (Integrated Circuit) fabrication techniques, are applied to high precision processing such as photolithography, implantation, etching, and the like, while specialized MEMS fabrication techniques such as bulk silicon etching, mask layer release, and the like, are required to form three-dimensional mechanical structures such as beams, bridges, films, and the like, typically on a single crystal silicon substrate, with dimensions on the order of microns, even nanometers.
These tiny mechanical structures often require a receiving cavity TO provide mechanical protection, such as using a TO-8 package TO seal the micromechanical structure into the cavity by a metal soldering process, or by bonding it TO a substrate with a cavity for receiving the mechanical structure. These methods are difficult to be compatible with low cost manufacturing processes for high performance circuits, thereby achieving monolithically integrated MEMS microsystem products. In particular, where MEMS structures are required to operate in a vacuum environment, these approaches fail to provide a process for monolithically integrating with circuitry.
Disclosure of Invention
In view of this, the present invention proposes an integrated structure of a MEMS device and a circuit device and a method for manufacturing the same, so as to implement monolithic integration of the MEMS device and the circuit device, improve the integration level of the device, and reduce the complexity of the process.
According to a first aspect of the present invention, a method for manufacturing an integrated structure of a MEMS device and a circuit device is provided, which includes: providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer; forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion; providing an upper substrate, forming the upper substrate on the device layer by bonding technology to form a sealed cavity for accommodating the movable part of the micromechanical structure; and forming a circuit device in the upper substrate.
Preferably, a conductive via is formed in the upper substrate to connect to the micromechanical structure to electrically connect the micromechanical structure out of the cavity.
Preferably, the method of forming the micromechanical structure comprises: forming a first dielectric layer on the substrate; forming patterned photoresist, and etching the first dielectric layer and the device layer to the top of the insulating layer by taking the patterned photoresist as a mask so as to form a plurality of grooves in the device layer; and removing portions of the first dielectric layer and the insulating layer to form the micromechanical structure.
Preferably, before forming the patterned photoresist, the method further includes forming a patterned mask layer on the first dielectric layer, the patterned mask layer having at least a first window forming a movable portion of the micromechanical structure, the patterned photoresist being located at least on the first dielectric layer exposed by the first window.
Preferably, the method for removing part of the first dielectric layer and the insulating layer includes: and removing the first dielectric layer and the insulating layer by adopting the patterned mask layer as a protective layer and adopting a corrosion method at least until the first dielectric layer on the upper surface of the movable part of the micromechanical structure and the insulating layer on the lower surface of the first dielectric layer are completely removed.
Preferably, the method further comprises removing the patterned mask layer.
Preferably, the method of forming the conductive path includes: forming a first contact hole exposing the first dielectric layer in the upper substrate; forming a second dielectric layer on the inner surface of the first contact hole and the upper surface of the upper substrate; removing the first dielectric layer at the bottom of the first contact hole; and depositing a first conductive material in the first contact hole with the side wall covered with the second dielectric layer and part of the upper surface of the upper substrate to form the conductive channel.
Preferably, the method of forming the circuit device includes forming a well region of a first doping type in the upper substrate; forming a gate conductor on the second dielectric layer; and forming a drain region of the second doping type and a source region of the second doping type in the well region by a self-aligned ion implantation process.
Preferably, the well region is formed before the second dielectric layer is formed.
Preferably, the second dielectric layer is used as a gate dielectric layer of the circuit device.
Preferably, the first conductive material and the gate conductor are formed in a simultaneous process.
Preferably, the method of forming the first conductive material and forming the gate conductor comprises: depositing a conductive layer in the first contact hole and on the upper surface of the upper substrate; and a selective etching part is positioned on the conductive layer on the upper surface of the upper substrate to form the first conductive material and a gate conductor positioned above the well region.
Preferably, the method further comprises: forming a third dielectric layer on the second dielectric layer and the gate conductor in the conductive channel; forming second contact holes in the third dielectric layer, wherein the second contact holes are respectively partially exposed out of the conductive channels, the gate conductor, the drain region and the source region; and depositing a second conductive material in the second contact hole.
Preferably, the upper substrate is a silicon substrate, and the first dielectric layer is silicon oxide.
Preferably, the upper substrate is bonded to the upper surface of the first dielectric layer by a silicon-silicon fusion bonding technique.
Preferably, before forming the conductive via, the method further comprises thinning the upper substrate using a chemical mechanical polishing process.
Preferably, the upper substrate is thinned to 10-15um.
Preferably, the patterned mask layer is a silicon nitride layer.
Preferably, the device layer is etched using a deep silicon etch process.
Preferably, the first dielectric layer and the insulating layer are etched using hydrofluoric acid or a buffer oxide etchant in a gaseous state.
Preferably, the first conductive material is highly doped polysilicon or conductive metal.
Preferably, the thickness of the device layer ranges from 5 to 15um.
Preferably, the substrate is an SOI substrate.
According to a second aspect of the present invention, there is provided an integrated structure of a MEMS device and a circuit device, comprising: a substrate including a lower support layer, an upper device layer, and an insulating layer between the support layer and the device layer, the device layer including therein a micromechanical structure including a fixed portion and a movable portion; a first dielectric layer at least located on the upper surface of the fixed portion of the micromechanical structure; the upper substrate is bonded on the first dielectric layer through a bonding technology; and a circuit device in the upper substrate, wherein the upper substrate and the substrate form a sealed cavity for accommodating the movable portion of the micromechanical structure.
Preferably, a conductive channel is further included in the upper substrate for electrically connecting the micromechanical structure outside the cavity.
Preferably, the movable part of the micromechanical structure comprises at least two separated suspended structures, the first dielectric layer is not included between the upper surface of the movable part of the micromechanical structure and the upper substrate, and the insulating layer is not included between the lower surface of the movable part of the micromechanical structure and the supporting layer.
Preferably, the fixed part of the micromechanical structure is connected to at least one suspended structure of the movable part of the micromechanical structure.
Preferably, the movable part of the micromechanical structure is located between the fixed parts of the micromechanical structure.
Preferably, the conductive via includes a first contact hole in the upper substrate and a first conductive material filling the first contact hole and located on at least an upper surface of the upper substrate.
Preferably, the semiconductor device further comprises a second dielectric layer positioned on the side wall of the first contact hole and the upper surface of the upper substrate.
Preferably, the circuit device includes; a well region of a first doping type in the upper substrate; a gate conductor on the second dielectric layer; and a source region of a second doping type and a drain region of the second doping type located in the well region.
Preferably, the semiconductor device further comprises a third dielectric layer located on the conductive channel, the second dielectric layer and the gate conductor.
Preferably, the first dielectric layer is silicon oxide.
Preferably, the upper substrate is a silicon substrate.
Preferably, the first conductive material is highly doped polysilicon or conductive metal.
Preferably, the thickness of the upper substrate ranges from 10 um to 15um.
Preferably, the thickness of the device layer ranges from 5 to 15um.
Preferably, the substrate is an SOI substrate.
According to the manufacturing method of the integrated structure of the MEMS device and the circuit device, a substrate comprising a device layer, an insulating layer and a supporting layer is provided, and the device layer is etched to form a micro-mechanical structure; bonding an upper substrate to the substrate by bonding to form a sealed cavity for accommodating the movable portion of the micromechanical structure; finally, a circuit device is formed in the upper substrate, and a conductive channel is formed to electrically connect the micromechanical structure to outside the cavity. The cavity formed by the bonding method has low tensile stress, can regulate the environmental pressure in the cavity, and has the sealing performance which is not degraded in the subsequent process, and the performance of the micromechanical structure in the cavity is not affected. In addition, the MEMS device and the circuit device are monolithically integrated, so that the circuit device and the MEMS device with high performance are manufactured on the same substrate, the integration level is improved, and the process complexity and the manufacturing cost are reduced.
Drawings
FIG. 1 is a cross-sectional view of an integrated structure of a MEMS device and a circuit device according to an embodiment of the invention;
fig. 2A-2J are partial, staged, cross-sectional views of a method of fabricating an integrated structure of a MEMS device and a circuit device in accordance with an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the invention, such as structures, materials, dimensions, processing and techniques for each component, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 is a cross-sectional view of an integrated structure of a MEMS device and a circuit device according to an embodiment of the present invention.
The integrated structure includes a substrate, a micromechanical structure, a first dielectric layer 11, an upper substrate 12, a circuit device, and a conductive via 30a. Wherein the substrate comprises a lower support layer 10a, an upper device layer 10b and an insulating layer 10c between the support layer 10a and the device layer 10b, the micromechanical structure comprising fixed parts 21, 22 and movable parts is comprised in the device layer 10 b. The first dielectric layer 11 is located at least on the upper surface of the fixed part of the micromechanical structure, and in this embodiment, the first dielectric layer 11 is also located on the other part 23 of the device layer 10 b. The upper substrate 12 is bonded to the first dielectric layer 11 by a bonding technique, and the upper substrate 12 and the substrate form a sealed cavity for accommodating the movable portion of the micromechanical structure. The conductive channel 30a is located in the upper substrate for electrically connecting the micromechanical structure outside the cavity. The circuit device is located in the upper substrate 12. In this embodiment, the substrate is an SOI (silicon-on-insulator) substrate, the support layer 10a and the device layer 10b are semiconductor silicon materials, and the insulating layer 10c is silicon dioxide. The first dielectric layer 11 is silicon oxide, the upper substrate 12 is a silicon substrate, and the upper substrate 12 and the first dielectric layer 11 are bonded by silicon-silicon bonding. Wherein, the thickness of the upper substrate 12 is 10-15um. The thickness of the device layer 10b ranges from 5 to 15um, and the doping resistivity of the device layer 10b ranges from 1ohm.cm to 0.01ohm.cm.
The movable part of the micro-mechanical structure comprises at least two separated suspended structures, a first dielectric layer is not included between the upper surface of the movable part of the micro-mechanical structure and the upper substrate, and an insulating layer is not included between the lower surface of the movable part of the micro-mechanical structure and the supporting layer. In this embodiment, the movable portion of the micromechanical structure comprises three separate suspended structures, 20a,20b,20c, respectively. The fixed part of the micromechanical structure is also partially suspended, in particular, the edge part of the fixed part of the micromechanical structure is suspended.
The fixed parts 21, 22 of the micromechanical structure are connected to at least one suspended structure of the movable part of the micromechanical structure. In the present embodiment, the fixed portion 21 of the micromechanical structure is connected to the movable portions 20a and 20c, and the fixed portion 22 of the micromechanical structure is connected to the movable portion 20 b. The movable parts 20a,20b,20c of the micromechanical structure are located between the fixed parts 21 and 22 of the micromechanical structure. The fixed portion 21 of the micromechanical structure is spaced apart from the other portions 23 of the device layer 10 b. It should be noted that the connection of the fixed part and the movable part of the micromechanical structure is not limited to the manner disclosed in the present invention, and those skilled in the art can connect according to actual process and device requirements, and are not limited in any way herein.
The conductive via 30a includes a first contact hole in the upper substrate 12 and a first conductive material filling the first contact hole and on a portion of the upper surface of the upper substrate. In this embodiment, the conductive channel 30a extends to the upper surface of the fixed portion of the micromechanical structure to electrically connect the micromechanical structure outside the cavity. The side walls of the first contact hole and the upper surface of the upper substrate further include a second dielectric layer 13, where the second dielectric layer in the first contact hole is used to isolate the conductive channel from other device structures or conductive structures in the upper substrate 12. The first conductive material is highly doped polysilicon or conductive metal.
Wherein the circuit device comprises a well region 31 of a first doping type in the upper substrate; a gate conductor 30b located on the second dielectric layer 13; and a source region 32 of a second doping type and a drain region 32 of a second doping type located in the well region 31. The integrated structure further comprises a third dielectric layer 15 on the conductive via 30a, the second dielectric layer 13 and the gate conductor 30b; the second contact holes are positioned in the third dielectric layer 15 and respectively partially expose the conductive channels 30a, the gate conductors 30b, the source regions 32 and the drain regions 32; and a second conductive material (not shown) in the second contact hole.
The first doping type is one of N type and P type, and the second doping type is the other of N type and P type.
Fig. 2A-2H are partial, staged, cross sectional views of a method of fabricating an integrated structure of a MEMS device and a circuit device in accordance with an embodiment of the present invention.
As shown in fig. 2A, a substrate is provided, and in this embodiment, the substrate slice is an SOI substrate. The SOI substrate includes a lower support layer 10a, an upper device layer 10b, and an insulating layer 10c between the support layer 10a and the device layer 10 b. Wherein the support layer 10a and the device layer 10b are made of semiconductor silicon material, the insulating layer 10c is made of silicon dioxide, the doping resistivity of the device layer 10b is preferably 1 ohm.cm-0.01 ohm.cm, and the thickness of the device layer 10b is preferably 5-15um.
As shown in fig. 2B, a first dielectric layer 11 is grown on the SOI substrate, and then a mask layer is formed on the first dielectric layer 11. The thickness of the first dielectric layer is preferably 1um, and the thickness of the mask layer is preferably 0.25um. The mask layer is then patterned, using conventional photolithography, etching processes, to obtain a patterned mask layer having at least windows 1201 forming movable portions of subsequent micromechanical structures. In this embodiment, the mask layer further includes a window 1202 for subsequently forming a trench separating the fixed portion of the micromechanical structure from other portions of the device layer. The etching process of this step is preferably a wet etching process. The first dielectric layer 11 is selected to be an oxide layer, preferably silicon oxide.
As shown in fig. 2C, a patterned photoresist (not shown in the drawing) is formed at least in the window 1201, and the first dielectric layer 11 and the device layer 10b are etched up to the upper surface of the insulating layer 10C with the patterned photoresist as a mask layer to form a plurality of trenches in the device layer 10 b. The etching process for etching the device layer 10b in this step is a deep silicon etching process, which is a dry etching process, and can form nearly vertical sidewalls. The process of etching the first dielectric layer 11 in this step is a wet etching process.
As shown in fig. 2D, the first dielectric layer 11 and the insulating layer 10c are etched with the patterned mask layer as a protective layer to form a micromechanical structure including movable portions 20a,20b, and 20c and fixed portions 21 and 22. Wherein the first dielectric layer 11 and the insulating layer 10c are etched at least until the first dielectric layer 11 on the upper surface of the movable part of the micromechanical structure and the insulating layer 10c on the lower surface thereof are completely removed. In this embodiment, a Buffered Oxide Etchant (BOE) or VHF (vapour HF acid) is used for etching, wherein the gaseous hydrofluoric acid, VHF, does not cause the structure to adhere to the support layer after etching. And finally removing the patterned mask layer.
As shown in fig. 2E, an upper substrate 12 is provided, and the upper substrate 12 is bonded to the first dielectric layer 11 to form a closed cavity with the substrate to accommodate the movable portion of the micromechanical structure. In this embodiment, the upper substrate 12 is preferably made of silicon, and the upper substrate 12 may be bonded to the first dielectric layer 11 by a silicon-silicon fusion bonding technique, and the bonding temperature is about 1100-1300 ℃, preferably 1200 ℃. Because of the silicon-silicon bonding, the thermal mismatch ratio of the materials is small, so that the stress of a bonding interface is small, and the bonding is very firm. In addition, by adjusting the environment of the bonding process, the type and pressure of the environmental gas in the cavity can be correspondingly adjusted, so that the cavity contains fluid with certain pressure to provide damping required by the work of the device. During operation, a part or parts of the micromechanical structure may perform a relevant movement within the cavity.
As shown in fig. 2F, the upper substrate 12 is thinned to a desired thickness for subsequent fabrication. The required thickness is preferably 10-15um. This thinning is typically achieved by a CMP (Chemical Mechanical Polishing ) process that results in a very flat and smooth surface after thinning, and thus allows for fabrication of circuit devices on this surface.
As shown in fig. 2G, a well region 31 is formed in the upper substrate 12, the well region 31 is formed using an ion implantation process, and then impurities are diffused into the upper substrate by high temperature diffusion. The well region 31 is a well region of the first doping type. Then, an etching process is used to form a first contact hole 14 in the upper substrate 12, and the first contact hole 14 exposes the upper surface of the first dielectric layer 11. Since the etching rate of the first dielectric layer 11 is low, the etching process can be self-stopped. The etching process of this step may be a dry etching process. In this embodiment, the first contact hole is formed after the step of forming the well region 31. Of course, in other embodiments, the first contact hole may also be formed before the step of forming the well region 31, which is not limited herein.
As shown in fig. 2H, a second dielectric layer 13 is formed on the inner surface of the first contact hole 14 and the upper surface of the upper substrate 12. The second dielectric layer 13 also covers the upper surface of the well region 31. In this embodiment, the second dielectric layer 13 is formed by a thermal oxidation growth or deposition process.
As shown in fig. 2I, the first dielectric layer 11 at the bottom of the first contact hole is removed, and a first conductive material is deposited in the first contact hole and on the upper surface of the second dielectric layer 13 on the upper substrate 12. And etching the first conductive material on the upper surface of the second dielectric layer on the upper substrate to form a conductive channel 30a and a gate conductor 30b. The conductive channel is used for electrically connecting the micromechanical structure to the outside of the cavity, the gate conductor is located above the well region 31, the second dielectric layer 13 below the gate conductor is a gate dielectric layer of the circuit device, and the second dielectric layer in the first contact hole is also used for isolating the conductive channel from other device structures or conductive structures in the upper substrate 12. In this embodiment, the first conductive material may be selected to be highly doped polysilicon or a conductive metal material.
As shown in fig. 2J, a source region 32 and a drain region 32 of a second doping type are formed in the well region 31, the source region 32 and the drain region 32 being formed by a self-aligned ion implantation process. In this embodiment, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
As shown in fig. 1, the method further includes forming a third dielectric layer 15 on the conductive channel 30a, the gate conductor 30b and the second dielectric layer 13, and forming second contact holes in the third dielectric layer 15 to partially expose the conductive channel 30a, the gate conductor 30b, the source region 32 and the drain region 32, respectively; finally, a second conductive material (not shown) is deposited in the second contact hole to lead out the microstructure and the electrodes of the circuit device.
According to the method for manufacturing the MEMS device, firstly, a substrate comprising a device layer, an insulating layer and a supporting layer is provided, and the device layer is etched to form a micro-mechanical structure; bonding an upper substrate to the substrate by bonding to form a sealed cavity for accommodating the movable portion of the micromechanical structure; finally, a circuit device is formed in the upper substrate, and a conductive channel is formed to electrically connect the micromechanical structure to outside the cavity. The cavity formed by the bonding method has low tensile stress, can regulate the environmental pressure in the cavity, and has the sealing performance which is not degraded in the subsequent process, and the performance of the micromechanical structure in the cavity is not affected. In addition, the MEMS device and the circuit device are monolithically integrated, so that the circuit device and the MEMS device with high performance are manufactured on the same substrate, the integration level is improved, and the process complexity and the manufacturing cost are reduced.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (38)
1. A method of fabricating an integrated structure of a MEMS device and a circuit device, comprising:
providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer;
forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion;
providing an upper substrate, forming the upper substrate on the device layer by bonding technology to form a sealed cavity for accommodating the movable part of the micromechanical structure; and
a circuit device is formed in the upper substrate,
the method further comprises forming a patterned first dielectric layer on the substrate, wherein the upper substrate is bonded to the upper surface of the first dielectric layer through a silicon-silicon fusion bonding technology.
2. The method of claim 1, further comprising forming a conductive via in the upper substrate connected to the micromechanical structure to electrically connect the micromechanical structure outside the cavity.
3. The method of claim 2, wherein the method of forming the micromechanical structure comprises:
forming a first dielectric layer on the substrate;
forming patterned photoresist, and etching the first dielectric layer and the device layer to the top of the insulating layer by taking the patterned photoresist as a mask so as to form a plurality of grooves in the device layer; and
portions of the first dielectric layer and the insulating layer are removed to form the micromechanical structure.
4. The method of claim 3, wherein prior to forming the patterned photoresist, the method further comprises forming a patterned masking layer on the first dielectric layer, the patterned masking layer having at least a first window forming a movable portion of the micromechanical structure, the patterned photoresist being located on at least the first dielectric layer exposed by the first window.
5. The method of claim 4, wherein removing portions of the first dielectric layer and the insulating layer comprises: and removing the first dielectric layer and the insulating layer by adopting the patterned mask layer as a protective layer and adopting a corrosion method at least until the first dielectric layer on the upper surface of the movable part of the micromechanical structure and the insulating layer on the lower surface of the first dielectric layer are completely removed.
6. The method of claim 5, wherein the method further comprises removing the patterned mask layer.
7. A method according to claim 3, wherein the method of forming the conductive channel comprises:
forming a first contact hole exposing the first dielectric layer in the upper substrate;
forming a second dielectric layer on the inner surface of the first contact hole and the upper surface of the upper substrate;
removing the first dielectric layer at the bottom of the first contact hole; and
and depositing a first conductive material in the first contact hole with the side wall covered with the second dielectric layer and part of the upper surface of the upper substrate to form the conductive channel.
8. The method of claim 7, wherein forming the circuit device comprises:
forming a well region of a first doping type in the upper substrate;
forming a gate conductor on the second dielectric layer; and
a self-aligned ion implantation process forms a drain region of a second doping type and a source region of a second doping type in the well region.
9. The method of claim 8, wherein the well region is formed prior to forming the second dielectric layer.
10. The method of claim 8, wherein the second dielectric layer serves as a gate dielectric layer for the circuit device.
11. The method of claim 8, wherein the first conductive material and the gate conductor are formed in a simultaneous process.
12. The method of claim 8, wherein forming the first conductive material and forming the gate conductor comprises:
depositing a conductive layer in the first contact hole and on the upper surface of the upper substrate; and
and a selective etching part is positioned on the conductive layer on the upper surface of the upper substrate to form the first conductive material and a gate conductor positioned above the well region.
13. The method of claim 8, wherein the method further comprises:
forming a third dielectric layer on the second dielectric layer and the gate conductor in the conductive channel;
forming second contact holes in the third dielectric layer, wherein the second contact holes are respectively partially exposed out of the conductive channels, the gate conductor, the drain region and the source region; and
and depositing a second conductive material in the second contact hole.
14. The method of claim 3, wherein the upper substrate is a silicon substrate and the first dielectric layer is silicon oxide.
15. The method of claim 14, wherein the upper substrate is bonded to the first dielectric layer upper surface by a silicon-silicon fusion bonding technique.
16. The method of claim 2, wherein prior to forming the conductive via, further comprising thinning the upper substrate using a chemical mechanical polishing process.
17. The method of claim 16, wherein the upper substrate is thinned to 10-15um.
18. The method of claim 4, wherein the patterned masking layer is a silicon nitride layer.
19. The method of claim 3, wherein the device layer is etched using a deep silicon etch process.
20. The method of claim 5, wherein the first dielectric layer and the insulating layer are etched with hydrofluoric acid or a buffered oxide etchant in a gaseous state.
21. The method of claim 7, wherein the first conductive material is highly doped polysilicon or a conductive metal.
22. The method of claim 1, wherein the device layer has a thickness in the range of 5-15um.
23. The method of claim 1, wherein the substrate is an SOI substrate.
24. An integrated structure of a MEMS device and a circuit device, comprising:
a substrate including a lower support layer, an upper device layer, and an insulating layer between the support layer and the device layer, the device layer including therein a micromechanical structure including a fixed portion and a movable portion;
a first dielectric layer at least located on the upper surface of the fixed portion of the micromechanical structure;
the upper substrate is bonded on the first dielectric layer through a silicon-silicon fusion bonding technology; and
a circuit device located in the upper substrate,
wherein the upper substrate and the substrate form a sealed cavity for accommodating the movable portion of the micromechanical structure.
25. The integrated structure of claim 24, further comprising conductive vias in the upper substrate to electrically connect the micromechanical structure outside the cavity.
26. The integrated structure of claim 24, wherein the movable portion of the micromechanical structure comprises at least two separate suspended structures that do not comprise a first dielectric layer between an upper surface of the movable portion of the micromechanical structure and the upper substrate, and wherein the lower surface of the movable portion of the micromechanical structure does not comprise an insulating layer between the lower surface of the movable portion of the micromechanical structure and the support layer.
27. The integrated structure of claim 24, wherein the fixed portion of the micromechanical structure is coupled to at least one suspended structure of the micromechanical structure movable portion.
28. The integrated structure of claim 24, wherein the movable portion of the micromechanical structure is located between the fixed portions of the micromechanical structure.
29. The integrated structure of claim 25, wherein the conductive via comprises a first contact hole in the upper substrate and a first conductive material filling the first contact hole and located on at least an upper surface of the upper substrate.
30. The integrated structure of claim 29, further comprising a second dielectric layer on sidewalls of the first contact hole and an upper surface of the upper substrate.
31. The integrated structure of claim 30, wherein the circuit device comprises;
a well region of a first doping type in the upper substrate;
a gate conductor on the second dielectric layer; and
a source region of a second doping type and a drain region of the second doping type located in the well region.
32. The integrated structure of claim 31, further comprising a third dielectric layer on the conductive via, the second dielectric layer, and the gate conductor.
33. The integrated structure of claim 24 wherein the first dielectric layer is silicon oxide.
34. The integrated structure of claim 24, wherein the upper substrate is a silicon substrate.
35. The integrated structure of claim 29, wherein the first conductive material is highly doped polysilicon or a conductive metal.
36. The integrated structure of claim 24, wherein the upper substrate has a thickness in the range of 10-15um.
37. The integrated structure of claim 24, wherein the device layer has a thickness in the range of 5-15um.
38. The integrated structure of claim 24, wherein the substrate is an SOI substrate.
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