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CN112635458B - Silicon controlled rectifier and manufacturing method thereof - Google Patents

Silicon controlled rectifier and manufacturing method thereof Download PDF

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Publication number
CN112635458B
CN112635458B CN202011095029.4A CN202011095029A CN112635458B CN 112635458 B CN112635458 B CN 112635458B CN 202011095029 A CN202011095029 A CN 202011095029A CN 112635458 B CN112635458 B CN 112635458B
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concentration
doped region
type doped
well
width
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CN112635458A (en
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朱天志
黄冠群
陈昊瑜
邵华
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a silicon controlled rectifier, comprising: the N well and the P well are formed on the upper part of the P type semiconductor substrate; the first high-concentration P-type doped region and the first high-concentration N-type doped region are formed at the upper part of the N well; the second high-concentration P-type doped region and the second high-concentration N-type doped region are formed at the upper part of the P well; the third high-concentration P-type doped region is formed above the boundary of the N well and the P well. The invention also provides a manufacturing method of the silicon controlled rectifier. The invention can reduce the efficiency of injecting electrons from the N-type doped region with extremely high concentration of the parasitic NPN and reaching the P well/N well interface, so that the current gain of the parasitic NPN triode can be reduced, the product of the PNP of the parasitic triode and the current gain of the NPN triode can be further reduced, the key size of the device required for realizing no hysteresis effect can be reduced, the whole size of the device can be reduced, and the layout area can be saved.

Description

Silicon controlled rectifier and manufacturing method thereof
Technical Field
The invention relates to the field of integrated circuit production and manufacturing, in particular to a silicon controlled rectifier without hysteresis effect. The invention also relates to a manufacturing method of the silicon controlled rectifier without hysteresis effect.
Background
The design of antistatic protection for high voltage circuits has been a technical challenge because the core of the high voltage circuit: the high voltage device (24 e.g., LDMOS) itself is not suitable for antistatic protection design as a conventional low voltage device because the hysteresis effect curve of the high voltage device exhibits poor characteristics. As shown in fig. 1, the following defects can be derived from the hysteresis effect curve of the conventional high-voltage device:
1) The maintenance voltage (Vh) is too low, which is often much lower than the working voltage of the high-voltage circuit, and the latch-up effect is easily caused when the high-voltage circuit works normally;
2) The secondary breakdown current (thermal breakdown current, it 2) is too low because the LDMOS experiences local current crowding (Localized Current Crowding) due to device structural characteristics when discharging the ESD current.
Therefore, when the high-voltage circuit antistatic protection design is solved in the industry, two ideas are adopted to realize the protection: 1) The structure of the high-voltage device used for the anti-static protection module is adjusted, and the hysteresis effect curve of the high-voltage device is optimized, so that the high-voltage device is suitable for the anti-static protection design, but the high-voltage device is difficult to practice due to the structural characteristics of the high-voltage device; 2) The anti-static protection circuit capable of bearing high voltage is formed by connecting a certain number of low-voltage anti-static protection devices in series. Because the characteristics of low voltage anti-static protection devices are relatively easy to adjust and control, the industry, particularly integrated circuit design companies, often prefer a method of using a certain number of low voltage anti-static protection devices in series.
Because of the requirement of the design window of the anti-static protection of the high-voltage circuit, the low-voltage anti-static protection device has certain requirements on the hysteresis effect characteristics, and the smaller and better the hysteresis effect window is, the hysteresis effect is preferably not generated, namely the maintenance voltage and the trigger voltage of the hysteresis effect are basically consistent. The low-voltage PMOS device is a common static protection device without hysteresis effect, and because the parasitic PNP triode current gain when the hysteresis effect occurs is smaller, but the low-voltage PMOS device has the defect that the secondary breakdown current (It 2) of the hysteresis effect is smaller, the industry studies and develops an anti-static protection device without the hysteresis effect and with higher secondary breakdown current.
The industry proposed a novel silicon controlled rectifier (No-Snapback SCR) without hysteresis effect in 2015, as shown in fig. 2, and experimental data of the novel silicon controlled rectifier without hysteresis effect show that when the size (D2) of n+ (28) and p+ (22) reaches a certain degree (4 um), the novel silicon controlled rectifier shows the characteristic without hysteresis effect, as shown in fig. 3, and is very suitable for the requirement of multistage series connection of low-voltage devices for high-voltage circuit antistatic protection design. However, the novel silicon controlled rectifier without hysteresis effect has the defects that the size of a device is relatively large, and particularly when multistage series connection is required, the layout area is relatively large.
Chinese patent No.: CN108183101B discloses a novel scr, which directly connects the original floating n+28 with the anode, so that the probability that n+28 reduces holes from p+20 to be injected into the N Well (n_well 60) and reach the N Well/P Well interface is further reduced, that is, the efficiency of n+28 serving as a guard ring is further improved, so that the width of n+28 can be designed to be smaller, and the layout area is saved; in addition, the n+28 has the function of the N Well (n_well 60) junction point (Pickup), so that the N Well junction point (n+30) in the existing silicon controlled rectifier without hysteresis effect in fig. 2 can be further removed, and the layout area is further saved. Although the layout area is further saved by the scheme, with the trend of miniaturization of devices, the technical requirement that the layout area of the silicon controlled rectifier is further reduced is proposed for higher layout area requirements.
Disclosure of Invention
In the summary section, a series of simplified form concepts are introduced that are all prior art simplifications in the section, which are described in further detail in the detailed description section. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing a silicon controlled rectifier which can reduce the size of an overall device, reduce the layout area and has no hysteresis effect compared with the prior art.
The invention aims to provide a manufacturing method of the silicon controlled rectifier, which can reduce the size of the whole device, reduce the layout area and has no hysteresis effect compared with the prior art.
In order to solve the above technical problems, the present invention provides a scr, comprising:
a P-type semiconductor substrate 80;
An N-well 60 and a P-well 70 formed on the P-type semiconductor substrate 80;
A first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed on the upper portion of the N-well 60;
a second high concentration P-type doped region 24 and a second high concentration N-type doped region 26 formed on the upper portion of the P-well 70;
The third high-concentration P-type doped region 22 is formed above the boundary between the N well 60 and the P well 70;
The first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-well 70 and the second high-concentration N-type doped region 26 form a parasitic NPN triode structure;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
Optionally, the scr further includes:
A first shallow trench isolation 10 adjacent to the first high concentration P-type doped region 20 and formed in the N-well 60 on the left side of the first high concentration P-type doped region 20;
A second shallow trench isolation 12 adjacent to the second high concentration P-type doped region 24 and the third high concentration P-type doped region 22, formed in the P-well 70 between the second high concentration P-type doped region 24 and the third high concentration P-type doped region 22;
A third shallow trench isolation 14 adjacent to the second high concentration P-type doped region 24 and the second high concentration N-type doped region 26, formed in the P-well 70 between the second high concentration P-type doped region 24 and the second high concentration N-type doped region 26 adjacent;
The fourth shallow trench isolation 16 is formed adjacent to the second high concentration N-type doped region 26 in the P-well 70 on the right side of the second high concentration P-type doped region 26.
Optionally, in the scr further described, the first width S ranges from 0.2um to 10um, the second width D1 ranges from 0.2um to 2um, the third width D2 ranges from 0.2um to 5um, the fourth width D3 ranges from 0.2um to 10um, and the fifth width D4 ranges from 0.2um to 10um.
Alternatively, the scr can achieve a characteristic without hysteresis effect by adjusting the sustain voltage by adjusting the third width D2 and the fifth width D4.
Optionally, the scr can adjust the trigger voltage of the hysteresis effect by adjusting the second width D1.
Alternatively, when the scr is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected as an anode of the ESD protection structure through metal, and the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 are connected as a cathode of the ESD protection structure through metal.
In order to solve the above technical problems, the present invention provides a method for manufacturing a silicon controlled rectifier, comprising the following steps:
s1, forming an N well 60 and a P well 70 in a P type semiconductor substrate 80;
S2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well 60, forming a second high-concentration P-type doped region 24 and a second high-concentration N-type doped region 26 in the P well 60, and forming a third high-concentration P-type doped region 22 at the boundary between the N well 60 and the P well 70;
The first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-well 70 and the second high-concentration N-type doped region 26 form a parasitic NPN triode structure;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
Optionally, in the further method for manufacturing a silicon controlled rectifier, a step of manufacturing shallow trench isolation is added between the steps S1 and S2;
The first shallow trench isolation 10 is formed in the N-well 60 at the left side of the first high-concentration P-type doped region 20 and is adjacent to the first high-concentration P-type doped region 20;
The second shallow trench isolation 12 is formed in the P-well 70 between the second high-concentration P-type doped region 24 and the third high-concentration P-type doped region 22, and is adjacent to the second high-concentration P-type doped region 24 and the third high-concentration P-type doped region 22;
the third shallow trench isolation 14 is formed in the P-well 70 between the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 adjacent, and is adjacent to the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26;
The fourth shallow trench isolation 16 is formed in the P-well 70 on the right side of the second high concentration P-type doped region 26 and is adjacent to the second high concentration N-type doped region 26.
Alternatively, in the method for manufacturing a silicon controlled rectifier, the first width S ranges from 0.2um to 10um, the second width D1 ranges from 0.2um to 2um, the third width D2 ranges from 0.2um to 5um, the fourth width D3 ranges from 0.2um to 10um, and the fifth width D4 ranges from 0.2um to 10um.
Alternatively, in the further described method for manufacturing a scr, the third width D2 and the fifth width D4 are adjusted to adjust the sustain voltage to achieve the characteristic of no hysteresis effect.
Optionally, in the method for manufacturing the silicon controlled rectifier, the trigger voltage during hysteresis is adjusted by adjusting the second width D1.
Alternatively, the further described method for manufacturing the scr is used for ESD protection, where the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected by metal to serve as an anode of the ESD protection structure, and the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 are connected by metal to serve as a cathode of the ESD protection structure.
The invention improves the high-concentration N-type doped region connected with the cathode in the silicon controlled rectifier without hysteresis effect shown in the prior art figure 4 into the high-concentration P-type doped region 24, and the high-concentration P-type doped region is changed into the high-concentration N-type doped region 26, and the high-concentration P-type doped region 24 can reduce the efficiency that electrons are injected into the P well 70 from the emitter high-concentration N-type doped region 26 of the parasitic NPN triode and migrate to reach the interface of the P well 70/N well 60, so that the current gain of the parasitic NPN (second high-concentration N-type doped region 26/P well 70/N well 60) triode can be reduced, the product of the current gain of the parasitic PNP and the NPN triode can be further reduced, the critical dimensions D2 and D4 of the device required by realizing no hysteresis effect can be reduced, and the whole size of the device can be reduced, thereby achieving the purpose of saving the layout area.
Drawings
The accompanying drawings are intended to illustrate the general features of methods, structures and/or materials used in accordance with certain exemplary embodiments of the invention, and supplement the description in this specification. The drawings of the present invention, however, are schematic illustrations that are not to scale and, thus, may not be able to accurately reflect the precise structural or performance characteristics of any given embodiment, the present invention should not be construed as limiting or restricting the scope of the numerical values or attributes encompassed by the exemplary embodiments according to the present invention. The invention is described in further detail below with reference to the attached drawings and detailed description:
Fig. 1 is a schematic diagram of a conventional high voltage device LDMOS hysteresis effect curve.
Fig. 2 is a schematic diagram of a first conventional silicon controlled rectifier without hysteresis effect.
Fig. 3 is a schematic diagram showing a relationship between hysteresis effect curves D2 of the non-hysteresis effect scr shown in fig. 2.
Fig. 4 is a schematic diagram of a second prior art scr without hysteresis effect.
Fig. 5 is a schematic view of the structure of the present invention.
Description of the reference numerals
20. 22, 26 Represent different high concentration P-type doped regions
24. 28, 30 Denote different high concentration N-type doped regions
10. 12, 14, 16 Represent different shallow trench isolations
60 Denotes an N-well
70 Denotes a P-well
80 Denotes a P-type semiconductor substrate
A represents an anode
C represents a cathode
S represents the width between the first high concentration P-type doped region 20 and the first high concentration N-type doped region 28
D1 represents the width between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22
D2 represents the width of the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22 in the prior art structure;
d3 represents the width of the third high concentration P-type doped region 22 in the structure of the present invention
D4 represents the width of the second high concentration P-type doped region 24 in the structure of the present invention.
Detailed Description
Other advantages and technical effects of the present invention will become more fully apparent to those skilled in the art from the following disclosure, which is a detailed description of the present invention given by way of specific examples. The invention may be practiced or carried out in different embodiments, and details in this description may be applied from different points of view, without departing from the general inventive concept. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solution of these exemplary embodiments to those skilled in the art.
Furthermore, it will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of the example embodiments of the present invention.
A first embodiment;
as shown in reference to fig. 5, the present invention provides a silicon controlled rectifier comprising:
a P-type semiconductor substrate 80;
An N-well 60 and a P-well 70 formed on the P-type semiconductor substrate 80;
A first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed on the upper portion of the N-well 60;
a second high concentration P-type doped region 24 and a second high concentration N-type doped region 26 formed on the upper portion of the P-well 70;
The third high-concentration P-type doped region 22 is formed above the boundary between the N well 60 and the P well 70;
The first high-concentration P-type doped region 20, the N well 60 and the P well 70 form a parasitic PNP triode structure, and the N well 60, the P well 70 and the second high-concentration N-type doped region 26 form a parasitic NPN triode structure;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
The invention improves the high-concentration N-type doped region connected with the cathode in the silicon controlled rectifier without hysteresis effect shown in the prior art figure 4 into the high-concentration P-type doped region 24, and the high-concentration P-type doped region is changed into the high-concentration N-type doped region 26, and the high-concentration P-type doped region 24 can reduce the efficiency that electrons are injected into the P well 70 from the emitter extremely high-concentration N-type doped region 26 of the parasitic NPN and migrate to reach the interface of the P well 70/N well 60, so that the current gain of the parasitic NPN (second high-concentration N-type doped region 26/P well 70/N well 60) triode can be reduced, the product of the current gain of the parasitic PNP and NPN triode can be further reduced, the width of the first high-concentration N-type doped region 28 and the width of the second high-concentration P-type doped region 24 of the critical dimension of the device required by realizing no hysteresis effect can be reduced, and the overall dimension of the device can be reduced, thereby, and the layout area can be saved.
A second embodiment;
with continued reference to fig. 5, the present invention provides a silicon controlled rectifier comprising:
a P-type semiconductor substrate 80;
An N-well 60 and a P-well 70 formed on the P-type semiconductor substrate 80;
A first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed on the upper portion of the N-well 60;
a second high concentration P-type doped region 24 and a second high concentration N-type doped region 26 formed on the upper portion of the P-well 70;
The third high-concentration P-type doped region 22 is formed above the boundary between the N well 60 and the P well 70;
A first shallow trench isolation 10 adjacent to the first high concentration P-type doped region 20 and formed in the N-well 60 on the left side of the first high concentration P-type doped region 20;
A second shallow trench isolation 12 adjacent to the second high concentration P-type doped region 24 and the third high concentration P-type doped region 22, formed in the P-well 70 between the second high concentration P-type doped region 24 and the third high concentration P-type doped region 22;
A third shallow trench isolation 14 adjacent to the second high concentration P-type doped region 24 and the second high concentration N-type doped region 26, formed in the P-well 70 between the second high concentration P-type doped region 24 and the second high concentration N-type doped region 26 adjacent;
fourth shallow trench isolation 16 adjacent to second high concentration N-type doped region 26 formed in P-well 70 on the right side of second high concentration P-type doped region 26;
the first high-concentration P-type doped region 20, the N well 60 and the P well 70 form an equivalent PNP triode structure, and the N well 60, the P well 70 and the second high-concentration N-type doped region 26 form an equivalent NPN triode structure;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
Wherein the range of the first width S is 0.2 um-10 um, the range of the second width D1 is 0.2 um-2 um, the range of the third width D2 is 0.2 um-5 um, the range of the fourth width D3 is 0.2 um-10 um, and the range of the fifth width D4 is 0.2 um-10 um.
It should be further noted that, in either the first embodiment or the second embodiment, the hysteresis-free characteristic can be achieved by adjusting the sustain voltage by adjusting the first width S, the third width D2, and the fourth width D3.
The first embodiment and the second embodiment can achieve the hysteresis-free characteristic by adjusting the sustain voltage by adjusting the third width D2 and the fifth width D4.
The trigger voltage in the hysteresis effect can be adjusted by adjusting the second width D1 in either the first embodiment or the second embodiment.
Accordingly, regardless of whether the first embodiment or the second embodiment is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected as an anode of the ESD protection structure by metal, and the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 are connected as a cathode of the ESD protection structure by metal.
An exemplary embodiment according to the present invention is described herein with reference to a schematic cross-sectional view of a preferred embodiment (and intermediate structure) as an exemplary embodiment. As such, variations from the illustrated shapes, such as due to manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, the implant region, shown as a rectangle, may have rounded or curved features and/or gradient variations in implant concentration at its edges, rather than just binary variations from implant regions to non-implant regions. Also, a buried region formed by implantation may result in some implantation also being present in the region between the buried region and the surface through which the implantation passes. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a respective region in a device and are not intended to limit the scope of an exemplary embodiment in accordance with the present invention.
A third embodiment;
The invention provides a manufacturing method of a silicon controlled rectifier, which comprises the following steps:
s1, forming an N well 60 and a P well 70 in a P type semiconductor substrate 80;
S2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well 60, forming a second high-concentration P-type doped region 24 and a second high-concentration N-type doped region 26 in the P well 60, and forming a third high-concentration P-type doped region 22 at the boundary between the N well 60 and the P well 70;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
A fourth embodiment;
The invention provides a manufacturing method of a silicon controlled rectifier, which comprises the following steps:
s1, forming an N well 60 and a P well 70 in a P type semiconductor substrate 80;
then, performing shallow trench isolation;
The first shallow trench isolation 10 is formed in the N-well 60 at the left side of the first high-concentration P-type doped region 20 and is adjacent to the first high-concentration P-type doped region 20;
the second shallow trench isolation 12 is formed in the P-well 70 between the second high-concentration P-type doped region 2424 and the third high-concentration P-type doped region 22 and is adjacent to the second high-concentration P-type doped region 2424 and the third high-concentration P-type doped region 22;
the third shallow trench isolation 14 is formed in the P-well 70 between the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 adjacent, and is adjacent to the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26;
The fourth shallow trench isolation 16 is formed in the P-well 70 on the right side of the second high concentration P-type doped region 26 and is adjacent to the second high concentration N-type doped region 26.
S2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well 60, forming a second high-concentration P-type doped region 24 and a second high-concentration N-type doped region 26 in the P well 60, and forming a third high-concentration P-type doped region 22 at the boundary between the N well 60 and the P well 70;
An N-well 60 of a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 of a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the first high-concentration N-type doped region 28 has a third width D2, the third high-concentration P-type doped region 22 has a fourth width D3, and the second high-concentration P-type doped region 24 has a fifth width D4.
Wherein the range of the first width S is 0.2 um-10 um, the range of the second width D1 is 0.2 um-2 um, the range of the third width D2 is 0.2 um-5 um, the range of the fourth width D3 is 0.2 um-10 um, and the range of the fifth width D4 is 0.2 um-10 um.
It should be further noted that, in either the third embodiment or the fourth embodiment, the hysteresis-free characteristic can be achieved by adjusting the sustain voltage by adjusting the third width D2 and the fifth width D4.
The trigger voltage in the hysteresis can be adjusted by adjusting the second width D1 in either the third embodiment or the fourth embodiment.
Accordingly, whenever the above-described third embodiment or fourth embodiment is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected as an anode of the ESD protection structure through a metal, and the second high-concentration P-type doped region 24 and the second high-concentration N-type doped region 26 are connected as a cathode of the ESD protection structure through a metal.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail by way of specific embodiments and examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (10)

1. A silicon controlled rectifier, comprising:
a P-type semiconductor substrate (80);
An N-well (60) and a P-well (70) formed on the upper part of the P-type semiconductor substrate (80);
a first high-concentration P-type doped region (20) and a first high-concentration N-type doped region (28) formed on the upper portion of the N well (60);
A second high-concentration P-type doped region (24) and a second high-concentration N-type doped region (26) formed on the upper portion of the P-well (70);
The third high-concentration P-type doped region (22) is formed above the boundary of the N well (60) and the P well (70);
An N well (60) with a first width (S) is formed between the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28), an N well (60) with a second width (D1) is formed between the first high-concentration N-type doped region (28) and the third high-concentration P-type doped region (22), the first high-concentration N-type doped region (28) has a third width (D2), the third high-concentration P-type doped region (22) has a fourth width (D3), and the second high-concentration P-type doped region (24) has a fifth width (D4);
The first high-concentration P-type doped region (20), the N well (60) and the P well (70) form a parasitic PNP triode structure, and the N well (60), the P well (70) and the second high-concentration N-type doped region (26) form a parasitic NPN triode structure;
When the semiconductor device is used for ESD protection, the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28) are connected through metal to serve as an anode of an ESD protection structure, and the second high-concentration P-type doped region (24) and the second high-concentration N-type doped region (26) are connected through metal to serve as a cathode of the ESD protection structure.
2. The silicon controlled rectifier of claim 1 further comprising:
a first shallow trench isolation (10) adjacent to the first high-concentration P-type doped region (20) and formed in the N-well (60) on the left side of the first high-concentration P-type doped region (20);
A second shallow trench isolation (12) adjacent to the second high concentration P-type doped region (24) and the third high concentration P-type doped region (22), formed in the P-well (70) between the second high concentration P-type doped region (24) and the third high concentration P-type doped region (22);
A third shallow trench isolation (14) adjacent to the second high concentration P-type doped region (24) and the second high concentration N-type doped region (26), formed in the P-well (70) between the second high concentration P-type doped region (24) and the second high concentration N-type doped region (26) adjacent;
And a fourth shallow trench isolation (16) adjacent to the second high concentration N-type doped region (26) and formed in the P-well (70) on the right side of the second high concentration P-type doped region (26).
3. The silicon controlled rectifier of claim 1 wherein: the first width (S) ranges from 0.2um to 10um, the second width (D1) ranges from 0.2um to 2um, the third width (D2) ranges from 0.2um to 5um, the fourth width (D3) ranges from 0.2um to 10um, and the fifth width (D4) ranges from 0.2um to 10um.
4. The silicon controlled rectifier of claim 1 wherein: which can realize the hysteresis-free characteristic by adjusting the sustain voltage by adjusting the third width (D2) and the fifth width (D4).
5. The silicon controlled rectifier of claim 1 wherein: the trigger voltage of the hysteresis effect can be adjusted by adjusting the second width (D1).
6. A method of manufacturing a silicon controlled rectifier comprising the steps of:
s1, forming an N well (60) and a P well (70) in a P type semiconductor substrate (80);
S2, forming a first high-concentration P-type doped region (20) and a first high-concentration N-type doped region (28) in an N well (60), forming a second high-concentration P-type doped region (24) and a second high-concentration N-type doped region (26) in the P well (60), and forming a third high-concentration P-type doped region (22) at the boundary of the N well (60) and the P well (70);
An N well (60) with a first width (S) is formed between the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28), an N well (60) with a second width (D1) is formed between the first high-concentration N-type doped region (28) and the third high-concentration P-type doped region (22), the first high-concentration N-type doped region (28) has a third width (D2), the third high-concentration P-type doped region (22) has a fourth width (D3), and the second high-concentration P-type doped region (24) has a fifth width (D4); the first high-concentration P-type doped region (20), the N well (60) and the P well (70) form a parasitic PNP triode structure, and the N well (60), the P well (70) and the second high-concentration N-type doped region (26) form a parasitic NPN triode structure;
When the semiconductor device is used for ESD protection, the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28) are connected through metal to serve as an anode of an ESD protection structure, and the second high-concentration P-type doped region (24) and the second high-concentration N-type doped region (26) are connected through metal to serve as a cathode of the ESD protection structure.
7. The method of manufacturing a silicon controlled rectifier as defined in claim 6, wherein: adding a step of manufacturing shallow trench isolation between the steps S1 and S2;
A first shallow trench isolation (10) formed in the N-well (60) on the left side of the first high-concentration P-type doped region (20) and adjacent to the first high-concentration P-type doped region (20);
The second shallow trench isolation (12) is formed in the P-well (70) between the second high-concentration P-type doped region (24) and the third high-concentration P-type doped region (22) and is adjacent to the second high-concentration P-type doped region (24) and the third high-concentration P-type doped region (22);
The third shallow trench isolation (14) is formed in the P well (70) between the second high-concentration P-type doped region (24) and the second high-concentration N-type doped region (26) adjacent, and is adjacent to the second high-concentration P-type doped region (24) and the second high-concentration N-type doped region (26);
the fourth shallow trench isolation (16) is formed in the P-well (70) on the right side of the second high concentration P-type doped region (26) and is adjacent to the second high concentration N-type doped region (26).
8. The method of manufacturing a silicon controlled rectifier as defined in claim 7, wherein: the first width (S) ranges from 0.2um to 10um, the second width (D1) ranges from 0.2um to 2um, the third width (D2) ranges from 0.2um to 5u m, the fourth width (D3) ranges from 0.2um to 10um, and the fifth width (D4) ranges from 0.2um to 10um.
9. The method of manufacturing a silicon controlled rectifier as defined in claim 7, wherein: the hysteresis-free characteristic is achieved by adjusting the sustain voltage by adjusting the third width (D2) and the fifth width (D4).
10. The method of manufacturing a silicon controlled rectifier as defined in claim 7, wherein: the trigger voltage at the time of its hysteresis is adjusted by adjusting the second width (D1).
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101807598A (en) * 2010-03-17 2010-08-18 浙江大学 PNPNP type triac
KR20130011027A (en) * 2011-07-20 2013-01-30 단국대학교 산학협력단 Esd protection device
CN108091650A (en) * 2017-12-28 2018-05-29 上海华力微电子有限公司 Without echo effect thyristor type esd protection structure and its implementation
CN108183101A (en) * 2017-12-28 2018-06-19 上海华力微电子有限公司 Without echo effect thyristor type esd protection structure and its implementation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101807598A (en) * 2010-03-17 2010-08-18 浙江大学 PNPNP type triac
KR20130011027A (en) * 2011-07-20 2013-01-30 단국대학교 산학협력단 Esd protection device
CN108091650A (en) * 2017-12-28 2018-05-29 上海华力微电子有限公司 Without echo effect thyristor type esd protection structure and its implementation
CN108183101A (en) * 2017-12-28 2018-06-19 上海华力微电子有限公司 Without echo effect thyristor type esd protection structure and its implementation

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